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Rob Clark [Tue, 2 Dec 2014 22:38:12 +0000 (17:38 -0500)]
freedreno: fix signed vs unsigned lols
Signed-off-by: Rob Clark <robclark@freedesktop.org>
José Fonseca [Wed, 3 Dec 2014 07:48:26 +0000 (07:48 +0000)]
gallivm: Update for RTDyldMemoryManager becoming an unique_ptr.
Trivial.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=86958
Tapani Pälli [Tue, 4 Nov 2014 12:20:15 +0000 (14:20 +0200)]
glsl: throw error when using invariant(all) in a fragment shader
Note that some of the GLSL specifications explicitly state this as
compile error, some simply state that 'it is an error'.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Ben Widawsky [Sat, 22 Nov 2014 23:22:15 +0000 (15:22 -0800)]
i965/skl: Fix SBE state upload code.
The state upload code was incorrectly shifting the attribute swizzles. The
effect of this is we're likely to get the default swizzle values, which disables
the component.
This doesn't technically fix any bugs since Skylake support is still disabled by
default (no PCI IDs).
While here, since VARYING_SLOT_MAX can be greater than the number of attributes
we have available, add a warning to the code to make sure we never do the wrong
thing (and hopefully prevent further static analysis from finding this).
Admittedly I am a bit confused. It seems to me like the moment a user has
greater than 8 varyings we will hit this condition. CC Ken to clarify.
v2: Forgot to git add the warning message in v1
v3: Change the > 31 varyings to an assertion (Ken)
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> (via Coverity)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jan Vesely [Tue, 2 Dec 2014 19:47:53 +0000 (14:47 -0500)]
r600, llvm: Don't leak global symbol offsets
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Matt Turner [Tue, 2 Dec 2014 19:18:47 +0000 (11:18 -0800)]
i965: Avoid union literal, for old gcc compatibility.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 12 Nov 2014 18:17:36 +0000 (10:17 -0800)]
i965: Remove tabs from instruction scheduler.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Kenneth Graunke [Mon, 1 Dec 2014 09:09:35 +0000 (01:09 -0800)]
i965/vs: Set brw_vs_prog_key::clamp_vertex_color to 0 when irrelevant.
Vertex color clamping is only relevant if the shader writes to
the built-in gl_[Secondary]{Front,Back}Color varyings. Otherwise,
brw_vs_prog_key::clamp_vertex_color is never used, so we can simply
leave it set to 0.
This enables us to correctly predict the clamp_vertex_color key value
in the precompile for shaders which don't use those varyings.
Eliminates virtually all VS recompiles in Serious Sam 3's intro.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Mon, 1 Dec 2014 09:01:02 +0000 (01:01 -0800)]
i965: Make vertex color clamp handling code VS specific.
Vertex color clamping only applies to gl_[Secondary]{Front,Back}Color,
which are compatibility-only built-in varyings. We only support GS in
core profile, so they can't exist in geometry shaders.
We can drop several dirty bits from the GS program key - they're
unnecessary for a core profile implementation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Mon, 1 Dec 2014 08:53:02 +0000 (00:53 -0800)]
i965/vs: Handle vertex color clamping in emit_urb_slot().
Vertex color clamping only applies to a few specific built-ins: COL0/1
and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to
handle special cases in a function called emit_generic_urb_slot().
emit_urb_slot() is all about handling special cases, so it makes more
sense to handle this there.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 2 Dec 2014 06:23:22 +0000 (22:23 -0800)]
i965: Use the enum type for gen6_gather_wa sampler key field.
Requested by Matt Turner.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 29 Oct 2014 01:48:49 +0000 (18:48 -0700)]
i965: Drop use of GL types in program keys.
This is really far removed from the API; we should just use C types.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Wed, 29 Oct 2014 01:13:49 +0000 (18:13 -0700)]
i965: Move program key structures to brw_program.h.
With fs_visitor/fs_generator being reused for SIMD8 VS/GS programs,
we're running into weird #include patterns, where scalar code #includes
brw_vec4.h and such.
Program keys aren't really related to SIMD4X2/SIMD8 execution - they
mostly capture NOS for a particular shader stage. Consolidating them
all in one place that's vec4/scalar neutral should help avoid problems.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 25 Nov 2014 08:35:31 +0000 (00:35 -0800)]
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 07:57:48 +0000 (23:57 -0800)]
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 07:30:51 +0000 (23:30 -0800)]
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 1 Dec 2014 05:58:03 +0000 (21:58 -0800)]
i965: Remove "disable_derivative_optimization" driconf option.
This was added in September 2013 when we first implemented the fast
(but lower quality) derivatives. A quick Google search didn't turn
up anyone using or recommending the option, so I suspect no one does.
Applications that want to control the quality of their derivatives can
use the new GL_ARB_derivative_control extension, or use the glHint
mechanism. The driconf option seems superfluous.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 11 Nov 2014 14:10:06 +0000 (14:10 +0000)]
i965: Just return void from brw_try_draw_prims
Note from Ken:
"We used to use the return value to indicate whether software
fallbacks were necessary, but we haven't in years."
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 11 Nov 2014 10:21:50 +0000 (10:21 +0000)]
mesa: Use current Mesa coding style in check_valid_to_render
This makes some others patches (still in my local tree) a bit cleaner.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 11 Nov 2014 10:20:49 +0000 (10:20 +0000)]
mesa: Use unreachable instead of assert in check_valid_to_render
This is generally the prefered style these days.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 11 Nov 2014 09:50:55 +0000 (09:50 +0000)]
mesa: Silence unused parameter warnings in _mesa_validate_Draw functions
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawElements':
../../src/mesa/main/api_validate.c:376:37: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_MultiDrawElements':
../../src/mesa/main/api_validate.c:394:65: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawRangeElements':
../../src/mesa/main/api_validate.c:452:35: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawArrays':
../../src/mesa/main/api_validate.c:473:25: warning: unused parameter 'start' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawElementsInstanced':
../../src/mesa/main/api_validate.c:590:44: warning: unused parameter 'basevertex' [-Wunused-parameter]
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 11 Nov 2014 09:44:46 +0000 (09:44 +0000)]
mesa: Refactor common validation code to validate_DrawElements_common
Most of the code in _mesa_validate_DrawElements,
_mesa_validate_DrawRangeElements, and
_mesa_validate_DrawElementsInstanced was the same. Refactor this out to
common code.
As a side-effect, a bug in _mesa_validate_DrawElementsInstanced was
fixed. Previously this function would not generate an error when
check_valid_to_render failed if numInstances was 0.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 11 Nov 2014 10:53:37 +0000 (10:53 +0000)]
mesa: Generate GL_INVALID_OPERATION when drawing w/o a VAO in core profile
GL 3-ish versions of the spec are less clear that an error should be
generated here, so Ken (and I during review) just missed it in
1afe335.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Tue, 2 Dec 2014 16:41:20 +0000 (09:41 -0700)]
mesa: fix height error check for 1D array textures
height=0 is legal for 1D array textures (as depth=0 is legal for
2D arrays). Fixes new piglit ext_texture_array-errors test.
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Jan Vesely [Tue, 4 Nov 2014 01:29:36 +0000 (20:29 -0500)]
r600, llvm: Fix mem leak
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
EdB [Fri, 7 Nov 2014 09:30:40 +0000 (10:30 +0100)]
clover: clCompileProgram CL_INVALID_COMPILER_OPTIONS
clCompileProgram should return CL_INVALID_COMPILER_OPTIONS
instead of CL_INVALID_BUILD_OPTIONS
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Eric Anholt [Mon, 1 Dec 2014 19:48:20 +0000 (11:48 -0800)]
vc4: Pair up QPU instructions when scheduling.
We've got two mostly-independent operations in each QPU instruction, so
try to pack two operations together. This is fairly naive (doesn't track
read and write separately in instructions, doesn't convert ADD-based MOVs
into MUL-based movs, doesn't reorder across uniform loads), but does show
a decent improvement on shader-db-2.
total instructions in shared programs: 59583 -> 57651 (-3.24%)
instructions in affected programs: 47361 -> 45429 (-4.08%)
Dave Airlie [Fri, 28 Nov 2014 00:49:48 +0000 (00:49 +0000)]
r600g/sb: fix issues cause by GLSL switching to loops for switch
Since
73dd50acf6d244979c2a657906aa56d3ac60d550
glsl: implement switch flow control using a loop
The SB backend was falling over in an assert or crashing.
Tracked this down to the loops having no repeats, but requiring
a working break, initial code just called the loop handler for
all non-if statements, but this caused a regression in
tests/shaders/dead-code-break-interaction.shader_test.
So I had to add further code to detect if all the departure
nodes are empty and avoid generating an empty loop for that case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86089
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-By: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Mon, 1 Dec 2014 23:20:48 +0000 (18:20 -0500)]
freedreno/a4xx: alpha blend fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 1 Dec 2014 22:44:36 +0000 (17:44 -0500)]
freedreno/a4xx: fix DRAW initiator encoding of index size
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 1 Dec 2014 22:41:21 +0000 (17:41 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Matt Turner [Mon, 3 Nov 2014 04:36:53 +0000 (20:36 -0800)]
i965/vec4: Rewrite dead code elimination to use live in/out.
Improves 359 shaders by >=10%
114 shaders by >=20%
91 shaders by >=30%
82 shaders by >=40%
22 shaders by >=50%
4 shaders by >=60%
2 shaders by >=80%
total instructions in shared programs:
5845346 ->
5822422 (-0.39%)
instructions in affected programs: 364979 -> 342055 (-6.28%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 3 Nov 2014 05:16:44 +0000 (21:16 -0800)]
i965/vec4: Track liveness of the flag register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 3 Nov 2014 19:24:03 +0000 (11:24 -0800)]
i965/fs: Remove opt_drop_redundant_mov_to_flags().
Dead code elimination now handles this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 29 Oct 2014 20:58:45 +0000 (13:58 -0700)]
i965/fs: Use const fs_reg & rather than a copy or pointer.
Also while we're touching var_from_reg, just make it an inline function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 29 Oct 2014 03:12:21 +0000 (20:12 -0700)]
i965/fs: Dead code eliminate instructions writing the flag.
Most prominently helps Natural Selection 2, which has a surprising
number shaders that do very complicated things before drawing black.
instructions in affected programs: 21052 -> 16978 (-19.35%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 29 Oct 2014 02:53:53 +0000 (19:53 -0700)]
i965/fs: Track liveness of the flag register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 29 Oct 2014 20:35:16 +0000 (13:35 -0700)]
i965: Use local pointer to block_data in live intervals.
The next patch will be simplified because of this, and makes reading the
code a lot easier.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 29 Oct 2014 20:27:37 +0000 (13:27 -0700)]
i965/vec4: Make live_intervals part of the vec4_visitor class.
Like in fs_visitor.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 12 Nov 2014 02:02:23 +0000 (18:02 -0800)]
i965/fs: Treat the FB_WRITE as predicated if we're discarding.
Pre-Haswell hardware couldn't actually predicate it, but it's easier to
pretend as if it's predicated in the visitor since it will generate a
MOV from f0.1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Tue, 11 Nov 2014 23:56:58 +0000 (15:56 -0800)]
i965: Don't treat IF or WHILE with cmod as writing the flag.
Sandybridge's IF and WHILE instructions can do an embedded comparison
with conditional mod.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 3 Nov 2014 17:23:33 +0000 (09:23 -0800)]
i965/disasm: Disassemble tdr and tm registers properly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Mon, 24 Nov 2014 21:56:29 +0000 (13:56 -0800)]
main, glsl: Bump max known desktop glsl version to 4.50
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jordan Justen [Mon, 20 Oct 2014 23:23:51 +0000 (16:23 -0700)]
glsl/cs: Change gl_WorkGroupSize from ivec3 to uvec3
As documented in:
https://www.opengl.org/registry/specs/ARB/compute_shader.txt
const uvec3 gl_WorkGroupSize;
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jonathan Gray [Sat, 29 Nov 2014 08:00:51 +0000 (19:00 +1100)]
i965: avoid anonymous struct in float <-> VF conversions
Anonymous structures are only supported with newer versions of
GCC. They will not work with GCC 4.2.1 used by OpenBSD or
GCC 4.4.7 shipped with RHEL6 going by a commit to fix a similiar
problem in radeonsi earlier in the year
(
74388dd24bc7fdb9e62ec18096163f5426e03fbf).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Brian Paul [Fri, 5 Sep 2014 21:20:00 +0000 (15:20 -0600)]
mesa: fix arithmetic error in _mesa_compute_compressed_pixelstore()
We need parenthesis around the expression which computes the number of
blocks per row.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Brian Paul [Mon, 1 Dec 2014 20:41:47 +0000 (13:41 -0700)]
vbo: also print buffer object pointer in vbo_print_vertex_list()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Mon, 1 Dec 2014 20:41:47 +0000 (13:41 -0700)]
mesa: some improvements for print_list()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Mon, 1 Dec 2014 20:41:47 +0000 (13:41 -0700)]
mesa: inline/remove _mesa_polygon_stipple()
Was not called from any other place.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Mon, 1 Dec 2014 20:41:47 +0000 (13:41 -0700)]
svga: fix comment typo
Brian Paul [Mon, 1 Dec 2014 20:38:14 +0000 (13:38 -0700)]
mesa: remove unused functions in prog_execute.c
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Mon, 1 Dec 2014 20:36:14 +0000 (13:36 -0700)]
mesa: update glext.h to version
20141118
Brian Paul [Mon, 1 Dec 2014 20:34:15 +0000 (13:34 -0700)]
gallium: add include path to fix building of pipe-loader code
The pipe-loader code wasn't finding util/u_atomic.h
Reviewed-by: Matt Turner <mattst88@gmail.com>
José Fonseca [Mon, 1 Dec 2014 20:24:06 +0000 (20:24 +0000)]
graw: Avoid 'near'/'far' variables.
They are defined by windows.h, which got included slightly more
frequently than before with u_atomic.h
Matt Turner [Fri, 21 Nov 2014 07:45:38 +0000 (23:45 -0800)]
i965/fs: Clean up some whitespace in reg_allocate.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Fri, 21 Nov 2014 07:46:03 +0000 (23:46 -0800)]
ra: Don't use regs as the ralloc context.
The i965 backends pass something out of 'screen', which is allocated
per-process, making using this as a ralloc context not thread-safe.
All callers ra_alloc_interference_graph() already ralloc_free() its
return value.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Sat, 22 Nov 2014 02:05:40 +0000 (18:05 -0800)]
i965: Initialize INTEL_DEBUG once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Sat, 22 Nov 2014 02:04:51 +0000 (18:04 -0800)]
i965: Initialize compaction tables once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Sat, 22 Nov 2014 02:04:21 +0000 (18:04 -0800)]
glsl: Initialize static temporaries_allocate_names once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
José Fonseca [Tue, 25 Nov 2014 14:25:28 +0000 (14:25 +0000)]
util/u_atomic: Fix the unlocked implementation.
It was totally broken:
- p_atomic_dec_zero() was returning the negation of the expected value
- p_atomic_inc_return()/p_atomic_dec_return() was
post-incrementing/decrementing, hence returning the old value instead
of the new
- p_atomic_cmpxchg() was returning the new value on success, instead of
the old
It is clear this never used in the past. I wonder if it wouldn't be better to
yank it altogether.
Reviewed-by: Matt Turner <mattst88@gmail.com>
José Fonseca [Tue, 25 Nov 2014 14:17:29 +0000 (14:17 +0000)]
util/u_atomic: Add a simple test.
It was much easier for me to verify things build and run as expected
with this simple test, than building and testing whole Mesa.
With scons the test can be build and run merely by doing:
scons u_atomic_test
Building the test with autotools is left as a future exercise.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Sat, 22 Nov 2014 00:33:40 +0000 (16:33 -0800)]
util: Make u_atomic.h typeless.
like how C11's stdatomic.h provides generic functions. GCC's __sync_*
builtins already take a variety of types, so that's simple.
MSVC and Sun Studio don't, but we can implement it with something that
looks a little crazy but is actually quite readable.
Thanks to Jose for some MSVC fixes!
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Sat, 22 Nov 2014 00:44:43 +0000 (16:44 -0800)]
util: Use stdbool.h's bool rather than "boolean".
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Sat, 22 Nov 2014 00:28:21 +0000 (16:28 -0800)]
util: Remove u_atomic.h's GCC inline assembly.
GCC >= 4.1 support the __sync_* intrinsics. That seems like a
sufficiently old baseline.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Fri, 21 Nov 2014 23:51:42 +0000 (15:51 -0800)]
util: Remove u_atomic.h's MSVC inline assembly.
There was already an intrinsics path that implemented all of the same
functions, plus more.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Fri, 21 Nov 2014 23:50:58 +0000 (15:50 -0800)]
util: Remove u_atomic.h's Gallium dependence.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Fri, 21 Nov 2014 23:47:44 +0000 (15:47 -0800)]
util: s/INLINE/inline/ in u_atomic.h.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Fri, 21 Nov 2014 23:37:54 +0000 (15:37 -0800)]
util: Move u_atomic.h to src/util.
To be shared outside of Gallium.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Wed, 26 Nov 2014 20:44:19 +0000 (12:44 -0800)]
vc4: Introduce scheduling of QPU instructions.
This doesn't reschedule much currently, just tries to fit things into the
regfile A/B write-versus-read slots (the cause of the improvements in
shader-db), and hide texture fetch latency by scheduling setup early and
results collection late (haven't performance tested it). This
infrastructure will be important for doing instruction pairing, though.
shader-db2 results:
total instructions in shared programs: 61874 -> 59583 (-3.70%)
instructions in affected programs: 50677 -> 48386 (-4.52%)
Eric Anholt [Wed, 26 Nov 2014 20:51:27 +0000 (12:51 -0800)]
vc4: Drop the explicit scoreboard wait.
This is actually implicitly handled by the TLB operations.
Eric Anholt [Sun, 30 Nov 2014 23:13:40 +0000 (15:13 -0800)]
vc4: Also deal with VPM reads at thread end.
Prevents a regression with QPU scheduling, which happens to put the no-op
reads for unused VPM contents end up at the end of the program.
Eric Anholt [Sun, 30 Nov 2014 21:25:16 +0000 (13:25 -0800)]
vc4: Fix assertion about SFU versus texturing.
We're supposed to be checking that nothing else writes r4, which is done
by the TMU result collection signal, not the coordinate setup.
Avoids a regression when QPU instruction scheduling is introduced.
Eric Anholt [Thu, 27 Nov 2014 01:01:59 +0000 (17:01 -0800)]
vc4: Add another check for invalid TLB scoreboard handling.
This was caught by an assertion in the simulator.
Rob Clark [Mon, 1 Dec 2014 16:55:36 +0000 (11:55 -0500)]
freedreno/a4xx: invalidate cache when vbo's change
Otherwise vertex shader can see stale cache data. This in particular
happens when the same vbo is updated and reused. Not sure yet if vbo's
at differing addresses but bound to same vertex buffer slot could have
issues, but seems safest to flush whenever new vertex buffers are bound.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Sun, 30 Nov 2014 03:12:12 +0000 (22:12 -0500)]
st/mesa: avoid exposing EXT_texture_integer for pre-GLSL 1.30
For drivers building up to GL(ES)3, only expose the actual extension if
the API will let it be used (e.g. via overrides/debug flags that enable
higher versions).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sat, 29 Nov 2014 07:14:35 +0000 (02:14 -0500)]
freedreno/a3xx: add missing integer formats and enable rendering
The mesa state tracker doesn't fall back on similar integer formats, so
they must all be provided. Remove the restriction against integer color
rendering.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 30 Nov 2014 00:24:35 +0000 (19:24 -0500)]
freedreno/a3xx: enable sampling from integer textures
We need to produce a u32 destination type on integer sampling
instructions, so keep that in a shader key set based on the
currently-bound textures.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 30 Nov 2014 00:21:33 +0000 (19:21 -0500)]
freedreno: allow each generation to hook into sampler view setting
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 29 Nov 2014 07:13:07 +0000 (02:13 -0500)]
freedreno/a3xx: don't use half precision shaders for int/float32
Integer outputs end up getting mangled due to cov.f32f16, and float32
loses precision. Use full precision shaders in both of those cases.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 29 Nov 2014 07:10:15 +0000 (02:10 -0500)]
freedreno/a3xx: disable blending for integer formats
Also add support for the BLENDABLE bind flag, similarly predicated on
non-int formats.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 29 Nov 2014 01:54:30 +0000 (20:54 -0500)]
freedreno/a3xx: remove blend clamp enables from gmem/clears
Just pass the data through unmolested. This probably has no effect since
blending isn't actually enabled.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 28 Nov 2014 19:10:36 +0000 (14:10 -0500)]
freedreno/a3xx: add format to emit info, use to set sint/uint flags
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 29 Nov 2014 22:04:57 +0000 (17:04 -0500)]
freedreno/a3xx: add 16-bit unorm/snorm texture formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 29 Nov 2014 19:01:51 +0000 (14:01 -0500)]
freedreno/ir3: remove unused arg parameter
Leaving it around in the struct in case we want to use it later.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Oct 2014 19:55:12 +0000 (15:55 -0400)]
freedreno/ir3: fix UMAD
Looks like none of the mad variants do u16 * u16 + u32, so just add in
the extra value "by hand".
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Rob Clark [Fri, 28 Nov 2014 16:02:20 +0000 (11:02 -0500)]
freedreno/a4xx: stencil fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 30 Nov 2014 15:42:36 +0000 (10:42 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 29 Nov 2014 13:23:08 +0000 (08:23 -0500)]
freedreno/a4xx: add render target format to fd4_emit
This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 28 Nov 2014 22:30:32 +0000 (17:30 -0500)]
freedreno/a3xx: unify vertex/texture formats into a single table
The table contains all the relevant information about each format. The
helper functions now just do lookups in the table.
Note that this adds support for a lot of formats that were previously
unsupported. Additionally it adds disabled support for integer render
buffers, which will require more work to actually enable.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 28 Nov 2014 22:29:09 +0000 (17:29 -0500)]
freedreno/a3xx: rename vertex/texture format enums to be more consistent
Switch both of them from independently inconsistent conventions to having
UINT/SINT/UNORM/SNORM/FLOAT/FIXED suffixes.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 28 Nov 2014 22:16:24 +0000 (17:16 -0500)]
freedreno/a3xx: fd3_util -> fd3_format
All the "util" helpers are actually format-related
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 28 Nov 2014 21:59:21 +0000 (16:59 -0500)]
freedreno/a3xx: only enable blend clamp for non-float formats
This fixes arb_color_buffer_float-render GL_RGBA16F.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Fri, 26 Sep 2014 18:38:06 +0000 (11:38 -0700)]
i965: Add _CACHE_ in brw_cache_id enum names.
BRW_CACHE_VS_PROG is more easily associated with program caches than
plain BRW_VS_PROG.
While we're at it, rename BRW_WM_PROG to BRW_CACHE_FS_PROG, to move away
from the outdated Windowizer/Masker name.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 26 Sep 2014 17:49:44 +0000 (10:49 -0700)]
i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.
This flag signifies that we've emitted a new SAMPLER_STATE table.
Given that we haven't cached those in years, CACHE_NEW_SAMPLER isn't
a great name. Putting it in the BRW_NEW_* hierarchy would make more
sense; BRW_NEW_SAMPLER_STATE_TABLE better reflects its actual purpose.
When this flag is raised, the pointer to the SAMPLER_STATE table has
changed, so we need to re-issue any packets which point to it (unit
state on Gen4-5, 3DSTATE_SAMPLER_STATE_POINTERS on Gen6, and the
per-stage variants on Gen7+).
Saves 2 * sizeof(void *) bytes per context, as we remove useless
aux_compare/aux_free function pointers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 06:20:29 +0000 (22:20 -0800)]
i965: Move some /* CACHE_NEW_SAMPLER */ comments.
Marking brw_stage_state::sampler_count as CACHE_NEW_SAMPLER is wrong.
The number of samplers used by each program is actually computed at
draw time (brw_try_draw_prims), based purely on the currently bound
shader programs (gl_program::SamplersUsed).
CACHE_NEW_SAMPLER means that we've emitted a new SAMPLER_STATE table.
Although this could indicate that the number of samplers has changed,
it could also simply mean that the contents of the table has changed
(i.e. we've bound different textures).
The real reason these atoms depend on CACHE_NEW_SAMPLER is because they
include a pointer to the SAMPLER_STATE table. This was not commented.
So, move the comments to the appropriate place.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 26 Sep 2014 17:26:09 +0000 (10:26 -0700)]
i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.
We've been streaming these out for ages, so they basically have nothing
to do with brw_state_cache.c.
Saves 6 * sizeof(void *) bytes per context, as we won't have useless
aux_compare/aux_free functions for them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 26 Sep 2014 10:05:10 +0000 (03:05 -0700)]
i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.
These always happen together; the extra atom just means another item to
iterate through, flags to check, and a call through a function pointer.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 26 Sep 2014 08:50:04 +0000 (01:50 -0700)]
i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.
On Gen4-5, unit state is specified as indirect state, rather than
commands. If any unit state changes, we upload it via brw_state_batch
and arrange for 3DSTATE_PIPELINED_POINTERS to be re-emitted, which
updates pointers to all unit state at once.
Since there's only one command and state atom (brw_psp_urb_cs) that
needs to know about this, there's no benefit to having six separate
flags. We can combine CACHE_NEW_*_UNIT into a single flag.
We also haven't cached these in a long time, so it doesn't make sense
to use the "CACHE_NEW_" prefix. Instead, use the "BRW_NEW_" prefix.
This also saves 12 * sizeof(void *) bytes of memory per context, as
we remove useless aux_compare/aux_free functions for each CACHE bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 07:16:56 +0000 (23:16 -0800)]
i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order. Some used
bonus parenthesis. Some put multiple flags on one line, others put one
per line. Some used tabs instead of spaces...but only on some lines.
This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.
Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Christoph Bumiller [Thu, 4 Jul 2013 12:19:18 +0000 (14:19 +0200)]
nv50/ir/tgsi: handle TGSI_OPCODE_ARR
This instruction is used by st/nine.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>