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Chandler Carruth [Sun, 19 Oct 2014 09:06:56 +0000 (09:06 +0000)]
Move previously dead code to handle computing the known bits of an alias
up to where it actually works as intended. The problem is that
a GlobalAlias isa GlobalValue and so the prior block handled all of the
cases.
This allows us to constant fold based on the actual constant expression
in the global alias. As an example, see the last function in the newly
added test case which explicitly aligns an unaligned pointer using
constant expression math. Without this change, we fail to see that and
fold an alignment test to zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220164
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David Majnemer [Sun, 19 Oct 2014 08:32:32 +0000 (08:32 +0000)]
InstCombine: (sub (or A B) (xor A B)) --> (and A B)
The following implements the transformation:
(sub (or A B) (xor A B)) --> (and A B).
Patch by Ankur Garg!
Differential Revision: http://reviews.llvm.org/D5719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220163
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David Majnemer [Sun, 19 Oct 2014 08:23:08 +0000 (08:23 +0000)]
InstCombine: Optimize icmp eq/ne (shl Const2, A), Const1
The following implements the optimization for sequences of the form:
icmp eq/ne (shl Const2, A), Const1
Such sequences can be transformed to:
icmp eq/ne A, (TrailingZeros(Const1) - TrailingZeros(Const2))
This handles only the equality operators for now. Other operators need
to be handled.
Patch by Ankur Garg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220162
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Chandler Carruth [Sun, 19 Oct 2014 08:17:50 +0000 (08:17 +0000)]
Fix a long-standing miscompile in the load analysis that was uncovered
by my refactoring of this code.
The method isSafeToLoadUnconditionally assumes that the load will
proceed with the preferred type alignment. Given that, it has to ensure
that the alloca or global is at least that aligned. It has always done
this historically when a datalayout is present, but has never checked it
when the datalayout is absent. When I refactored the code in r220156,
I exposed this path when datalayout was present and that turned the
latent bug into a patent bug.
This fixes the issue by just removing the special case which allows
folding things without datalayout. This isn't worth the complexity of
trying to tease apart when it is or isn't safe without actually knowing
the preferred alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220161
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Chandler Carruth [Sun, 19 Oct 2014 00:42:16 +0000 (00:42 +0000)]
Switch how the datalayout availability test is handled in this code to
make much more sense and in theory be more correct.
If you trace the code alllll the way back to when it was first
introduced, the comments make it slightly more clear what was going on
here. At that time, the only way Base != V was if DL (then TD) was
non-null. As a consequence, if DL *was* null, that meant we were loading
directly from the alloca or global found above the test. After
refactoring, this has become at least terribly subtle and potentially
incorrect. There are many forms of pointer manipulation that can be
traversed without DataLayout, and some of them would in fact change the
size of object being loaded vs. allocated.
Rather than this subtlety, I've hoisted the actual 'return true' bits
into the code which actually found an alloca or global and based them on
the loaded pointer being that alloca or global. This is both more clear
and safer. I've also added comments about exactly why this set of
predicates is used.
I've also corrected a misleading comment about globals -- if overridden
they may not just have a different size, they may be null and completely
unsafe to load from!
Hopefully this confuses the next reader a bit less. I don't have any
test cases or anything, the patch is motivated strictly to improve the
readability of the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220156
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Bob Wilson [Sun, 19 Oct 2014 00:39:30 +0000 (00:39 +0000)]
Use triple predicate functions instead of checking values directly. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220155
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Chandler Carruth [Sat, 18 Oct 2014 23:47:22 +0000 (23:47 +0000)]
Rename 'TD' to 'DL' in this function as the argument is now a DataLayout
argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220151
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Chandler Carruth [Sat, 18 Oct 2014 23:46:17 +0000 (23:46 +0000)]
Fix the other comment to use modern doxygen style and be a bit more
direct. Notably, comment on the fact that the loaded type is significant
in that it determines how wide of an access must be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220150
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Chandler Carruth [Sat, 18 Oct 2014 23:41:25 +0000 (23:41 +0000)]
More formatting cleanup brought to you by clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220149
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Chandler Carruth [Sat, 18 Oct 2014 23:31:55 +0000 (23:31 +0000)]
Clean up doxygen syntax and reword comments to flow better, have a brief
section, and not have unfinished sentence fragments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220147
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Chandler Carruth [Sat, 18 Oct 2014 23:19:03 +0000 (23:19 +0000)]
Clean up the formatting and trailing whitespace of a routine before
editting it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220146
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Lang Hames [Sat, 18 Oct 2014 22:23:55 +0000 (22:23 +0000)]
[PBQP] Move register-allocation specific PBQP code into RegAllocPBQP.h.
Just clean-up - no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220145
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Lang Hames [Sat, 18 Oct 2014 17:26:07 +0000 (17:26 +0000)]
[PBQP] Replace the interference-constraints algorithm with a faster version
loosely based on linear scan.
On x86-64 this is good for a ~2% drop in compile time on the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220143
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Chandler Carruth [Sat, 18 Oct 2014 11:00:12 +0000 (11:00 +0000)]
Preserve AA metadata when combining (cast (load (...))) -> (load (cast
(...))).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220141
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Chandler Carruth [Sat, 18 Oct 2014 06:36:22 +0000 (06:36 +0000)]
[InstCombine] Do an about-face on how LLVM canonicalizes (cast (load
...)) and (load (cast ...)): canonicalize toward the former.
Historically, we've tried to load using the type of the *pointer*, and
tried to match that type as closely as possible removing as many pointer
casts as we could and trading them for bitcasts of the loaded value.
This is deeply and fundamentally wrong.
Repeat after me: memory does not have a type! This was a hard lesson for
me to learn working on SROA.
There is only one thing that should actually drive the type used for
a pointer, and that is the type which we need to use to load from that
pointer. Matching up pointer types to the loaded value types is very
useful because it minimizes the physical size of the IR required for
no-op casts. Similarly, the only thing that should drive the type used
for a loaded value is *how that value is used*! Again, this minimizes
casts. And in fact, the *only* thing motivating types in any part of
LLVM's IR are the types used by the operations in the IR. We should
match them as closely as possible.
I've ended up removing some tests here as they were testing bugs or
behavior that is no longer present. Mostly though, this is just cleanup
to let the tests continue to function as intended.
The only fallout I've found so far from this change was SROA and I have
fixed it to not be impeded by the different type of load. If you find
more places where this change causes optimizations not to fire, those
too are likely bugs where we are assuming that the type of pointers is
"significant" for optimization purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220138
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Chandler Carruth [Sat, 18 Oct 2014 06:36:18 +0000 (06:36 +0000)]
Remove a test that was ported from the old llvm-gcc frontend test suite.
This test is pretty awesome. It is claiming to test devirtualization.
However, the code in question is not in fact devirtualized by LLVM. If
you take the original C++ test case and run it through Clang at -O3 we
fail to devirtualize it completely. It also isn't a sufficiently focused
test case.
The *reason* we fail to devirtualize it isn't because of any missing
instcombine though. Instead, it is because we fail to emit an available
externally vtable and thus the vtable is just an external and completely
opaque. If I cause the vtable to be emitted, we successfully
devirtualize things.
Anyways, I'm just removing it because it is providing negative value at
this point: it isn't representative of the output of Clang really, LLVM
isn't doing the transform it claims to be testing, LLVM's failure to do
the transform isn't actually an LLVM bug at all and we shouldn't be
testing for it here, and finally the test is written in such a way that
it will trivially pass even when the point of the test is failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220137
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Nick Kledzik [Sat, 18 Oct 2014 02:28:01 +0000 (02:28 +0000)]
[llvm-objdump] don't test timestamp dump as that is time zone dependent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220123
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Nick Kledzik [Sat, 18 Oct 2014 01:50:55 +0000 (01:50 +0000)]
[llvm-objdump] enhance test case for mach-o -private-headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220120
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Nick Kledzik [Sat, 18 Oct 2014 01:21:02 +0000 (01:21 +0000)]
[llvm-objdump] Fix mach-o binding decompression error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220119
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Chandler Carruth [Sat, 18 Oct 2014 00:44:02 +0000 (00:44 +0000)]
[SROA] Change how SROA does vector-based promotion of allocas to handle
cases where the alloca type, the load types, and the store types used
all disagree.
Previously, the only way that vector-based promotion occured was if the
alloca type was a vector type. This was one of the *very* few remaining
uses of the alloca's type to guide SROA/mem2reg left in LLVM. It turns
out it was a bad idea.
The alloca type can change very easily based on the mixture of types
loaded and stored to that alloca. We shouldn't be relying on it as
a signal for very much. Instead, the source of truth should be loads and
stores. We should canonicalize the loads and stores as much as possible
and then rely on them exclusively in SROA.
When looking and loads and stores, we may find many different candidate
vector types. This change will let SROA try all of them to find a vector
type which is a viable way to promote the entire alloca to a vector
register.
With this change, it becomes possible to do better canonicalization and
optimization of loads and stores without breaking SROA in random ways,
and that should allow fixing a core source of performance loss in hot
numerical loops such as those in Eigen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220116
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Aaron Watry [Fri, 17 Oct 2014 23:33:03 +0000 (23:33 +0000)]
R600/SI: Add global atomicrmw xchg
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220110
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Aaron Watry [Fri, 17 Oct 2014 23:33:01 +0000 (23:33 +0000)]
R600/SI: Add global atomicrmw xor
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220109
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Aaron Watry [Fri, 17 Oct 2014 23:32:59 +0000 (23:32 +0000)]
R600/SI: Add global atomicrmw or
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220108
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Aaron Watry [Fri, 17 Oct 2014 23:32:57 +0000 (23:32 +0000)]
R600/SI: Add global atomicrmw min/umin
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220107
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Aaron Watry [Fri, 17 Oct 2014 23:32:56 +0000 (23:32 +0000)]
R600/SI: Add global atomicrmw max/umax
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220106
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Aaron Watry [Fri, 17 Oct 2014 23:32:54 +0000 (23:32 +0000)]
R600/SI: Add global atomicrmw and
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220105
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Aaron Watry [Fri, 17 Oct 2014 23:32:52 +0000 (23:32 +0000)]
R600/SI: Add global atomicrmw sub
v2: Add separate offset/no-offset tests
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220104
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Aaron Watry [Fri, 17 Oct 2014 23:32:50 +0000 (23:32 +0000)]
R600/SI: Fix/add tests for atomicrmw add
The previous tests claimed to test constant offsets in the function name,
but the tests weren't actually testing them.
Clone the tests, and do testing of all combinations of the following:
1) with/without constant pointer offset
2) 32/64-bit addressing modes
3) Usage and non-usage of the return value from the atomicrmw
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220103
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Aaron Watry [Fri, 17 Oct 2014 23:32:49 +0000 (23:32 +0000)]
R600: Rename atomic_load global tests to atomic_add
The function name now matches what it's actually testing.
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220102
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Evgeniy Stepanov [Fri, 17 Oct 2014 23:29:44 +0000 (23:29 +0000)]
[msan] Fix handling of byval arguments with large alignment.
MSan param-tls slots are 8-byte aligned. This change clips
alignment of memcpy into param-tls to 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220101
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Pete Cooper [Fri, 17 Oct 2014 22:59:33 +0000 (22:59 +0000)]
Check for dynamic alloca's when selecting lifetime intrinsics.
TL;DR: Indexing maps with [] creates missing entries.
The long version:
When selecting lifetime intrinsics, we index the *static* alloca map with the AllocaInst we find for that lifetime. Trouble is, we don't first check to see if this is a dynamic alloca.
On the attached example, this causes a dynamic alloca to create an entry in the static map, and returns 0 (the default) as the frame index for that lifetime. 0 was used for the frame index of the stack protector, which given that it now has a lifetime, is coloured, and merged with other stack slots.
PEI would later trigger an assert because it expects the stack protector to not be dead.
This fix ensures that we only get frame indices for static allocas, ie, those in the map. Dynamic ones are effectively dropped, which is suboptimal, but at least isn't completely broken.
rdar://problem/
18672951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220099
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Bill Schmidt [Fri, 17 Oct 2014 21:32:22 +0000 (21:32 +0000)]
[PowerPC] Disable +vsx RUN line for fma.ll due to inconsistency on other builders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220094
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Rafael Espindola [Fri, 17 Oct 2014 21:25:48 +0000 (21:25 +0000)]
Revert "TRE: make TRE a bit more aggressive"
This reverts commit r219899.
This also updates byval-tail-call.ll to make it clear what was breaking.
Adding r219899 again will cause the load/store to disappear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220093
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Bill Schmidt [Fri, 17 Oct 2014 21:19:59 +0000 (21:19 +0000)]
[PowerPC] Change assert to better form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220092
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Matt Arsenault [Fri, 17 Oct 2014 21:13:11 +0000 (21:13 +0000)]
R600/SI: Remove redundant setting of instruction bits
These are all set on the instruction base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220091
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Bill Schmidt [Fri, 17 Oct 2014 21:02:44 +0000 (21:02 +0000)]
[PowerPC] Change liveness testing in VSX FMA mutation pass
With VSX enabled, LLVM crashes when compiling
test/CodeGen/PowerPC/fma.ll. I traced this to the liveness test
that's revised in this patch. The interval test is designed to only
work for virtual registers, but in this case the AddendSrcReg is
physical. Since there is already a walk of the MIs between the
AddendMI and the FMA, I added a check for def/kill of the AddendSrcReg
in that loop. At Hal Finkel's request, I converted the liveness test
to an assert restricted to virtual registers.
I've changed the fma.ll test to have VSX and non-VSX variants so we
can test both kinds of multiply-adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220090
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Peter Collingbourne [Fri, 17 Oct 2014 18:32:36 +0000 (18:32 +0000)]
Disable ccache for go tests.
Should fix llvm-clang-lld-x86_64-debian-fast bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220071
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Matt Arsenault [Fri, 17 Oct 2014 18:02:31 +0000 (18:02 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220068
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Matt Arsenault [Fri, 17 Oct 2014 18:00:50 +0000 (18:00 +0000)]
R600/SI: Also check for FPImm literal constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220067
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Matt Arsenault [Fri, 17 Oct 2014 18:00:48 +0000 (18:00 +0000)]
R600/SI: Allow commuting with source modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220066
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Matt Arsenault [Fri, 17 Oct 2014 18:00:45 +0000 (18:00 +0000)]
R600/SI: Simplify code with hasModifiersSet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220065
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Matt Arsenault [Fri, 17 Oct 2014 18:00:43 +0000 (18:00 +0000)]
R600/SI: Fix general commuting breaking src mods
The generic code trying to use findCommutedOpIndices won't
understand that it needs to swap the modifier operands also,
so it should fail if they are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220064
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Matt Arsenault [Fri, 17 Oct 2014 18:00:41 +0000 (18:00 +0000)]
R600/SI: Cleanup code with ChangeToFPImmediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220063
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Matt Arsenault [Fri, 17 Oct 2014 18:00:39 +0000 (18:00 +0000)]
R600/SI: Allow comuting fp immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220062
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Matt Arsenault [Fri, 17 Oct 2014 18:00:37 +0000 (18:00 +0000)]
R600/SI: Use early return instead of checking condition twice
Any commutable instruction will have at least src1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220061
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Peter Collingbourne [Fri, 17 Oct 2014 17:46:46 +0000 (17:46 +0000)]
We also need to catch OSError here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220058
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Matt Arsenault [Fri, 17 Oct 2014 17:43:00 +0000 (17:43 +0000)]
R600/SI: Use complex pattern for MUBUF load patterns.
This eliminates a use of the SI_ADDR64_RSRC pseudo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220057
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Matt Arsenault [Fri, 17 Oct 2014 17:42:56 +0000 (17:42 +0000)]
R600/SI: Remove SI_BUFFER_RSRC pseudo
Just use REG_SEQUENCE directly, so there are fewer
instructions to need to deal with later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220056
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Juergen Ributzka [Fri, 17 Oct 2014 17:39:00 +0000 (17:39 +0000)]
[Stackmaps] Enable invoking the patchpoint intrinsic.
Patch by Kevin Modzelewski
Reviewers: atrick, ributzka
Reviewed By: ributzka
Subscribers: llvm-commits, reames
Differential Revision: http://reviews.llvm.org/D5634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220055
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Andrea Di Biagio [Fri, 17 Oct 2014 17:27:06 +0000 (17:27 +0000)]
[X86] Fix missed selection of non-temporal store of zero vector.
When the input to a store instruction was a zero vector, the backend
always selected a normal vector store regardless of the non-temporal
hint. This is fixed by this patch.
This fixes PR19370.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220054
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James Molloy [Fri, 17 Oct 2014 17:06:31 +0000 (17:06 +0000)]
[AArch64] Fix a silent codegen fault in BUILD_VECTOR lowering.
We should be talking about the number of source elements, not the number of destination elements, given we know at this point that the source and dest element numbers are not the same.
While we're at it, avoid writing to std::vector::end()...
Bug found with random testing and a lot of coffee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220051
91177308-0d34-0410-b5e6-
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Rafael Espindola [Fri, 17 Oct 2014 16:07:43 +0000 (16:07 +0000)]
Don't crash if find_executable return None.
This was crashing when trying to run the tests on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220048
91177308-0d34-0410-b5e6-
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Bill Schmidt [Fri, 17 Oct 2014 15:13:38 +0000 (15:13 +0000)]
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047
91177308-0d34-0410-b5e6-
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Jan Vesely [Fri, 17 Oct 2014 14:45:28 +0000 (14:45 +0000)]
Mips: Only set divrem i64 to custom on 64bit
Reviewed-by: Daniel Sanders <daniel.sanders@imgtec.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220046
91177308-0d34-0410-b5e6-
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Jan Vesely [Fri, 17 Oct 2014 14:45:27 +0000 (14:45 +0000)]
R600: Add EG to FMA test
Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220045
91177308-0d34-0410-b5e6-
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Jan Vesely [Fri, 17 Oct 2014 14:45:25 +0000 (14:45 +0000)]
SelectionDAG: Add sext_inreg optimizations
v2: use dyn_cast
fixup comments
v3: use cast
Reviewed-by: Matt Arsenault <arsenm2@gmail.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220044
91177308-0d34-0410-b5e6-
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Vasileios Kalintiris [Fri, 17 Oct 2014 14:08:28 +0000 (14:08 +0000)]
[mips] Add support for COP1's Branch-On-Cond-Likely instructions
Summary: Depends on D5782
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220042
91177308-0d34-0410-b5e6-
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Vasileios Kalintiris [Fri, 17 Oct 2014 12:38:35 +0000 (12:38 +0000)]
[mips] Add support for COP0's Branch-On-Cond-Likely instructions
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220036
91177308-0d34-0410-b5e6-
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Hal Finkel [Fri, 17 Oct 2014 11:56:00 +0000 (11:56 +0000)]
[DSE] Remove no-data-layout-only type-based overlap checking
DSE's overlap checking contained special logic, used only when no DataLayout
was available, which inferred a complete overwrite when the pointee types were
equal. This logic seems fine for regular loads/stores, but does not work for
memcpy and friends. Instead of fixing this, I'm just removing it.
Philosophically, transformations should not contain enhanced behavior used only
when data layout is lacking (data layout should be strictly additive), and
maintaining these rarely-tested code paths seems not worthwhile at this stage.
Credit to Aliaksei Zasenka for the bug report and the diagnosis. The test case
(slightly reduced from that provided by Aliaksei) replaces the original
contents of test/Transforms/DeadStoreElimination/no-targetdata.ll -- a few
other tests have been updated to have a data layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220035
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Fri, 17 Oct 2014 02:20:40 +0000 (02:20 +0000)]
Fix bashism in build.sh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220027
91177308-0d34-0410-b5e6-
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Rafael Espindola [Fri, 17 Oct 2014 01:48:58 +0000 (01:48 +0000)]
Add back commits r219835 and a fixed version of r219829.
The only difference from r219829 is using
getOrCreateSectionSymbol(*ELFSec)
instead of
GetOrCreateSymbol(ELFSec->getSectionName())
in ELFObjectWriter which causes us to use the correct section symbol even if
we have multiple sections with the same name.
Original messages:
r219829:
Correctly handle references to section symbols.
When processing assembly like
.long .text
we were creating a new undefined symbol .text. GAS on the other hand would
handle that as a reference to the .text section.
This patch implements that by creating the section symbols earlier so that
they are visible during asm parsing.
The patch also updates llvm-readobj to print the symbol number in the relocation
dump so that the test can differentiate between two sections with the same name.
r219835:
Allow forward references to section symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220021
91177308-0d34-0410-b5e6-
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Bill Schmidt [Fri, 17 Oct 2014 01:41:22 +0000 (01:41 +0000)]
[PPC] Adjust some PowerPC tests to account for presence/absence of VSX
Patch by Bill Seurer; committed on his behalf.
These test cases generate slightly different code sequences when VSX
is activated and thus fail. The update turns off VSX explicitly for
the existing checks and then adds a second set of checks for most of
them that test the VSX instruction output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220019
91177308-0d34-0410-b5e6-
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Rafael Espindola [Fri, 17 Oct 2014 01:34:23 +0000 (01:34 +0000)]
Add a test that would have found the bug in r219829.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220016
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Fri, 17 Oct 2014 01:31:47 +0000 (01:31 +0000)]
ARM: Fix a bug which was causing convergence failure in constant-island pass.
The bug is in ARMConstantIslands::createNewWater where the upper bound of the
new water split point is computed:
// This could point off the end of the block if we've already got constant
// pool entries following this block; only the last one is in the water list.
// Back past any possible branches (allow for a conditional and a maximally
// long unconditional).
if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
BaseInsertOffset = UserBBI.postOffset() - UPad - 8;
DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
}
The split point is supposed to be somewhere between the machine instruction that
loads from the constant pool entry and the end of the basic block, before branch
instructions. The code above is fine if the basic block is large enough and
there are a sufficient number of instructions following the machine instruction.
However, if the machine instruction is near the end of the basic block,
BaseInsertOffset can point to the machine instruction or another instruction
that precedes it, and this can lead to convergence failure.
This commit fixes this bug by ensuring BaseInsertOffset is larger than the
offset of the instruction following the constant-loading instruction.
rdar://problem/
18581150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220015
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Rafael Espindola [Fri, 17 Oct 2014 01:06:02 +0000 (01:06 +0000)]
Revert commit r219835 and r219829.
Revert "Correctly handle references to section symbols."
Revert "Allow forward references to section symbols."
Rui found a regression I am debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220010
91177308-0d34-0410-b5e6-
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Peter Zotov [Fri, 17 Oct 2014 01:02:40 +0000 (01:02 +0000)]
[OCaml] Add Llvm.instr_clone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220008
91177308-0d34-0410-b5e6-
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Peter Zotov [Fri, 17 Oct 2014 01:02:34 +0000 (01:02 +0000)]
[LLVM-C] Add LLVMInstructionClone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220007
91177308-0d34-0410-b5e6-
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Alexander Potapenko [Fri, 17 Oct 2014 00:50:19 +0000 (00:50 +0000)]
[llvm-symbolizer] Introduce the -dsym-hint option.
llvm-symbolizer will consult one of the .dSYM paths passed via -dsym-hint
if it fails to find the .dSYM bundle at the default location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220004
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 17 Oct 2014 00:36:20 +0000 (00:36 +0000)]
R600/SI: Simplify debug printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219999
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 16 Oct 2014 23:43:20 +0000 (23:43 +0000)]
Add our own copy of the find_executable function to cope with installations
that do not have the distutils.spawn package. Should hopefully fix the
aarch64 buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219991
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 16 Oct 2014 23:33:37 +0000 (23:33 +0000)]
R600/SI: Remove another VALU pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219988
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 16 Oct 2014 22:48:02 +0000 (22:48 +0000)]
Initial version of Go bindings.
This code is based on the existing LLVM Go bindings project hosted at:
https://github.com/go-llvm/llvm
Note that all contributors to the gollvm project have agreed to relicense
their changes under the LLVM license and submit them to the LLVM project.
Differential Revision: http://reviews.llvm.org/D5684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219976
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 16 Oct 2014 22:47:52 +0000 (22:47 +0000)]
Introduce LLVMParseCommandLineOptions C API function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219975
91177308-0d34-0410-b5e6-
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Juergen Ributzka [Thu, 16 Oct 2014 21:26:35 +0000 (21:26 +0000)]
Reduce code duplication between patchpoint and non-patchpoint lowering. NFC.
This is in preparation for another patch that makes patchpoints invokable.
Reviewers: atrick, ributzka
Reviewed By: ributzka
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219967
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 16 Oct 2014 21:11:55 +0000 (21:11 +0000)]
[SROA] Switch the common variable name for the 'AllocaSlices' class to
'AS'.
Using 'S' as this was a terrible idea. Arguably, 'AS' is not much
better, but it at least follows the idea of using initialisms and
removes active confusion about the AllocaSlices variable and a Slice
variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219963
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 16 Oct 2014 21:05:14 +0000 (21:05 +0000)]
[SROA] More range-based cleanups to SROA, these brought to you by
clang-modernize.
I did have to clean up the variable types and whitespace a bit because
the use of auto made the code much less readable here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219962
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 16 Oct 2014 20:42:08 +0000 (20:42 +0000)]
[SROA] Switch a couple of overly complex iterator accessors to just be
ArrayRef accessors.
I think this even came up in review that this was over-engineered, and
indeed it was. Time to un-build it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219958
91177308-0d34-0410-b5e6-
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Robin Morisset [Thu, 16 Oct 2014 20:34:57 +0000 (20:34 +0000)]
Erase fence insertion from SelectionDAGBuilder.cpp (NFC)
Summary:
Backends can use setInsertFencesForAtomic to signal to the middle-end that
montonic is the only memory ordering they can accept for
stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger
ordering to fences + monotonic accesses is currently living in
SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it
for several reasons:
- There is lots of redundancy to avoid: extremely similar logic already
exists in AtomicExpand.
- The current code in SelectionDAGBuilder does not use any target-hooks, it
does the same transformation for every backend that requires it
- As a result it is plain *unsound*, as it was apparently designed for ARM.
It happens to mostly work for the other targets because they are extremely
conservative, but Power for example had to switch to AtomicExpand to be
able to use lwsync safely (see r218331).
- Because it produces IR-level fences, it cannot be made sound ! This is noted
in the C++11 standard (section 29.3, page 1140):
```
Fences cannot, in general, be used to restore sequential consistency for atomic
operations with weaker ordering semantics.
```
It can also be seen by the following example (called IRIW in the litterature):
```
atomic<int> x = y = 0;
int r1, r2, r3, r4;
Thread 0:
x.store(1);
Thread 1:
y.store(1);
Thread 2:
r1 = x.load();
r2 = y.load();
Thread 3:
r3 = y.load();
r4 = x.load();
```
r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst.
But if they are lowered to monotonic accesses, no amount of fences can prevent it..
This patch does three things (I could cut it into parts, but then some of them
would not be tested/testable, please tell me if you would prefer that):
- it provides a default implementation for emitLeadingFence/emitTrailingFence in
terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder.
As we saw above, this is unsound, but the best that can be done without knowing
the targets well (and there is a comment warning about this risk).
- it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default
implementation (that exactly replicates the logic of SelectionDAGBuilder, so no
functional change)
- it finally erase this logic from SelectionDAGBuilder as it is dead-code.
Ideally, each target would define its own override for emitLeading/TrailingFence
using target-specific fences, but I do not know the Sparc/Mips/XCore memory model
well enough to do this, and they appear to be dealing fine with the ARM-inspired
default expansion for now (probably because they are overly conservative, as
Power was). If anyone wants to compile fences more agressively on these
platforms, the long comment should make it clear why he should first override
emitLeading/TrailingFence.
Test Plan: make check-all, no functional change
Reviewers: jfb, t.p.northover
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D5474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219957
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 16 Oct 2014 20:31:50 +0000 (20:31 +0000)]
R600/SI: Remove unnecessary VALU patterns
These haven't been necessary since allowing
selecting SALU instructions in non-entry blocks
was enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219956
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 16 Oct 2014 20:24:07 +0000 (20:24 +0000)]
[SROA] Start more deeply moving SROA to use ranges rather than just
iterators.
There are a ton of places where it essentially wants ranges
rather than just iterators. This is just the first step that adds the
core slice range typedefs and uses them in a couple of places. I still
have to explicitly construct them because they've not been punched
throughout the entire set of code. More range-based cleanups incoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219955
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 16 Oct 2014 20:07:40 +0000 (20:07 +0000)]
R600: Fix nonsensical implementation of computeKnownBits for BFE
This was resulting in invalid simplifications of sdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219953
91177308-0d34-0410-b5e6-
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Rafael Espindola [Thu, 16 Oct 2014 20:00:02 +0000 (20:00 +0000)]
Delete -std-compile-opts.
These days -std-compile-opts was just a silly alias for -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219951
91177308-0d34-0410-b5e6-
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Bjorn Steinbrink [Thu, 16 Oct 2014 19:43:08 +0000 (19:43 +0000)]
Allow call-slop optzn for destinations with a suitable dereferenceable attribute
Summary:
Currently, call slot optimization requires that if the destination is an
argument, the argument has the sret attribute. This is to ensure that
the memory access won't trap. In addition to sret, we can also allow the
optimization to happen for arguments that have the new dereferenceable
attribute, which gives the same guarantee.
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219950
91177308-0d34-0410-b5e6-
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Jonathan Roelofs [Thu, 16 Oct 2014 19:28:10 +0000 (19:28 +0000)]
Fix lang-ref doc bug: s/icmp lt/icmp slt/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219947
91177308-0d34-0410-b5e6-
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Nick Kledzik [Thu, 16 Oct 2014 18:58:20 +0000 (18:58 +0000)]
[llvm-objdump] Fix -private-headers for mach-o to print all LC_*_DYLIB variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219945
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 16 Oct 2014 18:48:17 +0000 (18:48 +0000)]
fold: sqrt(x * x * y) -> fabs(x) * sqrt(y)
If a square root call has an FP multiplication argument that can be reassociated,
then we can hoist a repeated factor out of the square root call and into a fabs().
In the simplest case, this:
y = sqrt(x * x);
becomes this:
y = fabs(x);
This patch relies on an earlier optimization in instcombine or reassociate to put the
multiplication tree into a canonical form, so we don't have to search over
every permutation of the multiplication tree.
Because there are no IR-level FastMathFlags for intrinsics (PR21290), we have to
use function-level attributes to do this optimization. This needs to be fixed
for both the intrinsics and in the backend.
Differential Revision: http://reviews.llvm.org/D5787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219944
91177308-0d34-0410-b5e6-
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Juergen Ributzka [Thu, 16 Oct 2014 16:41:15 +0000 (16:41 +0000)]
[AArch64] Fix miscompile of sdiv-by-power-of-2.
When the constant divisor was larger than 32bits, then the optimized code
generated for the AArch64 backend would emit the wrong code, because the shift
was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would
loose the upper 32bits.
This fixes rdar://problem/
18678801.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219934
91177308-0d34-0410-b5e6-
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Vasileios Kalintiris [Thu, 16 Oct 2014 15:41:51 +0000 (15:41 +0000)]
[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Summary:
In order to support big endian targets for the BuildPairF64 nodes we
just need to swap the low/high pair registers. Additionally, for the
ExtractElementF64 nodes we have to calculate the correct stack offset
with respect to the node's register/operand that we want to extract.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219931
91177308-0d34-0410-b5e6-
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Vasileios Kalintiris [Thu, 16 Oct 2014 15:23:52 +0000 (15:23 +0000)]
[mips] Marked the DI/EI instruction aliases as MIPS32r2
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219927
91177308-0d34-0410-b5e6-
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Vasileios Kalintiris [Thu, 16 Oct 2014 14:37:00 +0000 (14:37 +0000)]
Test commit access: remove extra new line at the end of file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219925
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 16 Oct 2014 10:10:07 +0000 (10:10 +0000)]
Add missing header guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219922
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Thu, 16 Oct 2014 06:00:46 +0000 (06:00 +0000)]
Reapply r219832 - InstCombine: Narrow switch instructions using known bits.
The code committed in r219832 asserted when it attempted to shrink a switch
statement whose type was larger than 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219902
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Thu, 16 Oct 2014 03:27:30 +0000 (03:27 +0000)]
TRE: make TRE a bit more aggressive
Make tail recursion elimination a bit more aggressive. This allows us to get
tail recursion on functions that are just branches to a different function. The
fact that the function takes a byval argument does not restrict it from being
optimised into just a tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219899
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Thu, 16 Oct 2014 01:17:02 +0000 (01:17 +0000)]
Revert r219832.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219884
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 16 Oct 2014 00:40:05 +0000 (00:40 +0000)]
[LVI] Add some additional comments about caching and context instructions
Philip Reames and I had a long conversation about this, mostly because it is
not obvious why the current logic is correct. Hopefully, these comments will
prevent such confusion in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219882
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Thu, 16 Oct 2014 00:14:57 +0000 (00:14 +0000)]
llvm/Support/Options.h: Use \tparam. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219881
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Matt Arsenault [Thu, 16 Oct 2014 00:08:09 +0000 (00:08 +0000)]
R600: Remove dead function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219879
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Sanjoy Das [Wed, 15 Oct 2014 23:46:04 +0000 (23:46 +0000)]
Revert "r219834 - Teach ScalarEvolution to sharpen range information"
This change breaks the asan buildbots:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/13468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219878
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Hal Finkel [Wed, 15 Oct 2014 23:44:41 +0000 (23:44 +0000)]
Preserve non-byval pointer alignment attributes using @llvm.assume when inlining
For pointer-typed function arguments, enhanced alignment can be asserted using
the 'align' attribute. When inlining, if this enhanced alignment information is
not otherwise available, preserve it using @llvm.assume-based alignment
assumptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219876
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Hal Finkel [Wed, 15 Oct 2014 23:44:22 +0000 (23:44 +0000)]
Add CreateAlignmentAssumption to IRBuilder
Clang CodeGen had a utility function for creating pointer alignment assumptions
using the @llvm.assume intrinsic. This functionality will also be needed by the
inliner (to preserve function-argument alignment attributes when inlining), so
this moves the utility function into IRBuilder where it can be used both by
Clang CodeGen and also other LLVM-level code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219875
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