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Stephen Boyd [Tue, 16 Feb 2021 22:09:24 +0000 (14:09 -0800)]
Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into clk-next
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- Video clk fixups on Qualcomm SM8250
- GPU clks for Qualcomm SDM660/SDM630
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
* clk-socfpga:
clk: socfpga: agilex: add clock driver for eASIC N5X platform
dt-bindings: documentation: add clock bindings information for eASIC N5X
* clk-mstar:
clk: mstar: msc313-mpll: Fix format specifier
clk: mstar: Allow MStar clk drivers to be compile tested
clk: mstar: MStar/SigmaStar MPLL driver
clk: fixed: add devm helper for clk_hw_register_fixed_factor()
dt-bindings: clk: mstar msc313 mpll binding description
dt-bindings: clk: mstar msc313 mpll binding header
* clk-qcom: (42 commits)
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: gcc-sm8350: add gdsc
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical
...
* clk-warnings: (27 commits)
clk: zynq: clkc: Remove various instances of an unused variable 'clk'
clk: versatile: clk-icst: Fix worthy struct documentation block
clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter
clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param
clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one
clk: st: clkgen-pll: Demote unpopulated kernel-doc header
clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header
clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
clk: socfpga: clk-pll: Remove unused variable 'rc'
clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used
clk: bcm: clk-iproc-pll: Demote kernel-doc abuse
clk: zynqmp: divider: Add missing description for 'max_div'
clk: spear: Move prototype to accessible header
clk: qcom: clk-rpm: Remove a bunch of superfluous code
clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags'
clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}'
clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx'
clk: clk-fixed-mmio: Demote obvious kernel-doc abuse
clk: qcom: gcc-ipq4019: Remove unused variable 'ret'
...
Stephen Boyd [Tue, 16 Feb 2021 22:09:12 +0000 (14:09 -0800)]
Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot
* clk-vc5:
clk: vc5: Add support for optional load capacitance
dt-bindings: clk: versaclock5: Add optional load capacitance property
* clk-silabs:
clk: si570: Skip NVM to RAM recall operation if an optional property is set
dt-bindings: clock: si570: Add 'silabs,skip-recall' property
* clk-aspeed:
clk: aspeed: Fix APLL calculate formula from ast2600-A2
* clk-qoriq:
clk: qoriq: use macros to generate pll_mask
* clk-rohm:
clk: BD718x7: Do not depend on parent driver data
Stephen Boyd [Tue, 16 Feb 2021 22:09:08 +0000 (14:09 -0800)]
Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next
* clk-mediatek:
clk: mediatek: mux: Update parent at enable time
clk: mediatek: mux: Drop unused clock ops
clk: mediatek: Select all the MT8183 clocks by default
* clk-imx:
dt-bindings: clock: imx: Switch to my personal address
MAINTAINERS: Add section for NXP i.MX clock drivers
clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header
clk: imx8mn: add clkout1/2 support
clk: imx8mm: add clkout1/2 support
clk: imx8mq: add PLL monitor output
clk: imx: clk-imx31: Remove unused static const table 'uart_clks'
clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting
clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
* clk-amlogic:
clk: meson: axg: Remove MIPI enable clock gate
clk: meson-axg: remove CLKID_MIPI_ENABLE
dt-bindings: clock: meson8b: remove non-existing clock macros
clk: meson: meson8b: remove compatibility code for old .dtbs
clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
clk: meson: clk-pll: make "ret" a signed integer
clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
* clk-at91:
clk: at91: Fix the declaration of the clocks
Stephen Boyd [Tue, 16 Feb 2021 22:08:51 +0000 (14:08 -0800)]
Merge branch 'clk-unused' into clk-next
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
* clk-unused:
clk: remove u300 driver
clk: remove sirf prima2/atlas drivers
clk: remove zte zx driver
clk: remove tango4 driver
clk: Drop unused efm32gg driver
Stephen Boyd [Tue, 16 Feb 2021 22:06:43 +0000 (14:06 -0800)]
Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and 'clk-xilinx' into clk-next
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
* clk-doc:
linux/clk.h: use correct kernel-doc notation for 2 functions
* clk-renesas: (21 commits)
clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
clk: renesas: r8a779a0: Add RAVB clocks
clk: renesas: r8a779a0: Add I2C clocks
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H
clk: renesas: r8a779a0: Add SYS-DMAC clocks
clk: renesas: r8a779a0: Add SDHI support
clk: renesas: rcar-gen3: Factor out CPG library
clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock
clk: renesas: r8a779a0: Add MSIOF clocks
clk: renesas: r8a779a0: Add PFC/GPIO clocks
clk: renesas: r8a779a0: Fix parent of CBFUSA clock
clk: renesas: r8a779a0: Remove non-existent S2 clock
clk: renesas: r8a779a0: Add HSCIF support
clk: renesas: r8a779a0: Add RWDT clocks
clk: renesas: r8a779a0: Add VSPX clock support
clk: renesas: r8a779a0: Add VSPD clock support
clk: renesas: r8a779a0: Add FCPVD clock support
clk: renesas: r8a77995: Add TMU clocks
clk: renesas: r8a77990: Add TMU clocks
clk: renesas: r8a77965: Add TMU clocks
...
* clk-allwinner:
clk: sunxi-ng: Add support for the Allwinner H616 CCU
clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
clk: sunxi-ng: h6: Fix clock divider range on some clocks
clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header
clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse
clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers
clk: sunxi-ng: h6: Fix CEC clock
clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
* clk-rockchip:
clk: rockchip: fix DPHY gate locations on rk3368
clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: Demote non-conformant kernel-doc header in half-divider
clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
clk: rockchip: Remove unused/undocumented struct members from clk-cpu
clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
* clk-xilinx:
clk: xilinx: move xlnx_vcu clock driver from soc
soc: xilinx: vcu: fix alignment to open parenthesis
soc: xilinx: vcu: fix repeated word the in comment
soc: xilinx: vcu: use bitfields for register definition
soc: xilinx: vcu: remove calculation of PLL configuration
soc: xilinx: vcu: make the PLL configurable
soc: xilinx: vcu: make pll post divider explicit
soc: xilinx: vcu: implement clock provider for output clocks
soc: xilinx: vcu: register PLL as fixed rate clock
soc: xilinx: vcu: implement PLL disable
soc: xilinx: vcu: add helpers for configuring PLL
soc: xilinx: vcu: add helper to wait for PLL locked
soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
clk: divider: fix initialization with parent_hw
ARM: dts: vcu: define indexes for output clocks
clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
clk: axi-clkgen: replace ARCH dependencies with driver deps
Daniel Palmer [Mon, 15 Feb 2021 11:57:10 +0000 (20:57 +0900)]
clk: mstar: msc313-mpll: Fix format specifier
The output dividers are unsigned int so the format specifier
should have been %u not %d.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210215115710.3762276-2-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Daniel Palmer [Mon, 15 Feb 2021 11:57:09 +0000 (20:57 +0900)]
clk: mstar: Allow MStar clk drivers to be compile tested
Allow COMPILE_TEST to also build the MStar clk drivers
instead of only building them when ARCH_MSTARV7 is selected.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210215115710.3762276-1-daniel@0x0f.com
[sboyd@kernel.org: Drop regmap select too]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Wasim Khan [Mon, 25 Jan 2021 14:25:13 +0000 (15:25 +0100)]
clk: qoriq: use macros to generate pll_mask
Use macros to generate pll_mask to make code
more readable.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Link: https://lore.kernel.org/r/20210125142513.3919014-1-wasim.khan@oss.nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Wed, 10 Feb 2021 18:26:19 +0000 (23:56 +0530)]
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612981579-17391-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Wed, 10 Feb 2021 18:26:18 +0000 (23:56 +0530)]
dt-bindings: clock: Add SC7280 GCC clock binding
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612981579-17391-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Wed, 10 Feb 2021 17:13:50 +0000 (22:43 +0530)]
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
Add support for RPMH clocks on SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612977230-11566-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Wed, 10 Feb 2021 17:13:49 +0000 (22:43 +0530)]
dt-bindings: clock: Add RPMHCC bindings for SC7280
Add bindings and update documentation for clock rpmh driver on SC7280.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612977230-11566-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Wed, 10 Feb 2021 16:16:49 +0000 (21:46 +0530)]
clk: qcom: gcc-sm8350: add gdsc
Add the GDSC found in GCC for SM8350 SoC
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:17 +0000 (19:38 +0100)]
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM630 and SDM660 SoCs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-10-angelogioacchino.delregno@somainline.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:16 +0000 (19:38 +0100)]
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
The GPUCC manages the clocks for the Adreno GPU found on the
SDM630, SDM636, SDM660 SoCs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:14 +0000 (19:38 +0100)]
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong
parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were
generalized in order to be able to reuse the same ops for more than just
one clock for one SoC: follow the change here in the MSM8996 MMCC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:13 +0000 (19:38 +0100)]
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
The function clk_gfx3d_determine_rate is selecting different PLLs
to manage the GFX3D clock source in a special way: this one needs
to be ping-pong'ed on different PLLs to ensure stability during
frequency switching (set a PLL rate, let it stabilize, switch the
RCG to the new PLL) and fast frequency transitions.
This technique is currently being used in the MSM8996 SoC and the
function was assuming that the parents were always at a specific
index in the parents list, which is TRUE, if we use this only on
the MSM8996 MMCC.
Unfortunately, MSM8996 is not the only SoC that needs to ping-pong
the graphics RCG, so choices are:
1. Make new special ops just to hardcode *again* other indexes,
creating code duplication for (imo) no reason; or
2. Generalize this function, so that it becomes usable for a range
of SoCs with slightly different ping-pong configuration.
In this commit, the second road was taken: define a new "special"
struct clk_rcg2_gfx3d, containing the ordered list of parents to
ping-pong the graphics clock on, and the "regular" rcg2 clock
structure in order to generalize the clk_gfx3d_determine_rate
function and make it working for other SoCs.
As for the function itself it is left with the assumption that we
need to ping-pong over three parents. The reasons for this are:
1. The initial model was MSM8996, which has 3 parents for the
graphics clock pingpong;
2. The other example that was taken into consideration is the
SDM630/636/660 SoC gpu clock controller, which is ping-ponging
over two dynamic clocked and one fixed clock PLL.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-6-angelogioacchino.delregno@somainline.org
[sboyd@kernel.org: Grow some local variables, drop do_div() usage in
favor of plain division, we're not dealing with a u64 here]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:12 +0000 (19:38 +0100)]
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
Document the multimedia clock controller found on SDM630/660.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-5-angelogioacchino.delregno@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Martin Botka [Wed, 13 Jan 2021 18:38:11 +0000 (19:38 +0100)]
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
Add a driver for the multimedia clock controller found on SDM660
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org
[sboyd@kernel.org: Silence NULL pointer sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:10 +0000 (19:38 +0100)]
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
This clock is critical for any access to the GPU: gating it will
crash the system when the GPU has been initialized (so, you cannot
gate it unless you deinit the Adreno completely).
So, to achieve a working state with GPU on, set the CLK_IS_CRITICAL
flag to this clock.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-3-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:09 +0000 (19:38 +0100)]
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
Similarly to MSM8998, any access to the MMSS depends on this clock.
Gating it will crash the system when RPMCC inits mmssnoc_axi_rpm_clk.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-2-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 14 Jan 2021 22:10:59 +0000 (23:10 +0100)]
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
The GPU PLL0 is not a fixed PLL and the rate can be set on it:
this is necessary especially on boards which bootloader is setting
a very low rate on this PLL before booting Linux, which would be
unsuitable for postdividing to reach the maximum allowed Adreno GPU
frequency of 710MHz (or, actually, even 670MHz..) on this SoC.
To allow setting rates on the GPU PLL0, also define VCO boundaries
and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider.
With this change, the Adreno GPU is now able to scale through all
the available frequencies.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-12-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 14 Jan 2021 22:10:58 +0000 (23:10 +0100)]
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated
on downstream kernels (and as verified upstream, because otherwise
random lockups happen).
Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream,
and also as verified here, to avoid GPU related lockups it is
necessary to force retain mem, but *not* peripheral when enabling
this GDSC (and, of course, the inverse on disablement).
With this change, the GPU finally works flawlessly on my four
different MSM8998 devices from two different manufacturers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-11-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Wed, 13 Jan 2021 18:38:15 +0000 (19:38 +0100)]
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
In some rare occasions, we want to only set the RETAIN_MEM bit, but
not the RETAIN_PERIPH one: this is seen on at least SDM630/636/660's
GPU-GX GDSC, where unsetting and setting back the RETAIN_PERIPH bit
will generate chaos and panics during GPU suspend time (mainly, the
chaos is unaligned access).
For this reason, introduce a new NO_RET_PERIPH flag to the GDSC
driver to address this corner case.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-8-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Daniel Palmer [Thu, 11 Feb 2021 05:22:03 +0000 (14:22 +0900)]
clk: mstar: MStar/SigmaStar MPLL driver
This adds a basic driver for the MPLL block found in MStar/SigmaStar
ARMv7 SoCs.
Currently this driver is only good for calculating the rates of it's
outputs and the actual configuration must be done before the kernel
boots. Usually this is done even before u-boot starts.
This driver targets the MPLL block found in the MSC313/MSC313E but
there is no documentation this chip so the register descriptions for
the another MStar chip the MST786 were used as they seem to match.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Daniel Palmer [Thu, 11 Feb 2021 05:22:02 +0000 (14:22 +0900)]
clk: fixed: add devm helper for clk_hw_register_fixed_factor()
Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally
register fixed factor clocks for things like dividers don't need to manually unregister
them on remove or if probe fails.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Daniel Palmer [Thu, 11 Feb 2021 05:22:01 +0000 (14:22 +0900)]
dt-bindings: clk: mstar msc313 mpll binding description
Add a binding description for the MStar/SigmaStar MPLL clock block.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-3-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Daniel Palmer [Thu, 11 Feb 2021 05:22:00 +0000 (14:22 +0900)]
dt-bindings: clk: mstar msc313 mpll binding header
Simple header to document the relationship between the MPLL outputs
and which divider they come from.
Output 0 is missing because it should not be consumed.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210211052206.2955988-2-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Fri, 12 Feb 2021 14:30:59 +0000 (08:30 -0600)]
clk: socfpga: agilex: add clock driver for eASIC N5X platform
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Fri, 12 Feb 2021 14:30:58 +0000 (08:30 -0600)]
dt-bindings: documentation: add clock bindings information for eASIC N5X
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the eASIC
N5X platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210212143059.478554-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Matti Vaittinen [Tue, 5 Jan 2021 12:47:54 +0000 (14:47 +0200)]
clk: BD718x7: Do not depend on parent driver data
The bd718x7 only needs a regmap from parent device. This can be
obtained by call to dev_get_regmap. Do not require parent to
populate the driver data for this.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Link: https://lore.kernel.org/r/20210105123028.GA3409663@localhost.localdomain
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ryan Chen [Tue, 19 Jan 2021 06:17:15 +0000 (14:17 +0800)]
clk: aspeed: Fix APLL calculate formula from ast2600-A2
Starting from A2, the A-PLL calculation has changed. Use the
existing formula for A0/A1 and the new formula for A2 onwards.
Fixes:
d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Saeed Nowshadi [Fri, 5 Feb 2021 03:35:04 +0000 (19:35 -0800)]
clk: si570: Skip NVM to RAM recall operation if an optional property is set
Recalling NVM data into RAM during probe() initiates a re-calibration of
the clock. If the clock is already in-use, the recall operation can cause
a glitch on the frequency out. At power on, the factory data are loaded
from NVM into RAM by default. If the clock frequency has been changed
since power on, the recall operation can be used to re-initialize the clock
to factory setting.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Link: https://lore.kernel.org/r/1612496104-3437-3-git-send-email-saeed.nowshadi@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Saeed Nowshadi [Fri, 5 Feb 2021 03:35:03 +0000 (19:35 -0800)]
dt-bindings: clock: si570: Add 'silabs,skip-recall' property
Add an optional property so the driver can skip calling the NVM->RAM
recall operation during probe().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Link: https://lore.kernel.org/r/1612496104-3437-2-git-send-email-saeed.nowshadi@xilinx.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Adam Ford [Sun, 7 Feb 2021 18:51:39 +0000 (12:51 -0600)]
clk: vc5: Add support for optional load capacitance
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Parse the device tree and set the
corresponding registers accordingly.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20210207185140.3653350-2-aford173@gmail.com
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Adam Ford [Sun, 7 Feb 2021 18:51:38 +0000 (12:51 -0600)]
dt-bindings: clk: versaclock5: Add optional load capacitance property
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20210207185140.3653350-1-aford173@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:40 +0000 (09:30 +0000)]
clk: zynq: clkc: Remove various instances of an unused variable 'clk'
Fixes the following W=1 kernel build warning(s):
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’:
drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’:
drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’:
drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-21-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:39 +0000 (09:30 +0000)]
clk: versatile: clk-icst: Fix worthy struct documentation block
Also demote non-worthy header to standard comment block.
Fixes the following W=1 kernel build warning(s):
drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'map' not described in 'clk_icst'
drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'vcoreg_off' not described in 'clk_icst'
drivers/clk/versatile/clk-icst.c:53: warning: Function parameter or member 'lockreg_off' not described in 'clk_icst'
drivers/clk/versatile/clk-icst.c:435: warning: cannot understand function prototype: 'const struct icst_params icst525_apcp_cm_params = '
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-20-lee.jones@linaro.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:36 +0000 (09:30 +0000)]
clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/gate.c:67: warning: Function parameter or member 'hw' not described in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
drivers/clk/ti/gate.c:67: warning: Excess function parameter 'clk' description in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-17-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:35 +0000 (09:30 +0000)]
clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/dpll.c:163: warning: Function parameter or member 'user' not described in '_register_dpll'
drivers/clk/ti/dpll.c:163: warning: Excess function parameter 'hw' description in '_register_dpll'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-16-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:33 +0000 (09:30 +0000)]
clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/clockdomain.c:107: warning: Function parameter or member 'hw' not described in 'omap2_init_clk_clkdm'
drivers/clk/ti/clockdomain.c:107: warning: Excess function parameter 'clk' description in 'omap2_init_clk_clkdm'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-14-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:32 +0000 (09:30 +0000)]
clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one
Fixes the following W=1 kernel build warning(s):
drivers/clk/st/clkgen-fsyn.c:186: warning: Function parameter or member 'data' not described in 'st_clk_quadfs_pll'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'regs_base' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'lock' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'data' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'chan' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'md' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'pe' not described in 'st_clk_quadfs_fsynth'
drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'sdiv' not described in 'st_clk_quadfs_fsynth'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Stephen Gallimore <stephen.gallimore@st.com>
Cc: Pankaj Dev <pankaj.dev@st.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-13-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:31 +0000 (09:30 +0000)]
clk: st: clkgen-pll: Demote unpopulated kernel-doc header
And remove an incorrect entry.
Fixes the following W=1 kernel build warning(s):
drivers/clk/st/clkgen-pll.c:142: warning: cannot understand function prototype: 'struct clkgen_pll '
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Stephen Gallimore <stephen.gallimore@st.com>
Cc: Pankaj Dev <pankaj.dev@st.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-12-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:29 +0000 (09:30 +0000)]
clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header
Not much effort has been put into this one.
Demote it for the time being at least.
Fixes the following W=1 kernel build warning(s):
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_reg' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_mask' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'cluster_offset' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'force_mask' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_offset' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'divider_ratio' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_offset' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_offset' not described in 'cpu_dfs_regs'
drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member 'ratio_state_cluster_offset' not described in 'cpu_dfs_regs'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Julia Lawall <Julia.Lawall@inria.fr>
Cc: Omri Itach <omrii@marvell.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-10-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:28 +0000 (09:30 +0000)]
clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
Fixes the following W=1 kernel build warning(s):
drivers/clk/socfpga/clk-pll-a10.c: In function ‘__socfpga_pll_init’:
drivers/clk/socfpga/clk-pll-a10.c:76:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable]
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-9-lee.jones@linaro.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:27 +0000 (09:30 +0000)]
clk: socfpga: clk-pll: Remove unused variable 'rc'
Fixes the following W=1 kernel build warning(s):
drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’:
drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable]
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-8-lee.jones@linaro.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:26 +0000 (09:30 +0000)]
clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used
Fixes the following W=1 kernel build warning(s):
drivers/clk/sifive/fu540-prci.h:16:35: warning: ‘prci_clk_fu540’ defined but not used [-Wunused-const-variable=]
drivers/clk/sifive/fu540-prci.h:16:35: warning: ‘prci_clk_fu540’ defined but not used [-Wunused-const-variable=]
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Pragnesh Patel <Pragnesh.patel@sifive.com>
Cc: Zong Li <zong.li@sifive.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-7-lee.jones@linaro.org
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Wed, 20 Jan 2021 09:30:25 +0000 (09:30 +0000)]
clk: bcm: clk-iproc-pll: Demote kernel-doc abuse
Fixes the following W=1 kernel build warning(s):
drivers/clk/bcm/clk-iproc-pll.c:712: warning: Function parameter or member 'pll' not described in 'iproc_pll_sw_cfg'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-6-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:40 +0000 (12:45 +0000)]
clk: zynqmp: divider: Add missing description for 'max_div'
Fixes the following W=1 kernel build warning(s):
drivers/clk/zynqmp/divider.c:46: warning: Function parameter or member 'max_div' not described in 'zynqmp_clk_divider'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Rajan Vaja <rajan.vaja@xilinx.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-22-lee.jones@linaro.org
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:38 +0000 (12:45 +0000)]
clk: spear: Move prototype to accessible header
Fixes the following W=1 kernel build warning(s):
drivers/clk/spear/spear1310_clock.c:385:13: warning: no previous prototype for ‘spear1310_clk_init’ [-Wmissing-prototypes]
drivers/clk/spear/spear1340_clock.c:442:13: warning: no previous prototype for ‘spear1340_clk_init’ [-Wmissing-prototypes]
Cc: Viresh Kumar <vireshk@kernel.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-20-lee.jones@linaro.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:37 +0000 (12:45 +0000)]
clk: qcom: clk-rpm: Remove a bunch of superfluous code
Fixes the following W=1 kernel build warning(s):
drivers/clk/qcom/clk-rpm.c:453:29: warning: ‘clk_rpm_branch_ops’ defined but not used [-Wunused-const-variable=]
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-19-lee.jones@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:36 +0000 (12:45 +0000)]
clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags'
Fixes the following W=1 kernel build warning(s):
drivers/clk/clk-xgene.c:229: warning: Function parameter or member 'mask' not described in 'xgene_clk_pmd'
drivers/clk/clk-xgene.c:229: warning: Function parameter or member 'flags' not described in 'xgene_clk_pmd'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Loc Ho <lho@apm.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-18-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:35 +0000 (12:45 +0000)]
clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}'
Fixes the following W=1 kernel build warning(s):
drivers/clk/qcom/mmcc-msm8974.c:85:27: warning: ‘mmcc_xo_mmpll0_1_2_gpll0’ defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/mmcc-msm8974.c:77:32: warning: ‘mmcc_xo_mmpll0_1_2_gpll0_map’ defined but not used [-Wunused-const-variable=]
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-17-lee.jones@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:34 +0000 (12:45 +0000)]
clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx'
Fixes the following W=1 kernel build warning(s):
drivers/clk/clk-npcm7xx.c:438:43: warning: ‘npcm7xx_gates’ defined but not used [-Wunused-const-variable=]
drivers/clk/clk-npcm7xx.c:365:48: warning: ‘npcm7xx_divs_fx’ defined but not used [-Wunused-const-variable=]
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Tomer Maimon <tmaimon77@gmail.com>
Cc: Tali Perry <tali.perry1@gmail.com>
Cc: Patrick Venture <venture@google.com>
Cc: Nancy Yuen <yuenn@google.com>
Cc: Benjamin Fair <benjaminfair@google.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Nuvoton Technologies <tali.perry@nuvoton.com>
Cc: openbmc@lists.ozlabs.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-16-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:33 +0000 (12:45 +0000)]
clk: clk-fixed-mmio: Demote obvious kernel-doc abuse
Fixes the following W=1 kernel build warning(s):
drivers/clk/clk-fixed-mmio.c:62: warning: Function parameter or member 'pdev' not described in 'of_fixed_mmio_clk_probe'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jan Kotas <jank@cadence.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-15-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:32 +0000 (12:45 +0000)]
clk: qcom: gcc-ipq4019: Remove unused variable 'ret'
Fixes the following W=1 kernel build warning(s):
drivers/clk/qcom/gcc-ipq4019.c: In function ‘clk_cpu_div_set_rate’:
drivers/clk/qcom/gcc-ipq4019.c:1279:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable]
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-14-lee.jones@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:29 +0000 (12:45 +0000)]
clk: ti: dpll44xx: Fix some potential doc-rot
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/dpll44xx.c:114: warning: Function parameter or member 'hw' not described in 'omap4_dpll_regm4xen_recalc'
drivers/clk/ti/dpll44xx.c:114: warning: Function parameter or member 'parent_rate' not described in 'omap4_dpll_regm4xen_recalc'
drivers/clk/ti/dpll44xx.c:114: warning: Excess function parameter 'clk' description in 'omap4_dpll_regm4xen_recalc'
drivers/clk/ti/dpll44xx.c:150: warning: Function parameter or member 'hw' not described in 'omap4_dpll_regm4xen_round_rate'
drivers/clk/ti/dpll44xx.c:150: warning: Function parameter or member 'parent_rate' not described in 'omap4_dpll_regm4xen_round_rate'
drivers/clk/ti/dpll44xx.c:150: warning: Excess function parameter 'clk' description in 'omap4_dpll_regm4xen_round_rate'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-11-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:28 +0000 (12:45 +0000)]
clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param
Fixes the following W=1 kernel build warning(s):
drivers/clk/tegra/cvb.c:106: warning: Function parameter or member 'align' not described in 'tegra_cvb_add_opp_table'
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-10-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:26 +0000 (12:45 +0000)]
clk: tegra: clk-tegra30: Remove unused variable 'reg'
Fixes the following W=1 kernel build warning(s):
drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_enable_cpu_clock’:
drivers/clk/tegra/clk-tegra30.c:1107:15: warning: variable ‘reg’ set but not used [-Wunused-but-set-variable]
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-8-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:23 +0000 (12:45 +0000)]
clk: qcom: clk-regmap: Provide missing description for 'devm_clk_register_regmap()'s dev param
Fixes the following W=1 kernel build warning(s):
drivers/clk/qcom/clk-regmap.c:97: warning: Function parameter or member 'dev' not described in 'devm_clk_register_regmap'
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-5-lee.jones@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:22 +0000 (12:45 +0000)]
clk: ti: dpll3xxx: Fix some kernel-doc headers and promote other worthy ones
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/dpll3xxx.c:414: warning: Function parameter or member 'hw' not described in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:414: warning: Function parameter or member 'parent_rate' not described in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:414: warning: Excess function parameter 'clk' description in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:437: warning: Function parameter or member 'hw' not described in 'omap3_noncore_dpll_enable'
drivers/clk/ti/dpll3xxx.c:437: warning: Excess function parameter 'clk' description in 'omap3_noncore_dpll_enable'
drivers/clk/ti/dpll3xxx.c:479: warning: Function parameter or member 'hw' not described in 'omap3_noncore_dpll_disable'
drivers/clk/ti/dpll3xxx.c:479: warning: Excess function parameter 'clk' description in 'omap3_noncore_dpll_disable'
drivers/clk/ti/dpll3xxx.c:755: warning: Function parameter or member 'hw' not described in 'omap3_clkoutx2_recalc'
drivers/clk/ti/dpll3xxx.c:755: warning: Function parameter or member 'parent_rate' not described in 'omap3_clkoutx2_recalc'
drivers/clk/ti/dpll3xxx.c:755: warning: Excess function parameter 'clk' description in 'omap3_clkoutx2_recalc'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-4-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:21 +0000 (12:45 +0000)]
clk: ti: clkt_dpll: Fix some kernel-doc misdemeanours
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'hw' not described in 'omap2_dpll_round_rate'
drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'parent_rate' not described in 'omap2_dpll_round_rate'
drivers/clk/ti/clkt_dpll.c:284: warning: Excess function parameter 'clk' description in 'omap2_dpll_round_rate'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-3-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lee Jones [Tue, 26 Jan 2021 12:45:20 +0000 (12:45 +0000)]
clk: zynq: pll: Fix kernel-doc formatting in 'clk_register_zynq_pll's header
Fixes the following W=1 kernel build warning(s):
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'name' not described in 'clk_register_zynq_pll'
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'parent' not described in 'clk_register_zynq_pll'
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'pll_ctrl' not described in 'clk_register_zynq_pll'
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'pll_status' not described in 'clk_register_zynq_pll'
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'lock_index' not described in 'clk_register_zynq_pll'
drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'lock' not described in 'clk_register_zynq_pll'
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-2-lee.jones@linaro.org
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tudor Ambarus [Wed, 3 Feb 2021 15:43:32 +0000 (17:43 +0200)]
clk: at91: Fix the declaration of the clocks
These are all "early clocks" that require initialization just at
of_clk_init() time. Use CLK_OF_DECLARE() to declare them.
This also fixes a problem that was spotted when fw_devlink was
set to 'on' by default: the boards failed to boot. The reason is
that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes
the consumers of the clock to be postponed by fw_devlink until
the second initialization routine of the clock has been completed.
One of the consumers of the clock is the timer, which is used as a
clocksource, and needs the clock initialized early. Postponing the
timers caused the fail at boot.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com
Acked-by: Saravana Kannan <saravanak@google.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Wed, 10 Feb 2021 00:03:39 +0000 (16:03 -0800)]
Merge tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- pll driver fixup
- meson8b clock controller dt support clean up
- remove mipi clk from the axg clock controller
* tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson:
clk: meson: axg: Remove MIPI enable clock gate
clk: meson-axg: remove CLKID_MIPI_ENABLE
dt-bindings: clock: meson8b: remove non-existing clock macros
clk: meson: meson8b: remove compatibility code for old .dtbs
clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
clk: meson: clk-pll: make "ret" a signed integer
clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
Remi Pommarel [Mon, 9 Mar 2020 21:01:56 +0000 (22:01 +0100)]
clk: meson: axg: Remove MIPI enable clock gate
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Remi Pommarel [Mon, 9 Mar 2020 21:01:57 +0000 (22:01 +0100)]
clk: meson-axg: remove CLKID_MIPI_ENABLE
CLKID_MIPI_ENABLE is not handled by the AXG clock driver anymore but by
the MIPI/PCIe PHY driver.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Fabio Estevam [Sat, 30 Jan 2021 14:45:58 +0000 (11:45 -0300)]
dt-bindings: clock: imx: Switch to my personal address
My nxp account will expire soon, so switch to my personal e-mail
address.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210130144558.133534-1-festevam@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Laurent Pinchart [Mon, 25 Jan 2021 17:08:19 +0000 (19:08 +0200)]
clk: mediatek: mux: Update parent at enable time
The mux clocks don't always correctly take the new parent into account
when the parent is updated while the clock is disabled. Set the update
bit when enabling the clock to force an update of the mux.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com
Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Laurent Pinchart [Mon, 25 Jan 2021 17:08:18 +0000 (19:08 +0200)]
clk: mediatek: mux: Drop unused clock ops
Three out of the four defined clock ops are unused. Drop them.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210125170819.26130-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Enric Balletbo i Serra [Wed, 3 Feb 2021 10:54:23 +0000 (11:54 +0100)]
clk: mediatek: Select all the MT8183 clocks by default
If MT8183 SoC support is enabled, almost all machines will use topckgen,
apmixedsys, infracfg, mcucfg and subsystem clocks, so it feels wrong to
require each one to select that symbols manually.
Instead, enable it whenever COMMON_CLK_MT8183_* is disabled as
a simplification. This would add few KB in the kernel image size but
will make the life a bit easier to the users, anyway you'll need to probably
enable all of them if you want to have proper support for that SoC.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210203105423.682960-1-enric.balletbo@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Arnd Bergmann [Wed, 20 Jan 2021 13:10:26 +0000 (14:10 +0100)]
clk: remove u300 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-5-arnd@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Arnd Bergmann [Wed, 20 Jan 2021 13:10:25 +0000 (14:10 +0100)]
clk: remove sirf prima2/atlas drivers
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.
Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Arnd Bergmann [Wed, 20 Jan 2021 13:10:24 +0000 (14:10 +0100)]
clk: remove zte zx driver
The zte zx platform is getting removed, so this driver is no
longer needed.
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Arnd Bergmann [Wed, 20 Jan 2021 13:10:23 +0000 (14:10 +0100)]
clk: remove tango4 driver
The tango platform is getting removed, so the driver is no
longer needed.
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-2-arnd@kernel.org
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:59 +0000 (08:16 +0100)]
clk: xilinx: move xlnx_vcu clock driver from soc
The xlnx_vcu driver is actually a clock controller driver which provides
clocks that can be used by a driver for the encoder/decoder units. There
is no reason to keep this driver in soc. Move the driver to clk.
NOTE: The register mapping actually contains registers for AXI
performance monitoring, but these are not used by the driver.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:58 +0000 (08:16 +0100)]
soc: xilinx: vcu: fix alignment to open parenthesis
Fixes the following checkpatch check:
CHECK: Alignment should match open parenthesis
#610: FILE: drivers/soc/xilinx/xlnx_vcu.c:610:
+ xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-15-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:57 +0000 (08:16 +0100)]
soc: xilinx: vcu: fix repeated word the in comment
Fixes the following checkpatch warning:
WARNING: Possible repeated word: 'the'
#703: FILE: drivers/soc/xilinx/xlnx_vcu.c:703:
+ /* Add the the Gasket isolation and put the VCU in reset. */
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-14-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:56 +0000 (08:16 +0100)]
soc: xilinx: vcu: use bitfields for register definition
This makes the register accesses more readable and is closer to what is
usually used in the kernel.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-13-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:55 +0000 (08:16 +0100)]
soc: xilinx: vcu: remove calculation of PLL configuration
As the consumers are now responsible for setting the clock rate via
clock framework, the clock rate is now calculated using round_rate and
the driver does not need to calculate the clock rate beforehand.
Remove the code that calculates the PLL configuration.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-12-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:54 +0000 (08:16 +0100)]
soc: xilinx: vcu: make the PLL configurable
Do not configure the PLL when probing the driver, but register the clock
in the clock framework and do the configuration based on the respective
callbacks.
This is necessary to allow the consumers, i.e., encoder and decoder
drivers, of the xlnx_vcu clock provider to set the clock rate and
actually enable the clocks without relying on some pre-configuration.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-11-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:53 +0000 (08:16 +0100)]
soc: xilinx: vcu: make pll post divider explicit
According to the downstream driver documentation due to timing
constraints the output divider of the PLL has to be set to 1/2. Add a
helper function for that check instead of burying the code in one large
setup function.
The bit is undocumented and marked as reserved in the register
reference.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-10-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:52 +0000 (08:16 +0100)]
soc: xilinx: vcu: implement clock provider for output clocks
The VCU System-Level Control uses an internal PLL to drive the core and
MCU clock for the allegro encoder and decoder based on an external PL
clock.
In order be able to ensure that the clocks are enabled and to get their
rate from other drivers, the module must implement a clock provider and
register the clocks at the common clock framework. Other drivers are
then able to access the clock via devicetree bindings.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-9-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:51 +0000 (08:16 +0100)]
soc: xilinx: vcu: register PLL as fixed rate clock
Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is
pre-calculated when probing the driver. To still make the clock
framework aware of the PLL and to allow to configure other clocks based
on the PLL rate, register the PLL as a fixed rate clock.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-8-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:50 +0000 (08:16 +0100)]
soc: xilinx: vcu: implement PLL disable
The disabling of the PLL is not fully implemented, because according to
the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
be set to bring the PLL into reset.
Set the bits to disable the PLL.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-7-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:49 +0000 (08:16 +0100)]
soc: xilinx: vcu: add helpers for configuring PLL
The xvcu_set_vcu_pll_info function sets the rate of the PLL and enables
it, which makes it difficult to cleanly convert the driver to the common
clock framework.
Split the function and add separate functions for setting the rate,
enabling the clock and disabling the clock.
Also move the enable of the reference clock from probe to the helper
that enables the PLL.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-6-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:48 +0000 (08:16 +0100)]
soc: xilinx: vcu: add helper to wait for PLL locked
Extract a helper function to wait until the PLL is locked. Also,
disabling the bypass was buried in the exit path on the wait loop.
Separate the different steps and add a helper function to make the code
more readable.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-5-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:47 +0000 (08:16 +0100)]
soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
The coreclk field is newer read after being written to xlnx_vcu. Remove
the coreclk field from the xlnx_vcu and use a function local variable
instead.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-4-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:46 +0000 (08:16 +0100)]
clk: divider: fix initialization with parent_hw
If a driver registers a divider clock with a parent_hw instead of the
parent_name, the parent_hw is ignored and the clock does not have a
parent.
Fix this by initializing the parents the same way they are initialized
for clock gates.
Fixes:
ff258817137a ("clk: divider: Add support for specifying parents via DT/pointers")
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-3-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Michael Tretter [Thu, 21 Jan 2021 07:16:45 +0000 (08:16 +0100)]
ARM: dts: vcu: define indexes for output clocks
The VCU System-Level Control has 4 output clocks. Define indexes for
these clocks to allow to reference them in the device tree.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-2-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandru Ardelean [Mon, 1 Feb 2021 15:12:45 +0000 (17:12 +0200)]
clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
No major functional change. Noticed while checking the driver code that
this could be used.
Saves two lines.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-5-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandru Ardelean [Mon, 1 Feb 2021 15:12:44 +0000 (17:12 +0200)]
dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support
The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
driver needs to use different PFD & VCO limits.
For ZynqMP, these needs to be selected by using the
'adi,zynqmp-axi-clkgen-2.00.a' string.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-4-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandru Ardelean [Mon, 1 Feb 2021 15:12:43 +0000 (17:12 +0200)]
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
support these, this change adds a compatible string (i.e.
'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these
limits and apply them.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Mathias Tausen <mta@gomspace.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-3-alexandru.ardelean@analog.com
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandru Ardelean [Mon, 1 Feb 2021 15:12:42 +0000 (17:12 +0200)]
clk: axi-clkgen: replace ARCH dependencies with driver deps
The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-2-alexandru.ardelean@analog.com
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 8 Feb 2021 20:24:52 +0000 (12:24 -0800)]
Merge tag 'v5.12-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Kerneldoc fixes
- some new rk3368 clock ids related to camera input
* tag 'v5.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix DPHY gate locations on rk3368
clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: Demote non-conformant kernel-doc header in half-divider
clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
clk: rockchip: Remove unused/undocumented struct members from clk-cpu
clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
Uwe Kleine-König [Thu, 14 Jan 2021 15:16:25 +0000 (16:16 +0100)]
clk: Drop unused efm32gg driver
Support for this machine was just removed, so drop the now unused clk
driver, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20210114151630.128830-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Abel Vesa [Wed, 13 Jan 2021 12:53:08 +0000 (14:53 +0200)]
MAINTAINERS: Add section for NXP i.MX clock drivers
Add a section for NXP i.MX clock drivers and list myself
as the maintainer.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/1610542388-12078-1-git-send-email-abel.vesa@nxp.com
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 14 Jan 2021 22:10:57 +0000 (23:10 +0100)]
clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU
(mmss smmu), which has bootloader pre-set secure contexts.
In the event of a complete power loss, the secure contexts will be
reset and the hypervisor will crash the SoC.
To prevent this, and get a working multimedia subsystem, set this
GDSC as always on.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-10-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 14 Jan 2021 22:10:56 +0000 (23:10 +0100)]
clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
Hardware clock gating is supported on some of the clocks declared in
there: ignoring that it does exist may lead to unstabilities on some
firmwares.
Add the HWCG registers where applicable to stop potential crashes.
This was verified on a smartphone shipped with a recent MSM8998
firmware, which will experience random crashes without this change.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 14 Jan 2021 22:10:54 +0000 (23:10 +0100)]
clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs
and not generic alphas: this was producing bad effects over the entire
clock tree of MSM8998, where any GPLL child clock was declaring a false
clock rate, due to their parent also showing the same.
The issue resides in the calculation of the clock rate for the specific
Alpha PLL type, where Fabia has a different register layout; switching
the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate
(calculation) reading. While at it, also make these PLLs fixed since
their rate is supposed to *never* be changed while the system runs, as
this would surely crash the entire SoC.
Now all the children of all the PLLs are also complying with their
specified clock table and system stability is improved.
Fixes:
b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>