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Igor Gnatenko [Tue, 7 Jul 2015 10:05:04 +0000 (13:05 +0300)]
opencl: use versioned .so in mesa.icd
We must have versioned library in mesa.icd, because ICD loader would
fail if the mesa-devel package wasn't installed.
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Reported-by: Fabian Deutsch <fabian.deutsch@gmx.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512
Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Emil Velikov [Thu, 30 Jul 2015 14:18:54 +0000 (15:18 +0100)]
includes/GL: remove duplicated extension declarations from glx.h
All three of GLX_NV_float_buffer, GLX_EXT_texture_from_pixmap and
GLX_MESA_query_renderer have been in glxext.h for a while now.
As such we can drop this workaround/hack from the header.
v2: Remove the comment about GLX_NV_float_buffer.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Emil Velikov [Wed, 29 Jul 2015 17:13:50 +0000 (18:13 +0100)]
docs: rename/bump 10.7.0 release notes to 11.0.0
Recently a few drivers have grown OpenGL 4+ support so we might as
well go all the way to... 11 ;-)
v2: Don't forget to update the version file (Ilia)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Emil Velikov [Wed, 29 Jul 2015 14:44:32 +0000 (15:44 +0100)]
winsys/radeon: don't leak the fd when it is 0
Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue.
Although it did not consider the (very unlikely) case where we might end
up with the valid fd == 0.
Fixes:
28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash
table to fix ZaphodHeads.)
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 11:28:23 +0000 (12:28 +0100)]
configure.ac: check for mkostemp()
We can make use of it over mkstemp + fcntl in the egl/wayland code.
Cc: Axel Davy <axel.davy@ens.fr>
Suggested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 11:27:06 +0000 (12:27 +0100)]
egl/wayland: use drmGetNodeTypeFromFd helper instead of opencoding it
Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Boyan Ding <boyan.j.ding@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 11:24:11 +0000 (12:24 +0100)]
egl/wayland: use designated initializers
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 10:22:13 +0000 (11:22 +0100)]
egl: remove ifdef $(egl_extension) compile guards
All of these are already defined in the headers provided.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 10:01:55 +0000 (11:01 +0100)]
egl/wayland: libdrm is a hard requirement, treat it as such
Prompt at configure time if it's missing otherwise we'll fail later on
in the build. Remove ambiguous HAVE_LIBDRM guard.
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Fri, 10 Jul 2015 10:01:35 +0000 (11:01 +0100)]
egl: consolidate ifdef HAVE_LIBDRM blocks
Move the code around rather than having it scattered. No functional
change.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Emil Velikov [Thu, 9 Jul 2015 23:16:21 +0000 (00:16 +0100)]
configure.ac: null,android,gdi are not valid egl-platforms
... and update the documentation to reflect reality.
null and gdi are gone, and surfaceless is a recent addition.
v2: s/platforms/platform/ (spotted by Thomas)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Marek Olšák [Fri, 31 Jul 2015 22:51:00 +0000 (00:51 +0200)]
Revert "gallium/radeon: re-enable unsafe math for graphics shaders"
This reverts commit
8559f6ce62a9d5b52fa8189ba2352cd48bdabccf.
It causes hangs in DOTA 2 Reborn.
EdB [Fri, 31 Jul 2015 17:14:45 +0000 (19:14 +0200)]
clover: make dispatch matches functions def
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Vinson Lee [Thu, 30 Jul 2015 03:17:36 +0000 (20:17 -0700)]
gallivm: Fix GCC unused-variable warning.
lp_bld_tgsi_soa.c: In function 'lp_emit_immediate_soa':
lp_bld_tgsi_soa.c:3065:18: warning: unused variable 'size' [-Wunused-variable]
const uint size = imm->Immediate.NrTokens - 1;
^
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Adam Jackson [Fri, 31 Jul 2015 17:36:21 +0000 (13:36 -0400)]
glx: Fix missing bit decl for EXT_texture_integer
Missing from:
commit
b15aba940a3b6fc7c9bebc692968e7e9b72b9f29
Author: Adam Jackson <ajax@redhat.com>
Date: Tue Jul 21 11:43:42 2015 -0400
glx: Fix image size computation for EXT_texture_integer (v2)
Signed-off-by: Adam Jackson <ajax@redhat.com>
Matt Turner [Wed, 29 Jul 2015 17:47:51 +0000 (10:47 -0700)]
glsl: Initialize parse-state in constructor of lower_subroutine.
Static analysis tools don't like partial object initializations.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Adam Jackson [Tue, 21 Jul 2015 15:43:42 +0000 (11:43 -0400)]
glx: Fix image size computation for EXT_texture_integer (v2)
Without this this extension basically can't work in indirect contexts,
TexImage2D will compute the image size as 0 and we'll send no image data
to the server.
v2: Add EXT_texture_integer to the client extension list too (Ian)
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Marek Olšák [Thu, 30 Jul 2015 15:38:44 +0000 (17:38 +0200)]
radeonsi: copy *8_SNORM bits exactly in resource_copy_region
Disabling the FP16 mode didn't help.
If needed, we can use this trick for blits too, but not for scaled blits.
+ 4 piglits
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Tue, 28 Jul 2015 09:39:35 +0000 (11:39 +0200)]
r600g: early exit in r600_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Tue, 28 Jul 2015 09:39:35 +0000 (11:39 +0200)]
radeonsi: early exit in si_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 27 Jul 2015 17:01:21 +0000 (19:01 +0200)]
radeonsi: fix a regression since the resource_copy_region cleanup
Broken since:
46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 26 Jul 2015 19:08:18 +0000 (21:08 +0200)]
radeonsi: fix broken st/nine from merging tessellation
st/nine uses GENERIC slots greater than 60.
Marek Olšák [Fri, 24 Jul 2015 23:25:07 +0000 (01:25 +0200)]
radeonsi: move CP DMA functions to their own file
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 25 Jul 2015 14:15:48 +0000 (16:15 +0200)]
radeonsi: add a debug flag that disables printing ISA in shader dumps
Marek Olšák [Sat, 25 Jul 2015 14:15:48 +0000 (16:15 +0200)]
radeonsi: add a debug flag that disables printing TGSI in shader dumps
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Sat, 25 Jul 2015 14:15:48 +0000 (16:15 +0200)]
radeonsi: add a debug flag that disables printing the LLVM IR in shader dumps
This is for shader-db and should reduce size of shader dumps.
Marek Olšák [Fri, 10 Jul 2015 22:17:48 +0000 (00:17 +0200)]
radeonsi: store shader disassemblies in memory for future users
This will be used by the new ddebug pipe. I'm including it now to avoid
conflicts with other patches.
Marek Olšák [Sat, 25 Jul 2015 10:17:19 +0000 (12:17 +0200)]
radeonsi: don't use llvm.AMDIL.fraction for FRC and DFRAC
There are 2 reasons for this:
- LLVM optimization passes can work with floor
- there are patterns to select v_fract from floor anyway
There is no change in the generated code.
Marek Olšák [Sat, 25 Jul 2015 10:01:07 +0000 (12:01 +0200)]
gallium/radeon: re-enable unsafe math for graphics shaders
This reverts commit
4db985a5fa9ea985616a726b1770727309502d81.
The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.
Totals from affected shaders:
SGPRS: 151672 -> 150232 (-0.95 %)
VGPRS: 90620 -> 89776 (-0.93 %)
Code Size:
3980472 ->
3920836 (-1.50 %) bytes
LDS: 67 -> 67 (0.00 %) blocks
Scratch:
1357824 ->
1202176 (-11.46 %) bytes per wave
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Sat, 25 Jul 2015 15:24:08 +0000 (17:24 +0200)]
gallium/radeon: don't use rsq_action
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Sat, 25 Jul 2015 15:12:39 +0000 (17:12 +0200)]
gallium/radeon: move r600-specific code to r600g
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Sat, 25 Jul 2015 14:53:29 +0000 (16:53 +0200)]
gallium/radeon: remove unused variables and old comments
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Sat, 25 Jul 2015 09:26:18 +0000 (11:26 +0200)]
gallium/radeon: remove build_intrinsic and build_tgsi_intrinsic
duplicated now
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Sat, 25 Jul 2015 09:17:48 +0000 (11:17 +0200)]
gallivm: add LLVMAttribute parameter to lp_build_intrinsic
This will help remove some duplicated code from radeon.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Sat, 25 Jul 2015 13:55:45 +0000 (15:55 +0200)]
gallium/util: clear up that debug_get_flags_option returns a 64-bit mask
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Marek Olšák [Fri, 24 Jul 2015 22:53:16 +0000 (00:53 +0200)]
radeonsi: completely rework updating descriptors without CP DMA
The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
CP DMA doesn't serve as a middle man to update them.
This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
If not, we'll know the issue is not here.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Francisco Jerez [Thu, 30 Jul 2015 11:45:57 +0000 (14:45 +0300)]
i965/fs: Fix regression with SIMD8 VS since
b5f1a48e234d47b24df38cb562cffb8941d43795.
With num_direct_uniforms == 0 there's no space allocated in the
param_size array for the one block of direct uniforms -- On the FS
stage this would be a harmless no-op because it would simply re-set
one of the param_size entries allocated for the sampler units to zero,
but on the VS stage it has been reported to cause memory corruption
followed by a crash -- Surprising how a full piglit run on Gen8 didn't
catch it.
Reported-and-reviewed-by: "Lofstedt, Marta" <marta.lofstedt@intel.com>
Ben Widawsky [Fri, 31 Jul 2015 02:16:32 +0000 (19:16 -0700)]
i965/gen9: Add hs, ds, and cs thread + urb info
For SKL: These are the production values.
For BXT: These are low estimates to enable platforms.
This patch was originally part of
i965/skl: Add production thread counts and URB size
but was split out at Jordan's request (which I found to be reasonable).
Note on stable inclusion: 10.6 does not care about hs, and ds. It does care
about cs, but since Jordan was the one that asked me to extract it, I'll leave
it up to him to deal with a backport to stable is required.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ben Widawsky [Fri, 31 Jul 2015 02:12:15 +0000 (19:12 -0700)]
i965/bxt: Use more conservative thread counts
Since we really do not know what may occur in the future, pick a more
conservative value for thread counts until we know better what values are
correct. As far as I can tell, the old values will work fine, but some of the
registers seem to indicate that going even lower is possible and the purpose of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ben Widawsky [Wed, 29 Jul 2015 19:35:24 +0000 (12:35 -0700)]
i965/skl: Add production thread counts and URB size
This patch adjusts the SKL values to the best known values we have.
v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the
GEN9_FEATURES macro, however, doing that would require updating BXT values, and
Jordan requested I not do that. Conveniently, this request makes a lot of sense
wrt to stable backport as HS, and DS do not even exist there.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Eric Anholt [Thu, 30 Jul 2015 18:16:13 +0000 (11:16 -0700)]
vc4: Lower uniform loads to scalar in NIR.
This also moves the vec4-to-byte-addressing math into NIR, so that
algebraic has a chance at it.
Eric Anholt [Thu, 30 Jul 2015 00:27:54 +0000 (17:27 -0700)]
vc4: Move some FS input lowering into NIR.
Eric Anholt [Thu, 30 Jul 2015 00:29:39 +0000 (17:29 -0700)]
vc4: Move program keys to the header file.
I want to be able to inspect them from other files for lowering passes in
NIR.
Eric Anholt [Thu, 30 Jul 2015 00:16:26 +0000 (17:16 -0700)]
vc4: Lower NIR inputs to scalar as well.
For now this is just scalarizing, but it also means we'll get to dump a
bunch of QIR-based lowering in a moment.
Eric Anholt [Wed, 29 Jul 2015 22:52:18 +0000 (15:52 -0700)]
vc4: Start adding a NIR-based output lowering pass.
For now, this just splits up store_output intrinsics to be scalars, and
drops unused outputs in the coordinate shader. My goal is to be able to
drop a bunch of my VC4-specific optimization by letting NIR handle it.
Eric Anholt [Wed, 29 Jul 2015 19:16:50 +0000 (12:16 -0700)]
vc4: Mark our shaders as single-threaded.
I had my understanding of this bit flipped. We're using the full register
space, so we need to say so.
Eric Anholt [Wed, 29 Jul 2015 21:41:22 +0000 (14:41 -0700)]
vc4: Avoid leaking indirect array access UBOs.
Eric Anholt [Wed, 29 Jul 2015 21:40:10 +0000 (14:40 -0700)]
vc4: Avoid overflowing various static tables.
Eric Anholt [Wed, 29 Jul 2015 19:20:33 +0000 (12:20 -0700)]
vc4: Fix return values from recent validation changes.
Kai Wasserbäch [Thu, 30 Jul 2015 18:32:36 +0000 (20:32 +0200)]
docs: trivial cleanup of GL3.txt, remove redundant radeonsi entries.
Follow-up to
1b2b0e42ce47bfd1fcb5513ed2c23b9bb7a5a5b8
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 30 Jul 2015 10:44:50 +0000 (20:44 +1000)]
st/mesa: don't draw instead of asserting in transform feedback
if we get a request to take the count from feedback, but there
is no buffer to take it from, just draw as if we got 0 vertices
so nothing.
This fixes this assert killing the ogl conform, and a piglit
test I've sent.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Fri, 3 Jul 2015 22:35:35 +0000 (08:35 +1000)]
mesa: remove now unused _mesa_get_uniform_location
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Sat, 25 Jul 2015 02:39:43 +0000 (12:39 +1000)]
mesa: remove now unused subscript validations
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Sat, 25 Jul 2015 02:33:53 +0000 (12:33 +1000)]
mesa: fix and simplify resource query for arrays
This removes the need for multiple functions designed to validate an array
subscript and replaces them with a call to a single function.
The change also means that validation is now only done once and the index
is retrived at the same time, as a result the getUniformLocation code can
be simplified saving an extra hash table lookup (and yet another
validation call).
This chage also fixes some tests in:
ES31-CTS.program_interface_query.uniform
V3: rebase on subroutines, and move the resource index array == 0
check into _mesa_GetProgramResourceIndex() to simplify things further
V2: Fix bounds checks for program input/output, split unrelated comment fix
and _mesa_get_uniform_location() removal into their own patch.
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Neil Roberts [Wed, 29 Jul 2015 16:40:37 +0000 (17:40 +0100)]
i965/bxt: Don't use brw_device_info_skl_early on BXT
Previously it could end up using the “SKL early” device on BXT
depending on the revision number. This would probably break things
because for example has_llc would be wrong.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sat, 4 Jul 2015 05:43:15 +0000 (15:43 +1000)]
glsl: set stage flag for structs and arrays in resource list
This fixes the remaining failing tests in:
ES31-CTS.program_interface_query.uniform-types
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Wed, 29 Jul 2015 09:51:46 +0000 (10:51 +0100)]
docs: consolidate radeonsi in GL3.txt
move into DONE for GL4.0 and GL4.1
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 22 Jul 2015 00:24:39 +0000 (01:24 +0100)]
radeonsi: enable GL4.1 and update documentation (v2)
This enables GL4.1 for radeonsi, and updates the
docs in the correct places.
v2: enable only for llvm 3.7 which has fixes in place.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 20 Jul 2015 01:37:14 +0000 (02:37 +0100)]
radeonsi: add GS multiple streams support (v2)
This is the final piece for ARB_gpu_shader5,
The code is based on the r600 code from Glenn Kennard,
and myself.
While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used to limit the changes in registers. Otherwise
my initial attempts either regressed GS texelFetch tests
or primitive-id-restart. The current code has no regressions
in piglit.
This commit doesn't enable ARB_gpu_shader5, since that just
bumps the glsl level to 4.00, so I'll just do a separate patch
for 4.10.
v1.1: fix bug introduced in rebase.
v2: Address Marek's review comments,
remove my llvm stream code for simpler C,
move gsvs_ring and gs_next_vertex to arrays.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Anuj Phogat [Wed, 29 Jul 2015 17:15:03 +0000 (10:15 -0700)]
Delete unused functions in format parser
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Anuj Phogat [Wed, 29 Jul 2015 16:57:26 +0000 (09:57 -0700)]
i965: Change the type of max_{vs, hs, ...}_threads variables to unsigned
Fixes following compiler warning:
brw_cs.cpp:386:27: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Anuj Phogat [Wed, 29 Jul 2015 16:41:18 +0000 (09:41 -0700)]
Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Jose Fonseca [Wed, 29 Jul 2015 19:45:09 +0000 (20:45 +0100)]
gallium/auxiliary: Ensure c99_math.h is included.
As it is needed for exp2.
Trivial.
Roland Scheidegger [Wed, 29 Jul 2015 20:20:04 +0000 (22:20 +0200)]
c99_math: (trivial) implement exp2 for MSVC too
Unsurprisingly doesn't build otherwise with old msvc.
Ben Widawsky [Wed, 29 Jul 2015 02:52:49 +0000 (19:52 -0700)]
i965/bxt: Support 3src simd16 instructions
This is easily accomplished by moving simd16 3src to GEN9_FEATURES.
v2: small cleanup to make it more similar to GEN8_FEATURES
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Wed, 22 Jul 2015 15:04:28 +0000 (16:04 +0100)]
targets/dri: scons: add missing link against libdrm
Otherwise the final dri module will have (additional) unresolved
symbols.
Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviwed-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Fri, 17 Jul 2015 17:18:20 +0000 (18:18 +0100)]
svga: scons: remove unused HAVE_SYS_TYPES_H define
There isn't a single instance in mesa that
mentions HAVE_SYS_TYPES_H, other than this file.
Cc: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Matt Turner [Thu, 16 Jul 2015 04:29:21 +0000 (21:29 -0700)]
glsl: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:42 +0000 (23:15 -0700)]
mesa: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 06:15:32 +0000 (23:15 -0700)]
mesa/math: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 06:15:19 +0000 (23:15 -0700)]
program: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 06:15:10 +0000 (23:15 -0700)]
swrast: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 06:15:01 +0000 (23:15 -0700)]
tnl: Avoid double promotion.
There are a couple of unrelated changes in t_vb_lighttmp.h that I hope
you'll excuse -- there's a block of code that's duplicated modulo a few
trivial differences that I took the liberty of fixing.
Matt Turner [Mon, 13 Jul 2015 06:14:54 +0000 (23:14 -0700)]
vbo: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 01:01:54 +0000 (18:01 -0700)]
util: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 01:01:42 +0000 (18:01 -0700)]
gallium/auxiliary: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Matt Turner [Sun, 12 Jul 2015 19:37:00 +0000 (12:37 -0700)]
nir: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Sun, 12 Jul 2015 07:13:45 +0000 (00:13 -0700)]
i965: Use float calculations when double is unnecessary.
Literals without an f/F suffix are of type double, and implicit
conversion rules specify that the float in (float op double) be
converted to a double before the operation is performed. I believe float
execution was intended (in nearly all cases) or is sufficient (in the
case of gen7_urb.c).
Removes a lot of float <-> double conversion instructions and replaces
many double instructions with float instructions which are cheaper.
text data bss dec hex filename
4928659 195160 26192
5150011 4e953b i965_dri.so before
4928315 195152 26192
5149659 4e93db i965_dri.so after
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 13 Jul 2015 22:19:54 +0000 (15:19 -0700)]
gallium/auxiliary: Use exp2(x) instead of pow(2.0, x).
Matt Turner [Mon, 13 Jul 2015 22:19:33 +0000 (15:19 -0700)]
program: Use exp2(x) instead of pow(2.0, x).
Matt Turner [Sun, 12 Jul 2015 05:46:19 +0000 (22:46 -0700)]
mesa: Use floats for viewport bounds.
ARB_viewport_array specifies that DEPTH_RANGE consists of double-
precision parameters (corresponding commit
d4dc35987), and a preparatory
commit (
6340e609a) added _mesa_get_viewport_xform() which returned
double-precision scale[3] and translate[3] vectors, even though X, Y,
Width, and Height were still floats.
All users of _mesa_get_viewport_xform() immediately convert the double
scale and translation vectors into floats (which were floats originally,
but were converted to doubles in _mesa_get_viewport_xform(), sigh).
i965 at least cannot consume doubles (see SF_CLIP_VIEWPORT). If we want
to pass doubles to hardware, we should have a different function that
does that.
Acked-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Matt Turner [Thu, 16 Jul 2015 04:28:56 +0000 (21:28 -0700)]
c99_math: Implement exp2f for MSVC.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Thu, 16 Jul 2015 03:54:46 +0000 (20:54 -0700)]
glsl: Remove MSVC implementations of copysign and isnormal.
Non-Gallium parts of Mesa require MSVC 2013 which provides these.
Francisco Jerez [Mon, 27 Jul 2015 15:51:01 +0000 (18:51 +0300)]
i965/fs: Make the default builder 64-wide before entering the optimization loop.
Not a typo. Replace the default builder with one of bogus width to
catch cases in which optimization passes assume that the default
dispatch width is good enough. The execution controls of instructions
emitted during optimization should in general match the original code
that is being manipulated. Many of the problems fixed in this series
were caught by the assertions introduced in this patch.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:42:31 +0000 (18:42 +0300)]
i965/fs: Don't set exec_all on instructions wider than the original in lower_simd_width.
This could have led to somewhat increased bandwidth usage for lowered
texturing instructions on Gen4 (which is the only case in which
lower_width may be greater than inst->exec_size). After the previous
patches the invariant mentioned in the comment should no longer be
assumed by any of the other optimization and lowering passes, so the
exec_all() call shouldn't be necessary anymore.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:28:39 +0000 (18:28 +0300)]
i965/fs: Initialize a builder explicitly in the gen4 send dependency work-arounds.
Instead of relying on the default one. This shouldn't lead to any
functional changes because DEP_RESOLVE_MOV overrides the execution
size of the instruction anyway and other execution controls are
irrelevant.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Sat, 11 Jul 2015 02:49:49 +0000 (19:49 -0700)]
i965/cfg: Assert that cur_do/while/if pointers are non-NULL.
More.. like in commit
4d93a07c.
Ilia Mirkin [Wed, 29 Jul 2015 15:01:08 +0000 (11:01 -0400)]
nvc0/ir: cache vertex out base so that we don't recompute again
The global CSE pass stinks and is unable to pull this out. Easy enough
to handle it here and avoid generating unnecessary special register
loads (which can allegedly be quite slow).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 29 Jul 2015 13:37:14 +0000 (09:37 -0400)]
nvc0/ir: output base for reading is based on laneid
PFETCH retrieves the address for incoming vertices, not output vertices
in TCS. For output vertices, we must use the laneid as a base.
Fixes barrier piglit test, which was failing for entirely non-barrier
reasons, but rather that it was (a) trying to draw multiple patches and
(b) the incoming patch size was not the same as the outgoing patch size.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Wed, 29 Jul 2015 12:37:52 +0000 (15:37 +0300)]
Revert "pipe-loader: simplify pipe_loader_drm_probe"
This reverts commit
a27ec5dc460b91dc44675f48cddbbb2631ee824f. It
breaks the intended behaviour of pipe_loader_probe() with ndev==0 as
relied upon by clover to query the number of devices available to the
pipe loader in the system.
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
Francisco Jerez [Mon, 27 Jul 2015 16:18:51 +0000 (19:18 +0300)]
i965/fs: Switch opt_cse() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:41:18 +0000 (18:41 +0300)]
i965/fs: Switch lower_logical_sends() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:34:43 +0000 (18:34 +0300)]
i965/fs: Switch lower_load_payload() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 17:14:41 +0000 (20:14 +0300)]
i965/fs: Don't rely on the default builder to create a null register in emit_spill.
It's not guaranteed to have the same width as the instruction
generating the spilled variable.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:15:44 +0000 (18:15 +0300)]
i965/fs: Set up the builder execution size explicitly in opt_sampler_eot().
opt_sampler_eot() was relying on the default builder to have the same
width as the sampler and FB write opcodes it was eliminating, the
channel selects didn't matter because the builder was only being used
to allocate registers, no new instructions were being emitted with it.
A future commit will change the width of the default builder what will
break this assumption, so initialize it explicitly here.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 16:20:50 +0000 (19:20 +0300)]
i965/fs: Initialize a builder explicitly in opt_peephole_predicated_break().
This wasn't taking into account the execution controls of the original
instruction, but it was most likely not a bug because control flow
instructions are typically full width.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 16:27:30 +0000 (19:27 +0300)]
i965/fs: Set execution controls explicitly in opt_peephole_sel().
Emit the SELs and MOVs with the same execution controls as the
original MOVs, and the CMP with the same execution controls as the IF.
Also explicitly check that the execution controls of any pair of MOVs
being folded into a SEL are compatible (which is almost always going
to be the case), since otherwise it would seem wrong to initialize the
builder object below from the then_mov instruction only.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 15:38:59 +0000 (18:38 +0300)]
i965/fs: Set execution controls correctly in lower_integer_multiplication().
lower_integer_multiplication() was ignoring the execution controls of
the original MUL instruction. Fix it by using the new fs_builder
constructor.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 14:55:49 +0000 (17:55 +0300)]
i965/fs: Set execution controls correctly for lowered pull constant loads.
demote_pull_constants() was ignoring the execution size and channel
selects of the instruction that wanted the constant, which doesn't
matter for uniform pull constant loads because all channels get the
same scalar value, but it might for varying pull constant loads. Fix
it by using the new fs_builder() constructor that takes care of
setting execution controls compatible with the instruction passed as
argument.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 16:09:45 +0000 (19:09 +0300)]
i965/fs: Set the execution size of the MOVs correctly in opt_combine_constants().
The execution size was being left equal to the default of 8/16, which
AFAICT would have overwritten components other than the one we wanted
to initialize and could potentially have corrupted other registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>