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Wei Mi [Fri, 8 Jul 2016 21:08:09 +0000 (21:08 +0000)]
Allow dead insts to be kept in DeadRemat only when they are rematerializable.
Because isReallyTriviallyReMaterializableGeneric puts many limits on
rematerializable instructions, this fix can prevent instructions with
tied virtual operands and instructions with virtual register uses from
being kept in DeadRemat, so as to workaround the live interval consistency
problem for the dummy instructions kept in DeadRemat.
But we still need to fix the live interval consistency problem. This patch
is just a short time relieve. PR28464 has been filed as a reminder.
Differential Revision: http://reviews.llvm.org/D19486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274928
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Xinliang David Li [Fri, 8 Jul 2016 20:55:26 +0000 (20:55 +0000)]
Rename LoopAccessAnalysis to LoopAccessLegacyAnalysis /NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274927
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Sanjay Patel [Fri, 8 Jul 2016 20:53:29 +0000 (20:53 +0000)]
[InstCombine] don't form select from logic ops if it's unlikely that we'll eliminate any ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274926
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Sanjay Patel [Fri, 8 Jul 2016 20:35:53 +0000 (20:35 +0000)]
adjust test so it won't completely optimize away
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274925
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 20:29:42 +0000 (20:29 +0000)]
AArch64: Avoid implicit iterator conversions, NFC
Avoid implicit conversions from MachineInstrBundleInstr to MachineInstr*
in the AArch64 backend, mainly by preferring MachineInstr& over
MachineInstr* when a pointer isn't nullable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274924
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Sanjay Patel [Fri, 8 Jul 2016 20:22:27 +0000 (20:22 +0000)]
add tests for multi-use folding to select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274922
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Xinliang David Li [Fri, 8 Jul 2016 20:21:32 +0000 (20:21 +0000)]
Remove duplicate inclusion /NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274921
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 20:21:17 +0000 (20:21 +0000)]
ARM: Remove implicit iterator conversions, NFC
Remove remaining implicit conversions from MachineInstrBundleIterator to
MachineInstr* from the ARM backend. In most cases, I made them less attractive
by preferring MachineInstr& or using a ranged-based for loop.
Once all the backends are fixed I'll make the operator explicit so that this
doesn't bitrot back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274920
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Justin Bogner [Fri, 8 Jul 2016 20:14:27 +0000 (20:14 +0000)]
TableGen: Update style in CodeGenIntrinsics. NFC
Ran clang-format to remove the namespace indentation, and stopped
repeating names in doc comments since I was updating every line
anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274919
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Dehao Chen [Fri, 8 Jul 2016 20:12:44 +0000 (20:12 +0000)]
Remove inline hints computation from SampleProfile.cpp
Summary: As we will move to use uniformed hotness check in inliner, we do not need inline hints in SampleProfile pass any more.
Reviewers: dnovillo, davidxl
Subscribers: eraman, llvm-commits
Differential Revision: http://reviews.llvm.org/D19287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274918
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Nico Weber [Fri, 8 Jul 2016 19:52:19 +0000 (19:52 +0000)]
Revert r274829, it caused PR28472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274916
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Simon Pilgrim [Fri, 8 Jul 2016 19:51:08 +0000 (19:51 +0000)]
[X86] Regenerated bitreverse tests to demonstrate what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274915
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Simon Pilgrim [Fri, 8 Jul 2016 19:48:33 +0000 (19:48 +0000)]
[X86] Added bitreverse tests for non-legal types
Requested on D21578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274914
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:41:40 +0000 (19:41 +0000)]
Sparc: Avoid implicit iterator conversions, NFC
Remove the only implicit conversions from MachineInstrBundleIterator to
MachineInstr* in the Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274913
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:36:40 +0000 (19:36 +0000)]
WebAssembly: Avoid implicit iterator conversions, NFC
Avoid implicit conversions from MachineInstrBundleIterator to
MachineInstr* in the WebAssembly backend by preferring MachineInstr&
over MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274912
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:31:47 +0000 (19:31 +0000)]
AsmPrinter: Avoid implicit iterator conversions in DbgValueHistoryCalculator, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274911
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Davide Italiano [Fri, 8 Jul 2016 19:30:06 +0000 (19:30 +0000)]
[CrossDSOCFI] Change the pass so that it doesn't require doInitialization()
Differential Revision: http://reviews.llvm.org/D21357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274910
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Simon Pilgrim [Fri, 8 Jul 2016 19:23:29 +0000 (19:23 +0000)]
[X86][AVX2] Add support for target shuffle combining to VPERMPD/VPERMQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274908
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:23:12 +0000 (19:23 +0000)]
SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274907
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:16:05 +0000 (19:16 +0000)]
AMDGPU: Remove implicit iterator conversions, NFC
Remove remaining implicit conversions from MachineInstrBundleIterator to
MachineInstr* from the AMDGPU backend. In most cases, I made them less
attractive by preferring MachineInstr& or using a ranged-based for loop.
Once all the backends are fixed I'll make the operator explicit so that
this doesn't bitrot back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274906
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Davide Italiano [Fri, 8 Jul 2016 19:13:40 +0000 (19:13 +0000)]
[SCCP] Fold constants as we build them whne visiting cast instructions.
This should be slightly more efficient and could avoid spurious overdefined
markings, as Eli pointed out.
Differential Revision: http://reviews.llvm.org/D22122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274905
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:11:40 +0000 (19:11 +0000)]
SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274904
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:07:09 +0000 (19:07 +0000)]
SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274903
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 19:00:17 +0000 (19:00 +0000)]
AMDGPU: Make infinite loop clear, NFC
Change a while loop that was checking for nullptr on an
iterator-to-pointer conversion to an infinite for loop. Now it's clear
that the condition doesn't terminate.
The only change in behaviour is if an invalid iterator (holding nullptr)
was passed into AMDGPUCFGStructurizer::reversePredicateSetter. There
are only two callers, and they both dereference the iterator before
sending it in, so rather than adding an early return to avoid the loop
I've just asserted (using a static_cast, to avoid an implicit conversion
to pointer).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274902
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 18:36:41 +0000 (18:36 +0000)]
SelectionDAG: Avoid implicit iterator conversions in FastISel, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274899
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 18:26:20 +0000 (18:26 +0000)]
Target: Avoid getFirstTerminator() => pointer, NFC
Stop using an implicit conversion from the return of
MachineBasicBlock::getFirstTerminator to MachineInstr*. In two cases,
directly dereference to a MachineInstr& since later code assumes it's
valid. In a third case, change to an iterator since later code checks
against MachineBasicBlock::end.
Although the fix for the third case avoids undefined behaviour, I expect
this doesn't cause a functionality change in practice (since the basic
block already has a terminator).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274898
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 17:43:08 +0000 (17:43 +0000)]
CodeGen: Avoid iterator conversions in TwoAddressInstructionPass, NFC
Mostly through preferring MachineInstr&, avoid implicit conversions from
iterator to pointer.
Although this may bitrot (since there are other uses blocking me from
removing the implicit operator), this removes the last of the implicit
conversions from MachineInstrBundleIterator to MachineInstr* in the
LLVMCodeGen build target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274893
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 17:28:40 +0000 (17:28 +0000)]
CodeGen: Use MachineInstr& in StackSlotColoring, NFC
Avoid implicit iterator to pointer conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274892
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Sanjay Patel [Fri, 8 Jul 2016 17:26:47 +0000 (17:26 +0000)]
[InstCombine] check for one-use before turning simple logic op into a select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274891
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Justin Bogner [Fri, 8 Jul 2016 17:25:18 +0000 (17:25 +0000)]
IR: Set a TargetPrefix for nvvm intrinsics
Since these are named nvvm_* rather than nvptx_*, we also need to
update getArchTypePrefix. It's a bit unusual for getArchTypePrefix not
to match the backend name, but I think this fits the intent of the
function in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274890
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Simon Pilgrim [Fri, 8 Jul 2016 17:19:13 +0000 (17:19 +0000)]
[SLPVectorizer][X86] Added fma vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274889
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Duncan P. N. Exon Smith [Fri, 8 Jul 2016 17:16:57 +0000 (17:16 +0000)]
CodeGen: Use MachineInstr& in RegisterScavenging, NFC
Prefer MachineInstr& in order to avoid implicit conversions from
MachineInstrBundleIterator to MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274888
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Sanjay Patel [Fri, 8 Jul 2016 17:12:27 +0000 (17:12 +0000)]
add test to show multi-use output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274887
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Matt Arsenault [Fri, 8 Jul 2016 17:06:48 +0000 (17:06 +0000)]
AMDGPU: Minor adjustment to r274817
The commit message is inaccurate, modifiesRegister
will check for partial defs of exec.
We currently don't ever emit partial defs of exec,
so it doesn't really matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274886
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Simon Pilgrim [Fri, 8 Jul 2016 17:01:42 +0000 (17:01 +0000)]
[X86][AVX] Added combine test that should simplify to insertps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274884
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Sanjay Patel [Fri, 8 Jul 2016 17:01:15 +0000 (17:01 +0000)]
[InstCombine] allow or(sext(A), B) --> A ? -1 : B transform for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274883
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Zachary Turner [Fri, 8 Jul 2016 16:57:14 +0000 (16:57 +0000)]
Try to fix compilation error in DebugInfoPDBTests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274881
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Zhan Jun Liau [Fri, 8 Jul 2016 16:50:02 +0000 (16:50 +0000)]
[SystemZ] Add support for the .word directive.
Summary: Branch off the work to add support for the .word directive,
using addAliasForDirective.
Reviewers: koriakin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D22142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274878
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Chad Rosier [Fri, 8 Jul 2016 16:48:40 +0000 (16:48 +0000)]
[DSE] Minor refactor based on D21007. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274877
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Sanjay Patel [Fri, 8 Jul 2016 16:39:53 +0000 (16:39 +0000)]
add vector tests to show missing transform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274876
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David Majnemer [Fri, 8 Jul 2016 16:39:00 +0000 (16:39 +0000)]
[CodeGen, TargetPassConfig] Remove a race from createRegAllocPass
The createRegAllocPass reads and writes to a global variable 'Registry'
via calls to getDefault and setDefault. Run this under a call_once to
avoid races.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274875
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Matt Arsenault [Fri, 8 Jul 2016 16:29:11 +0000 (16:29 +0000)]
PeepholeOptimizer: Make pass name match DEBUG_TYPE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274874
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Zhan Jun Liau [Fri, 8 Jul 2016 16:18:40 +0000 (16:18 +0000)]
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274869
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Sanjay Patel [Fri, 8 Jul 2016 16:11:48 +0000 (16:11 +0000)]
minimize tests
The cmp and load aren't required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274864
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Eric Liu [Fri, 8 Jul 2016 16:09:51 +0000 (16:09 +0000)]
Move setName after accessing Name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274862
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Eric Liu [Fri, 8 Jul 2016 16:09:48 +0000 (16:09 +0000)]
Make a std::string copy of StringRef Name so that it remains valid when the original Name is overridden.
Summary: lib/IR/AutoUpgrade.cpp:348 and lib/IR/AutoUpgrade.cpp:350 upset sanitizer.
Reviewers: bkramer
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D22140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274861
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Sanjay Patel [Fri, 8 Jul 2016 16:06:38 +0000 (16:06 +0000)]
regenerate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274860
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Chris Dewhurst [Fri, 8 Jul 2016 15:33:56 +0000 (15:33 +0000)]
[Sparc] Leon errata fix passes.
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor.
The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these.
Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent.
Differential Revision: http://reviews.llvm.org/D21960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274856
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Sjoerd Meijer [Fri, 8 Jul 2016 15:32:01 +0000 (15:32 +0000)]
Do not expand SDIV when compiling for minimum code size
Differential Revision: http://reviews.llvm.org/D22139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274855
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Anna Thomas [Fri, 8 Jul 2016 15:18:56 +0000 (15:18 +0000)]
InstCombine rule to fold truncs whose value is available
We can fold truncs whose operand feeds from a load, if the trunc value
is available through a prior load/store.
This change is from: http://reviews.llvm.org/D21246, which folded the
trunc but missed the bitcast or ptrtoint/inttoptr required in the RAUW
call, when the load type didnt match the prior load/store type.
Differential Revision: http://reviews.llvm.org/D21791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274853
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Valery Pykhtin [Fri, 8 Jul 2016 15:12:46 +0000 (15:12 +0000)]
[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)
Differential Revision: http://reviews.llvm.org/D22049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274852
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Sjoerd Meijer [Fri, 8 Jul 2016 14:17:09 +0000 (14:17 +0000)]
Addressing post-commit comments regarding not expanding UDIV;
we don't expand only when compiling for minimum code size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274847
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Simon Pilgrim [Fri, 8 Jul 2016 13:28:34 +0000 (13:28 +0000)]
[X86][SSE] Improve constant folding tests for CVTSD/CVTSS/CVTTSD/CVTTSS
As discussed on D22106, improve the testing for constant folding sse scalar conversion intrinsics to ensure we are correctly handling special/out of range cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274846
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Sjoerd Meijer [Fri, 8 Jul 2016 12:54:43 +0000 (12:54 +0000)]
Code size optimisation: don't expand a div to a mul and and a shift sequence.
As a result, the urem instruction will not be expanded to a sequence of umull,
lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod.
Differential Revision: http://reviews.llvm.org/D22131
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274843
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Vassil Vassilev [Fri, 8 Jul 2016 12:00:08 +0000 (12:00 +0000)]
[modules] Add missing includes.
Patch by Cristina Cristescu!
Reviewed by Adrian Prantl (D21985)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274838
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Pankaj Gode [Fri, 8 Jul 2016 11:13:59 +0000 (11:13 +0000)]
[AArch64] Macro fusion of simple ALU ops with branches for Broadcom's Vulcan
Support for the macro fusion of simple ALU ops with branches for the Vulcan sub-target.
Patch by Meador Inge <meadori@gmail.com>
Differential Revision: http://reviews.llvm.org/D22042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274837
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Simon Pilgrim [Fri, 8 Jul 2016 10:39:12 +0000 (10:39 +0000)]
[X86][SSE] Accept any shuffle mask that is all zeroes
Until we have a better way to extract constants through bitcasted build vectors (and how to handle undefs of partial lanes etc.) at least accept build vectors that are all zeroes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274833
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Matt Arsenault [Fri, 8 Jul 2016 07:05:00 +0000 (07:05 +0000)]
Bug 28444: Fix assertion when extract_vector_elt has mismatched type
For some reason extract_vector_elt is sometimes allowed to have
a different result type than the vector element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274829
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Craig Topper [Fri, 8 Jul 2016 06:14:47 +0000 (06:14 +0000)]
[AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift intrinsics.
I'm not sure if clang ever used these builtin names or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274827
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Craig Topper [Fri, 8 Jul 2016 06:14:41 +0000 (06:14 +0000)]
[X86] Remove intrinsics that already have autoupgrade support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274826
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Wei Mi [Fri, 8 Jul 2016 03:32:49 +0000 (03:32 +0000)]
[PM] Port UnreachableBlockElim to the new Pass Manager
Differential Revision: http://reviews.llvm.org/D22124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274824
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Mehdi Amini [Fri, 8 Jul 2016 01:13:41 +0000 (01:13 +0000)]
Add an assertion for the value enumerator (bitcode writer) NFC
I have an LTO snapshot (for which I don't have sources) that can't
be read back by LLVM. It seems the writer emitted broken bitcode
and this assertions aims at catching such cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274819
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Matt Arsenault [Fri, 8 Jul 2016 00:55:44 +0000 (00:55 +0000)]
AMDGPU: Move si_mask_branch register operand to be a use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274818
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Matt Arsenault [Fri, 8 Jul 2016 00:55:39 +0000 (00:55 +0000)]
AMDGPU: Cleanup. Use definesRegister instead of manual loop
Also this will be more precise since it will check
exec_lo/exec_hi writes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274817
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Saleem Abdulrasool [Fri, 8 Jul 2016 00:48:22 +0000 (00:48 +0000)]
ARM: support high registers in __builtin_longjmp on WoA
Windows on ARM uses a pure thumb-2 environment. This means that it can select a
high register when doing a __builtin_longjmp. We would use a tLDRi which would
truncate the register to a low register. Use a t2LDRi12 to get the full
register file access. Tweak the code to just load into PC, as that is an
interworking branch on all supported cores anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274815
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Andrew Kaylor [Fri, 8 Jul 2016 00:35:39 +0000 (00:35 +0000)]
Temporarily remove a test case to unblock PPC bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274813
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Andrew Kaylor [Fri, 8 Jul 2016 00:32:58 +0000 (00:32 +0000)]
Temporarily remove one test run line to unblock PPC bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274812
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Piotr Padlewski [Fri, 8 Jul 2016 00:28:29 +0000 (00:28 +0000)]
Fix LTO document
Summary: fixed very old document
Reviewers: tejohnson, pcc
Subscribers: mehdi_amini, eraman, llvm-commits
Differential Revision: http://reviews.llvm.org/D22121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274811
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Jacques Pienaar [Thu, 7 Jul 2016 23:36:04 +0000 (23:36 +0000)]
[lanai] Use peephole optimizer to generate more conditional ALU operations.
Summary:
* Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations;
* Add predicated type with default always true to RR instructions in LanaiInstrInfo.td;
* Move LanaiSetflagAluCombiner into optimizeCompare;
* The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test;
* Remove unused MachineOperand flags;
Reviewers: eliben
Subscribers: aemerson
Differential Revision: http://reviews.llvm.org/D22072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274807
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Michael Kuperstein [Thu, 7 Jul 2016 22:50:23 +0000 (22:50 +0000)]
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc
xorl + setcc is generally the preferred sequence due to the partial register
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.
This fixes PR28146.
The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD)
which was not appreciated by fast regalloc on 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274802
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Vedant Kumar [Thu, 7 Jul 2016 22:45:28 +0000 (22:45 +0000)]
[tsan] Try harder to not instrument gcov counters
GCOVProfiler::emitProfileArcs() can create many variables with names
starting with "__llvm_gcov_ctr", so llvm appends a numeric suffix to
most of them. Teach tsan about this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274801
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Kevin Enderby [Thu, 7 Jul 2016 22:11:42 +0000 (22:11 +0000)]
Add checks to the MachOObjectFile() constructor to make sure load commands sizes
are the correct multiple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274798
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Davide Italiano [Thu, 7 Jul 2016 21:14:36 +0000 (21:14 +0000)]
[PM] Port InstSimplify to the new pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274796
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Anna Thomas [Thu, 7 Jul 2016 20:51:42 +0000 (20:51 +0000)]
[DSE] Remove dead stores in end blocks containing fence
We can remove dead stores in the presence of fence instructions. Fence
does not change an otherwise thread local store to visible.
reviewers: reames, dexonsmith, jfb
Differential Revision: http://reviews.llvm.org/D22001
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274795
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Rui Ueyama [Thu, 7 Jul 2016 20:21:50 +0000 (20:21 +0000)]
Add a missing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274794
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Rui Ueyama [Thu, 7 Jul 2016 20:19:19 +0000 (20:19 +0000)]
Add a reference for Elf_Chdr type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274793
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Alina Sbirlea [Thu, 7 Jul 2016 20:10:35 +0000 (20:10 +0000)]
Clang-format LoadStoreVectorizer
Reviewers: llvm-commits, jlebar, arsenm
Subscribers: mzolotukhin
Differential Revision: http://reviews.llvm.org/D22107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274792
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Chad Rosier [Thu, 7 Jul 2016 20:02:18 +0000 (20:02 +0000)]
[AArch64] Change the preferred alignment for char and short to word alignment.
The commit reinstates r273279, which was informally approved.
Original Review: http://reviews.llvm.org/D21414
This reverts commit
ca632c91aaa7cafc50942f890c49f727a046ace1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274790
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Tim Northover [Thu, 7 Jul 2016 19:45:45 +0000 (19:45 +0000)]
GlobalISel: remove redundant property setting. NFC.
AsmString is empty by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274789
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Andrew Kaylor [Thu, 7 Jul 2016 18:55:02 +0000 (18:55 +0000)]
Include SelectionDAGISel in the opt-bisect process
Differential Revision: http://reviews.llvm.org/D21143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274786
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Peter Collingbourne [Thu, 7 Jul 2016 18:31:51 +0000 (18:31 +0000)]
ThinLTO: Do not take into account whether a definition has multiple copies when promoting.
We currently do not touch a symbol's linkage in the case where a definition
has a single copy. However, this code is effectively unnecessary: either
the definition is not exported, in which case the internalize phase sets
its linkage to internal, or it is exported, in which case we need to promote
linkage to weak. Those two cases are already handled by existing code.
I believe that the only real functional change here is in the case where we
have a single definition which does not prevail (e.g. because the definition
in a native object file prevails). In that case we now lower linkage to
available_externally following the existing code path for that case.
As a result we can remove the isExported function parameter from the
thinLTOResolveWeakForLinkerInIndex function.
Differential Revision: http://reviews.llvm.org/D21883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274784
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Justin Lebar [Thu, 7 Jul 2016 18:14:55 +0000 (18:14 +0000)]
[NVVM] Rename __nvvm_bar0 builtin back to __syncthreads.
__syncthreads was renamed to __nvvm_bar0 in r274664. But __syncthreads
is part of our user-facing API, so we need to keep the name.
This will momentarily break clang; we need a matching patch there.
Patch by Justin Bogner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274779
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Dan Liew [Thu, 7 Jul 2016 18:14:11 +0000 (18:14 +0000)]
[LibFuzzer] Unbreak the build on macOS which was broken by r272858.
``afl_driver.cpp`` currently relies on weak symbols which doesn't
work properly under macOS. For now fix the build by providing a
dummy implementation of ``LLVMFuzzerInitialize(...)``. This is just
a temporary measure until we fix ``afl_driver.cpp`` for macOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274778
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Tim Northover [Thu, 7 Jul 2016 17:51:42 +0000 (17:51 +0000)]
tests: accept different TargetOpcode values.
These tests don't actually care about the internal opcode number, but have to
be updated whenever we add a new one for GlobalISel. That's bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274774
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Davide Italiano [Thu, 7 Jul 2016 17:44:38 +0000 (17:44 +0000)]
[LoopStrengthReduce] Fix -Wmisleading-indentation. Reported by GCC6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274773
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Michael Kuperstein [Thu, 7 Jul 2016 16:55:35 +0000 (16:55 +0000)]
Revert r274692 to check whether this is what breaks windows selfhost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274771
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Justin Bogner [Thu, 7 Jul 2016 16:40:17 +0000 (16:40 +0000)]
NVPTX: Remove the legacy ptx intrinsics
- Rename the ptx.read.* intrinsics to nvvm.read.ptx.sreg.* - some but
not all of these registers were already accessible via the nvvm
name.
- Rename ptx.bar.sync nvvm.bar.sync, to match nvvm.bar0.
There's a fair amount of code motion here, but it's all very
mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274769
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Chad Rosier [Thu, 7 Jul 2016 16:37:29 +0000 (16:37 +0000)]
Revert "[AArch64] Change the preferred alignment for char and short to word alignment"
This reverts commit r273279 as the change was not properly approved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274768
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Sanjay Patel [Thu, 7 Jul 2016 16:19:09 +0000 (16:19 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274765
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Zhan Jun Liau [Thu, 7 Jul 2016 15:34:46 +0000 (15:34 +0000)]
[SystemZ] Fix regression when handling conditional calls
Summary:
A regression showed up in node.js when handling conditional calls.
Fix the regression by recognizing external symbols as a possible
operand type in CallJG.
Reviewers: koriakin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D22054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274761
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Sanjay Patel [Thu, 7 Jul 2016 15:28:17 +0000 (15:28 +0000)]
save type in local var; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274760
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Sjoerd Meijer [Thu, 7 Jul 2016 14:31:19 +0000 (14:31 +0000)]
Addressing post-commit comments for not rewriting fputs:
moved the optimise for size check inside function optimizeFPuts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274758
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Valery Pykhtin [Thu, 7 Jul 2016 14:23:38 +0000 (14:23 +0000)]
[AMDGPU] fix ds_write_src2 encoding (bz26027)
Differential revision: http://reviews.llvm.org/D22041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274756
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Rafael Espindola [Thu, 7 Jul 2016 14:00:07 +0000 (14:00 +0000)]
Don't crash trying to relax 32 loads on COFF.
Fixes pr28452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274754
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Sjoerd Meijer [Thu, 7 Jul 2016 13:56:23 +0000 (13:56 +0000)]
Code size optimisation: don't rewrite fputs to fwrite when optimising for size
because fwrite requires more arguments and thus extra MOVs are required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274753
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Diana Picus [Thu, 7 Jul 2016 09:11:39 +0000 (09:11 +0000)]
[ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 1 flag
This is a follow-up for r273544.
The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.
This commit also removes a command line flag that isn't used in any of the tests:
check-vmlx-hazards. It can be replaced easily with the mattr mechanism, since
this is now a subtarget feature.
There is still some work left regarding FeatureExpandMLx. In the past MLx
expansion was enabled for subtargets with hasVFP2(), until r129775 [1] switched
from that to isCortexA9, without too much justification.
In spite of that, the code performing MLx expansion still contains calls to
isSwift/isLikeA9, although the results of those are pretty clear given that
we're only enabling it for the A9.
We should try to enable it for all targets that have FeatureHasVMLxHazards, as
it seems to be closely related to that behaviour, and if that is possible try to
clean up the MLx expansion pass from all calls to isWhatever. This will require
some performance testing, so it will be done in another patch.
[1] http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20110418/119725.html
Differential Revision: http://reviews.llvm.org/D21798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274742
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Chandler Carruth [Thu, 7 Jul 2016 07:52:07 +0000 (07:52 +0000)]
[LCG] Hoist the definitions of the stream operator friends to be inline
friend definitions.
Based on the experiments Sean Silva and Reid did, this seems the safest
course of action and also will work around a questionable warning
provided by GCC6 on the old form of the code. Thanks for Davide pointing
out the issue and other suggesting ways to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274740
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David Majnemer [Thu, 7 Jul 2016 06:24:36 +0000 (06:24 +0000)]
[LoopAccessAnalysis] Fix an integer overflow
We were inappropriately using 32-bit types to account for quantities
that can be far larger.
Fixed in PR28443.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274737
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Craig Topper [Thu, 7 Jul 2016 06:11:07 +0000 (06:11 +0000)]
[AVX512] Zero extend the result of vpcmpeq/vpcmpgt and similar intrinsics in the autoupgrade code. This currently results in worse codegen but is needed for correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274736
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Elena Demikhovsky [Thu, 7 Jul 2016 06:06:46 +0000 (06:06 +0000)]
Fixed a bug in vectorizing GEP before gather/scatter intrinsic.
Vectorizing GEP was incorrect and broke SSA in some cases.
The patch fixes PR27997 https://llvm.org/bugs/show_bug.cgi?id=27997.
Differential revision: http://reviews.llvm.org/D22035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274735
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