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Emil Velikov [Fri, 21 Jun 2019 16:26:44 +0000 (17:26 +0100)]
ac: change ac_query_gpu_info() signature
Currently libdrm_amdgpu provides a typedef of the various handles. While
the goal was to make those opaque, it effectively became part of the API
To the best of my knowledge there are two ways to have opaque handles:
- "typedef void *foo;" - rather messy IMHO
- "stuct foo;" and use "struct foo *" through the API
In our case amdgpu_device_handle is used only internally, plus
respective code is not used or applicable for r300 and r600. Hence we
copied the typedef.
Seemingly this will be a problem since libdrm_amdgpu wants to change the
API, while not updating the code(?).
Either way, we can safely s/amdgpU_device_handle/void */ and carry on.
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tomeu Vizoso [Fri, 28 Jun 2019 07:17:55 +0000 (09:17 +0200)]
panfrost: Only tag AFBC addresses when sampling
Rendering to AFBC was broken, as the HW will complaint loudly if we pass
a tagged pointer in bifrost_render_target.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes:
3609b50a6443 ("panfrost: Merge AFBC slab with BO backing")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Jose Fonseca [Fri, 31 May 2019 16:10:40 +0000 (17:10 +0100)]
gallivm: Improve lp_build_rcp_refine.
Use the alternative more accurate expression from
https://en.wikipedia.org/wiki/Division_algorithm#Newton%E2%80%93Raphson_division
v2: Use lp_build_fmuladd as suggested by Roland
Tested by enabling this code path, and running lp_test_arit.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tomeu Vizoso [Fri, 28 Jun 2019 06:10:29 +0000 (08:10 +0200)]
panfrost/ci: Don't error out on RK3288
At the moment we don't have enough people to ensure that RK3288 is
regression-free, so don't fail the CI in that case.
For now we'll focus on not regressing on RK3399 and we can expand to
other SoCs as more people join the effort.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Suggested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Wed, 26 Jun 2019 11:36:30 +0000 (13:36 +0200)]
panfrost/ci: Don't print every kernel file
As there's lots of them and Gitlab struggles rendering logs with so many
lines.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Wed, 26 Jun 2019 10:50:52 +0000 (12:50 +0200)]
panfrost/ci: Fix the image name
These changes will make sure we get the right image from the container
registry.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Wed, 26 Jun 2019 06:02:31 +0000 (08:02 +0200)]
panfrost/ci: Remove batching
Panfrost has grown and doesn't leak as much as before.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Kenneth Graunke [Fri, 28 Jun 2019 00:16:20 +0000 (17:16 -0700)]
iris: Don't leak resources in iris_create_surface for incomplete FBOs
We were failing to pipe_resource_unreference on the failure path due
to a non-renderable format. Instead of fixing this, just move the
checks earlier, before we even bother with refcounting or calloc.
Samuel Pitoiset [Thu, 27 Jun 2019 17:29:13 +0000 (19:29 +0200)]
radv: only enable VK_AMD_gpu_shader_{half_float,int16} on GFX9+
These two extensions are supported on GFX8 but the throughput
of 16-bit floats/integers is same as 32-bit. Also, shaderInt16
is only enabled on GFX9+ for the same reason, be more consistent.
This fixes a crash with Wolfenstein II because it expects
shaderInt16 to be enabled when VK_AMD_gpu_shader_half_float is
exposed. Note that AMDVLK only enables these extensions on GFX9+.
Cc: 19.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 26 Jun 2019 07:23:31 +0000 (09:23 +0200)]
radv: add si_emit_ia_multi_vgt_param() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alexandros Frantzis [Thu, 27 Jun 2019 07:48:50 +0000 (10:48 +0300)]
virgl: Don't allow creating staging pipe_resources
Staging buffers are now created directly by the virgl_staging_mgr. We
don't need to support creating staging pipe_resources.
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Alexandros Frantzis [Mon, 24 Jun 2019 13:57:46 +0000 (16:57 +0300)]
virgl: Use virgl_staging_mgr
Use an instance of virgl_staging_mgr instead of u_upload_mgr to handle
the staging buffer. This removes the need to track the availability
of the staging manager, since virgl_staging_mgr can handle concurrent
active allocations.
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Alexandros Frantzis [Tue, 25 Jun 2019 10:56:52 +0000 (13:56 +0300)]
virgl: Add tests for virgl_staging_mgr
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Alexandros Frantzis [Mon, 24 Jun 2019 13:30:07 +0000 (16:30 +0300)]
virgl: Introduce virgl_staging_mgr
Add a manager for the staging buffer used in virgl. The staging manager
is heavily inspired by u_upload_mgr, but is simpler and is a better fit
for virgl's purposes. In particular, the staging manager:
* Allows concurrent staging allocations.
* Calls the virgl winsys directly to create and map resources, avoiding
unnecessarily going through gallium resources and transfers.
olv: make virgl_staging_alloc_buffer return a bool
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Alexandros Frantzis [Wed, 26 Jun 2019 09:12:17 +0000 (12:12 +0300)]
virgl: Store the virgl_hw_res for copy transfers
Store the virgl_hw_res instead of the pipe_resource for copy transfer
sources. This prepares the codebase for a change to provide only the
virgl_hw_res for the staging buffers in upcoming commits.
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Kenneth Graunke [Thu, 27 Jun 2019 23:54:47 +0000 (16:54 -0700)]
iris: Fix major resource leak in iris_set_shader_images
We were failing to unreference the old image resource. Instead of open
coding this and doing it badly, just use the copier function which does
the right thing.
Kenneth Graunke [Thu, 27 Jun 2019 23:50:00 +0000 (16:50 -0700)]
gallium: Make util_copy_image_view handle shader_access
A while back, we added a new field, but failed to update the copier.
I believe iris is the only current user of the new field, and it hasn't
used the copier, so noone noticed.
Fixes:
8b626a22b24 st/mesa: Record shader access qualifiers for images
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Thu, 27 Jun 2019 21:35:13 +0000 (14:35 -0700)]
gallium: Teach GALLIUM_REFCNT_LOG about array textures
Otherwise they are classified as pipe_martian_resource, and don't
contain any helpful information about the texture.
Reviewed-by: Eric Anholt <eric@anholt.net>
Nanley Chery [Mon, 20 May 2019 21:50:23 +0000 (14:50 -0700)]
isl: Don't align phys_level0_sa by block dimension
Aligning phys_level0_sa by the compression block dimension prior to
mipmap layout causes the layout of compressed surfaces to differ from
the sampler's expectations in certain cases. The hardware docs agree:
From the BDW PRM, Vol. 5, Compressed Mipmap Layout,
The compressed mipmaps are stored in a similar fashion to
uncompressed mipmaps [...]
The following exceptions apply to the layout of compressed (vs.
uncompressed) mipmaps:
* [...]
* The dimensions of the mip maps are first determined by applying
the sizing algorithm presented in Non-Power-of-Two Mipmaps
above. Then, if necessary, they are padded out to compression
block boundaries.
The last bullet indicates that alignment should not be done for
calculating a miplevel's dimensions, but rather for determining miplevel
placement/padding. Comply with this text by removing the extra
alignment.
Fixes some fbo-generatemipmap-formats piglit failures on all tested
platforms (SNB-KBL).
v2:
- Note fixed platforms.
- Update some consumers via a helper function.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nanley Chery [Thu, 23 May 2019 20:44:52 +0000 (13:44 -0700)]
intel: Add and use helpers for level0 extent
Prepare for a bug fix by adding and using helpers which convert
isl_surf::logical_level0_px and isl_surf::phys_level0_sa to units of
surface elements.
v2:
- Update iris (Ken).
- Update anv.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dylan Baker [Wed, 22 May 2019 22:49:01 +0000 (15:49 -0700)]
meson: try to use cmake as a finder for clang
Clang (like LLVM), very annoyingly refuses to provide pkg-config, and
only provides cmake (unlike LLVM which at least provides llvm-config,
even if llvm-config is terrible). Meson has gained the ability to use
cmake to find dependencies, and can successfully find Clang. This change
attempts to use cmake to find clang instead of a bunch of library
searches, when paired with -Dcmake_prefix_path we can much more reliably
use cmake to control which clang we're getting. This is only enabled for
meson >= 0.51, which adds the required options.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 22 May 2019 18:01:17 +0000 (11:01 -0700)]
meson: Add support for using cmake for finding LLVM
Meson has support for using cmake as a finder for some dependencies,
including LLVM. Using cmake has a lot of advantages: it needs less meson
maintenance to keep working (even for llvm updates); it works more
sanely for cross compiles (as llvm-config is a compiled binary not a
shell script). Meson 0.51.0 also has a new generic variable getter that
can be used to get information from either cmake, pkg-config, or
config-tools dependencies, which is needed for cmake. We continue to
support using llvm-config if you don't have cmake installed, or if cmake
cannot find a suitable version.
Fixes:
0d59459432cf077d768164091318af8fb1612500
("meson: Force the use of config-tool for llvm")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Thu, 27 Jun 2019 21:09:05 +0000 (14:09 -0700)]
iris: Fix memory leak of SO targets
We need to pitch these on context destroy.
Kenneth Graunke [Thu, 27 Jun 2019 18:49:41 +0000 (11:49 -0700)]
iris: Fix memory leak for draw parameter resources
Need to pitch these on context destroy.
Kenneth Graunke [Thu, 27 Jun 2019 18:15:10 +0000 (11:15 -0700)]
iris: Drop u_upload_unmap
We use persistent maps so this does nothing.
Lionel Landwerlin [Tue, 25 Jun 2019 08:10:14 +0000 (11:10 +0300)]
intel/compiler: fix derivative on y axis implementation
This rewrites the ddy in EXECUTE_4 mode with a loop to make it more
obvious what is going on and also sets the group each of the 4 threads
in the groups are supposed to execute.
Fixes the following CTS tests :
dEQP-VK.glsl.derivate.dfdyfine.dynamic_*
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Co-Authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes:
2134ea380033d5 ("intel/compiler/fs: Implement ddy without using align16 for Gen11+")
Eric Engestrom [Wed, 22 May 2019 15:37:10 +0000 (16:37 +0100)]
meson: set up a proper internal dependency for xmlconfig
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Wed, 22 May 2019 14:32:27 +0000 (15:32 +0100)]
xmlconfig: add missing #include
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Wed, 22 May 2019 11:52:44 +0000 (12:52 +0100)]
xmlpool: fix typo in comment
s/otions/options/, and while here let's give the full path to xmlpool.h
since `../` won't be true in the generated file.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Kenneth Graunke [Thu, 27 Jun 2019 06:56:45 +0000 (23:56 -0700)]
iris: Also properly restore INTERFACE_DESCRIPTOR_DATA buffer object
We were at least cleaning up this reference, but we were failing to
pin it in iris_restore_compute_saved_bos.
Kenneth Graunke [Thu, 27 Jun 2019 06:38:59 +0000 (23:38 -0700)]
iris: Fix resource tracking for CS thread ID buffer
Today, we stream the compute shader thread IDs simply because they're
(annoyingly) relative to dynamic state base address. We could upload
them once at compile time, but we'd need a separate non-streaming
uploader for IRIS_MEMZONE_DYNAMIC, and I'm not sure it's worth it.
stream_state pins the buffer for use in the current batch, but also
returns a reference to the pipe_resource. We dropped this reference
on the floor, leaking a reference basically every time we dispatched
a compute shader after switching to a new one.
The reason it returns a reference is so that we can hold on to it and
re-pin it in iris_restore_compute_saved_bos, which we were also failing
to do. So if we actually filled up a batch with repeated dispatches to
the same compute shader, and flushed, then continued dispatching, we
would fail to pin it and likely GPU hang.
Kenneth Graunke [Thu, 27 Jun 2019 06:33:40 +0000 (23:33 -0700)]
iris: Only bother with thread ID upload if doing MEDIA_CURBE_LOAD
We were unconditionally uploading the new data, but then conditionally
using it with MEDIA_CURBE_LOAD. If we're not going to emit the command,
there's no point in uploading the data.
Kenneth Graunke [Thu, 27 Jun 2019 00:14:58 +0000 (17:14 -0700)]
iris: Do MEDIA_CURBE_LOAD when IRIS_DIRTY_CS is set, not constants
We only use push the compute shader thread IDs, not any actual constant
buffer data. So we should track the compute shader variant changing,
not constbuf changes.
Kenneth Graunke [Thu, 27 Jun 2019 06:24:56 +0000 (23:24 -0700)]
iris: Drop UBO range stuff from iris_restore_compute_saved_bos
Compute doesn't use UBO ranges (annoyingly), so this is dead code.
Kenneth Graunke [Thu, 27 Jun 2019 00:35:45 +0000 (17:35 -0700)]
iris: Properly align interface descriptor data addresses
MEDIA_INTERFACE_DESCRIPTOR's Interface Descriptor Data Start Address
field's docs say: "This bit specifies the 64-byte aligned address..."
And we were doing 32. Superfluous thread ID uploading was apparently
saving us from GPU hangs in most cases.
Andrii Simiklit [Tue, 25 Jun 2019 14:42:43 +0000 (17:42 +0300)]
mesa: use a correct function return type
v2: standard 'bool' can be used
( Eric Engestrom <eric.engestrom@intel.com> )
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Tomeu Vizoso [Tue, 25 Jun 2019 07:20:51 +0000 (09:20 +0200)]
panfrost/decode: Mention the address of a few descriptors
When the fault_pointer field in the header is set, we can get some idea
of which descriptor the HW isn't happy with if we know their addresses.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Tue, 25 Jun 2019 06:41:06 +0000 (08:41 +0200)]
panfrost/decode: Wait for a job to finish before dumping
Then we can get some information back about any exception that might
have happened.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Tue, 25 Jun 2019 06:22:30 +0000 (08:22 +0200)]
panfrost/decode: Decode exception status
Arm's kernel driver mentions how to decode this field, which makes a bit
clearer what had happened.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tomeu Vizoso [Tue, 25 Jun 2019 06:21:15 +0000 (08:21 +0200)]
panfrost/decode: Print AFBC struct when appropriate
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Samuel Pitoiset [Wed, 26 Jun 2019 14:35:44 +0000 (16:35 +0200)]
radv: only export clip/cull distances if PS reads them
The only exception is the GS copy shader which emits them
unconditionally.
Totals from affected shaders:
SGPRS: 71320 -> 71008 (-0.44 %)
VGPRS: 54372 -> 54240 (-0.24 %)
Code Size:
2952628 ->
2941368 (-0.38 %) bytes
Max Waves: 9689 -> 9723 (0.35 %)
This helps Dota2, Doom, GTAV and Hitman 2.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 26 Jun 2019 14:24:10 +0000 (16:24 +0200)]
radv: fix FMASK expand if layerCount is VK_REMAINING_ARRAY_LAYERS
This doesn't fix anything known, but it's likely going to
break if layerCount is ~0U.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 26 Jun 2019 02:34:45 +0000 (19:34 -0700)]
iris: Disable loop unrolling in GLSL IR.
Leave it to NIR instead, like i965 does. Thanks to Tim Arceri for
noticing that I'd left this enabled by accident.
shader-db results on Skylake:
total instructions in shared programs:
15522628 ->
15521642 (<.01%)
instructions in affected programs: 94008 -> 93022 (-1.05%)
helped: 34
HURT: 33
helped stats (abs) min: 12 max: 48 x̄: 33.82 x̃: 42
helped stats (rel) min: 0.06% max: 22.14% x̄: 9.86% x̃: 10.89%
HURT stats (abs) min: 1 max: 16 x̄: 4.97 x̃: 3t
HURT stats (rel) min: 0.82% max: 3.77% x̄: 1.73% x̃: 1.53%
95% mean confidence interval for instructions value: -20.08 -9.35
95% mean confidence interval for instructions %-change: -5.95% -2.36%
Instructions are helped.
total cycles in shared programs:
367105221 ->
367074230 (<.01%)
cycles in affected programs:
10017660 ->
9986669 (-0.31%)
helped: 266
HURT: 184
helped stats (abs) min: 1 max: 9556 x̄: 151.35 x̃: 12
helped stats (rel) min: 0.08% max: 59.91% x̄: 4.66% x̃: 1.67%
HURT stats (abs) min: 1 max: 1716 x̄: 50.37 x̃: 6
HURT stats (rel) min: <.01% max: 24.40% x̄: 2.42% x̃: 0.85%
95% mean confidence interval for cycles value: -133.90 -3.84
95% mean confidence interval for cycles %-change: -2.44% -1.10%
Cycles are helped.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Wed, 26 Jun 2019 04:00:46 +0000 (21:00 -0700)]
st/mesa: Set EmitNoIndirectSampler if GLSLVersion < 400.
This patch changes the code which sets EmitNoIndirectSampler to check
the core profile GLSL version, rather than the ARB_gpu_shader5 extension
enable. st/mesa exposes ARB_gpu_shader5 if GLSLVersion (in core
profiles) or GLSLVersionCompat (in compat profiles) >= 400.
The Intel drivers do not currently expose ARB_gpu_shader5 in compat
profiles. But the backend can absolutely handle indirect samplers.
Looking at the core profile version number should be a good indication
of what the driver supports.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Thu, 27 Jun 2019 03:16:10 +0000 (20:16 -0700)]
iris: Delete dead ice->state.streamout_strides field.
Nothing uses this, it must be a remnant from an earlier approach.
Caio Marcelo de Oliveira Filho [Wed, 12 Jun 2019 23:48:21 +0000 (16:48 -0700)]
nir/algebraic: Add helpers and a rule involving wrapping
The helpers are needed so we can use the syntax `instr(cond)` in the
algebraic rules. Add simple rule for dropping a pair of mul-div of
the same value when wrapping is guaranteed to not happen.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Sat, 18 May 2019 05:52:42 +0000 (22:52 -0700)]
spirv: Implement NoSignedWrap and NoUnsignedWrap decorations
When handling the specified ALU operations, check for the decorations
and set nir_alu_instr no_signed_wrap and no_unsigned_wrap flags accordingly.
v2: Add a glsl_base_type_is_unsigned_integer() helper. (Karol)
v3: Rename helper to glsl_base_type_is_uint().
v4: Use two flags, so we don't need the helper anymore. (Connor)
v5: Pass alu directly to handle function. (Jason)
Reviewed-by: Karol Herbst <kherbst@redhat.com> [v3]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Fri, 17 May 2019 20:46:38 +0000 (13:46 -0700)]
nir: Add a no wrapping bits to nir_alu_instr
They indicate the operation does not cause overflow or underflow.
This is motivated by SPIR-V decorations NoSignedWrap and
NoUnsignedWrap.
Change the storage of `exact` to be a single bit, so they pack
together.
v2: Handle no_wrap in nir_instr_set. (Karol)
v3: Use two separate flags, since the NIR SSA values and certain
instructions are typeless, so just no_wrap would be insufficient
to know which one was referred to. (Connor)
v4: Don't use nir_instr_set to propagate the flags, unlike `exact`,
consider the instructions different if the flags have different
values. Fix hashing/comparing. (Jason)
Reviewed-by: Karol Herbst <kherbst@redhat.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dylan Baker [Wed, 26 Jun 2019 20:48:06 +0000 (13:48 -0700)]
docs: add news item and link release notes for 19.0.8
This is an emergency release due to a critical bug.
Dylan Baker [Wed, 26 Jun 2019 20:42:45 +0000 (13:42 -0700)]
docs: Add mesa 19.0.8 sha256 sums
Dylan Baker [Wed, 26 Jun 2019 20:08:54 +0000 (13:08 -0700)]
docs: Add docs for 19.0.8
Jonathan Marek [Fri, 21 Jun 2019 03:22:02 +0000 (23:22 -0400)]
nir: remove fnot/fxor/fand/for opcodes
There doesn't seem to be any reason to keep these opcodes around:
* fnot/fxor are not used at all.
* fand/for are only used in lower_alu_to_scalar, but easily replaced
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jonathan Marek [Fri, 21 Jun 2019 03:05:13 +0000 (23:05 -0400)]
nir: opt_vectorize: combine different constant sources
We can vectorize instructions with different constant sources by creating
a new load_const and using that.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 22:11:57 +0000 (15:11 -0700)]
panfrost/midgard: Merge embedded constants
In Midgard, a bundle consists of a few ALU instructions. Within the
bundle, there is room for an optional 128-bit constant; this constant is
shared across all instructions in the bundle.
Unfortunately, many instructions want a 128-bit constant all to
themselves (how selfish!). If we run out of space for constants in a
bundle, the bundle has to be broken up, incurring a performance and
space penalty.
As an optimization, the scheduler now analyzes the constants coming in
per-instruction and attempts to merge shared components, adjusting the
swizzle accessing the bundle's constants appropriately. Concretely,
given the GLSL:
(a * vec4(1.5, 0.5, 0.5, 1.0)) + vec4(1.0, 2.3, 2.3, 0.5)
instead of compiling to the naive two bundles:
vmul.fmul [temp], [a], r26
fconstants 1.5, 0.5, 0.5, 1.0
vadd.fadd [out], [temp], r26
fconstants 1.0, 2.3, 2.3, 0.5
The scheduler can now fuse into a single (pipelined!) bundle:
vmul.fmul [temp], [a], r26.xyyz
vadd.fadd [out], [temp], r26.zwwy
fconstants 1.5, 0.5, 1.0, 2.3
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 22:02:44 +0000 (15:02 -0700)]
panfrost/midgard: Share swizzle compose
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 22:02:19 +0000 (15:02 -0700)]
panfrost/midgard: Share swizzle/mask code
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 26 Jun 2019 16:55:15 +0000 (09:55 -0700)]
panfrost: Fix checksumming typo
Fixes:
3e6c6bb0 ("panfrost: Merge checksum buffer with main BO")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Kenneth Graunke [Wed, 26 Jun 2019 04:14:11 +0000 (21:14 -0700)]
iris: Fix overzealous query object batch flushing.
In the past, each query object had their own BO. Checking if the batch
referenced that BO was an easy way to check if commands were still
queued to compute the query value. If so, we needed to flush.
More recently (
c24a574e6c), we started using an u_upload_mgr for query
objects, placing multiple queries in the same BO. One side-effect is
that iris_batch_references is a no longer a reasonable way to check if
commands are still queued for our query. Ours might be done, but a
later query that happens to be in the same BO might be queued. We don't
want to flush in that case.
Instead, check if the current batch's signalling syncpt is the one we
referenced when ending the query. We know the syncpt can't have been
reused because our query is holding a reference, so a simple pointer
comparison should suffice.
Removes all batch flushing caused by query objects in Shadow of Mordor.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Kenneth Graunke [Wed, 26 Jun 2019 04:11:52 +0000 (21:11 -0700)]
iris: Make an iris_batch_get_signal_syncpt() helper.
This returns a pointer to the signalling syncpt, without incrementing
the reference count. This can be useful for comparisons.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Boris Brezillon [Wed, 26 Jun 2019 09:16:31 +0000 (11:16 +0200)]
panfrost: Remove unneeded check in panfrost_scissor_culls_everything()
The ss local var is guaranteed to be != NULL. Get rid of this useless
check.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 20:30:17 +0000 (13:30 -0700)]
panfrost: Update copyright identifiers
"Collabora, Ltd." should be listed in lieu of simply "Collabora"
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:02:35 +0000 (09:02 -0700)]
panfrost/midgard: Reorder to permit constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:02:20 +0000 (09:02 -0700)]
panfrost/midgard: Add helper to encode constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:06:25 +0000 (09:06 -0700)]
panfrost/midgard: Handle negative immediate bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Rob Clark [Wed, 26 Jun 2019 15:25:55 +0000 (08:25 -0700)]
freedreno: correct batch_depends_on() logic
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Tue, 25 Jun 2019 18:21:28 +0000 (11:21 -0700)]
freedreno: drop unused arg from fd_batch_flush()
The `force` arg has been unused for a while.. but apparently I forgot to
garbage collect it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Timothy Arceri [Wed, 26 Jun 2019 13:02:12 +0000 (23:02 +1000)]
st/glsl: fix silly regression finding gs/tes variants
Fixes:
d19fe5e67a39 ("st/glsl: support clamping color outputs in compat for gs/tes")
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Tue, 25 Jun 2019 10:53:15 +0000 (20:53 +1000)]
st/glsl: support clamping color outputs in compat for gs/tes
This support requires the driver to be a NIR driver as we use the
NIR lowering pass to do the clamping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 25 Jun 2019 06:33:22 +0000 (16:33 +1000)]
nir: add tess support to nir_lower_clamp_color_outputs()
This will be used to add compat profile support for higher GL
versions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Sagar Ghuge [Mon, 24 Jun 2019 22:10:53 +0000 (15:10 -0700)]
glsl: Fix round64 conversion function
Fix round64 function to handle round to nearest even cases specially
with positive and negative numbers with fraction part 0.5.
v2: 1) Simplify unused bits (Elie Tournier)
Fixes:
KHR-GL45.gpu_shader_fp64.builtin.round_dvec2
KHR-GL45.gpu_shader_fp64.builtin.round_dvec3
KHR-GL45.gpu_shader_fp64.builtin.round_dvec4
KHR-GL45.gpu_shader_fp64.builtin.roundeven_double
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 20:42:58 +0000 (13:42 -0700)]
panfrost/ci: Add RK3288 flipflops I don't want to deal with right now
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 17:16:33 +0000 (10:16 -0700)]
panfrost/ci: Update failures list
A ton of tests were fixed by this series. A few were incorrectly passing
before (QualityError, for instance) and now are explicitly failing. A
few legitimate regressions but overwhelmingly positive.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 20:17:28 +0000 (13:17 -0700)]
panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0
Fixes cube map tests due to disagreements between Mesa, dEQP, and the
spec...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 22:06:47 +0000 (15:06 -0700)]
panfrost/ci: Run full set of mipmap tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 14:01:52 +0000 (07:01 -0700)]
panfrost: Advertise support for other 8-bit UNORM formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 15:57:55 +0000 (08:57 -0700)]
panfrost: Use pipe_surface->format directly in blitter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 15:51:48 +0000 (08:51 -0700)]
panfrost: Invert swizzle for rendering
Fixes rendering to e.g. alpha textures.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:53:54 +0000 (14:53 -0700)]
panfrost: Honour first_layer...last_layer when sampling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:39:37 +0000 (14:39 -0700)]
panfrost: Use the sampler_view target (not the textures)
u_blitter gets "special treatment" and uses this mechanism to cast
cube maps to 2D textures in order to texelFetch them.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:39:25 +0000 (14:39 -0700)]
panfrost/midgard: Assert guard texelFetch against cubemaps
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:13:20 +0000 (14:13 -0700)]
panfrost: Zero pixels in any axis is zero pixels total
Multiplication, not addition, so switch the logic operator.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 20:53:44 +0000 (13:53 -0700)]
panfrost: Respect mip level when wallpapering
Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a
mipmap.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 17:35:03 +0000 (10:35 -0700)]
panfrost/midgard: Fixup NIR texture op
In a vertex shader, a tex op should map to txl, as there *must* be a LOD
given to the hardware (implicitly or explicitly).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 16:16:11 +0000 (09:16 -0700)]
panfrost: Support (non-)seamless cube maps
Identify the seamless cubemap bit and passthrough the Gallium state
rather than setting unconditionally.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 14:08:52 +0000 (07:08 -0700)]
panfrost: Merge checksum buffer with main BO
This is similar to the AFBC merge; now all (non-imported) buffers use a
common backing buffer. Reenables checksumming, eliminating a performance
regression.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:29:46 +0000 (11:29 -0700)]
panfrost/decode: Limit MRT blend count
I thought I already fixed this. Maybe that was a dream...? Then again, I
might be dreaming now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:20:00 +0000 (11:20 -0700)]
panfrost: Clamp tile coordinates before job submission
Fixes TILE_RANGE_FAULT raised on some tests in
dEQP-GLES3.functional.fbo.blit.*
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:05:10 +0000 (11:05 -0700)]
panfrost: Use dedicated u_blitter context for wallpapers
The main ctx->blitter instance should be reserved for blits originated
from Gallium (like mipmap generation). Since wallpapering is
conceptually different -- wallpaper blits can be triggered by Gallium
blits -- the blitter pipes must be separate to avoid potential u_blitter
recursion.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:39:02 +0000 (17:39 -0700)]
panfrost: Sanity check layer
It doesn't make sense to try to render to multiple array elements at
once.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:27:05 +0000 (17:27 -0700)]
panfrost: Divide array_size by 6 for cubemaps
Addresses the disparity between Mali and Gallium definitions of
array_size.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:23:49 +0000 (17:23 -0700)]
panfrost: Use get_texture_address for framebuffer computations
Allows for sharing some code as well as theoretically allowing cubemap
rendering.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:54:44 +0000 (14:54 -0700)]
panfrost: Merge AFBC slab with BO backing
Rather than tracking AFBC memory "specially", just use the same codepath
as linear and tiled. Less things to mess up, I figure. This allows us to
use the standard setup_slices() call with AFBC resources, allowing
mipmapped AFBC resources.
Unfortunately, we do have to disable AFBC (and checksumming) in the
meantime to avoid functional regressions, as we don't know _a priori_ if
we'll need to access a resource from software (which is not yet hooked
up with AFBC) and we don't yet have routines to switch the layout of a
BO at runtime.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:41:14 +0000 (14:41 -0700)]
panfrost: Z/S can't be tiled
As far as we know, Utgard-style tiling only works for color render
targets, not depth/stencil, so ensure we don't try to tile it (rather
than compress or plain old linear) and drive ourselves into a corner.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:26:19 +0000 (14:26 -0700)]
panfrost: Enable mipmapping
Now the autogeneration of mipmaps is working (via u_blitter), we can
finally enable mipmaps!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:25:59 +0000 (14:25 -0700)]
panfrost: Enable blitting
Now that all the prerequisites breaking u_blitter are fixed, we can
finally hook up panfrost_blit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:49:49 +0000 (11:49 -0700)]
panfrost: Allow texelFetch for wallpaper blits
We just implemented the routine; we may as well use it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 23:17:34 +0000 (16:17 -0700)]
panfrost/midgard: Implement texelFetch (2D only)
txf instructions can result from blits, so handle them rather than
crash. Only works for 2D textures (not even 2D array texture) due to a
register allocation constraint that may not be sorted for a while.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 20:59:51 +0000 (13:59 -0700)]
panfrost: Skip flushes only for wallpapers, not any blit
We need the flush from u_blitter for a normal blit (e.g. for mipmaps);
it's only wallpaper-related blits that are special-cased.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 20:57:42 +0000 (13:57 -0700)]
panfrost: Handle generate_mipmap ourselves
To avoid interference with the wallpaper code, we need to do some state
tracking when generating mipmaps. In particular, we need to mark the
generated layers as invalid before generating the mipmap, so we don't
try to backblit them if they already had content.
Likewise, we need to flush both before and after generating a mipmap
since our usual set_framebuffer_state flushing isn't quite there yet.
Ideally better optimizations would save the flush but I digress.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 23:58:48 +0000 (16:58 -0700)]
panfrost: Disable mipmapping if necessary
If a mipfilter is not set, it's legal to have an incomplete mipmap; we
should handle this accordingly. An "easy way out" is to rig the LOD
clamps.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>