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Jason Ekstrand [Wed, 30 Mar 2016 22:03:34 +0000 (15:03 -0700)]
anv/blit2d: Refactor in preparation for different src/dst types
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 30 Mar 2016 20:54:56 +0000 (13:54 -0700)]
anv/blit2d: Add layouts for using a texel buffer source
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 30 Mar 2016 20:51:21 +0000 (13:51 -0700)]
anv/blit2d: Rename the descriptor set and pipeline layouts
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 30 Mar 2016 20:47:41 +0000 (13:47 -0700)]
anv/blit2d: Enhance teardown and clean up init error paths
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 30 Mar 2016 20:32:08 +0000 (13:32 -0700)]
anv/blit2d: Factor binding the source image into a helper
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 30 Mar 2016 18:51:50 +0000 (11:51 -0700)]
anv/blit2d: Inline meta_emit_blit2d
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 29 Mar 2016 21:24:31 +0000 (14:24 -0700)]
anv/blit2d: Pass the source pitch into the shader
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 28 Mar 2016 22:37:47 +0000 (15:37 -0700)]
anv/blit2d: Break the texelfetch portion of shader building into a helper
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 29 Mar 2016 21:06:32 +0000 (14:06 -0700)]
anv/blit2d: Fix whitespace
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 28 Mar 2016 22:39:17 +0000 (15:39 -0700)]
anv/blit2d: Fix a NIR writemask
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 28 Mar 2016 22:25:47 +0000 (15:25 -0700)]
anv/meta2d: Don't declare an array sampler in the fragment shader
With the new blit framework we aren't using array textures and, from
talking with Nanley, we don't think it's going to be useful in the future
either. Just get rid of it for now.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 28 Mar 2016 22:20:26 +0000 (15:20 -0700)]
anv/blit2d: Remove the tex_dim parameter from copy_fragment_shader
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Thu, 7 Apr 2016 23:56:34 +0000 (16:56 -0700)]
Merge remote-tracking branch 'public/master' into vulkan
Jason Ekstrand [Tue, 5 Apr 2016 17:37:54 +0000 (10:37 -0700)]
i965/fs: Use the scale helper in surface_builder
As requested by Curro
Marek Olšák [Sun, 3 Apr 2016 01:21:47 +0000 (03:21 +0200)]
radeonsi: do per-pixel clipping based on viewport states
In other words, vport scissors are derived from viewport states.
If the scissor test is enabled, the intersection of both is used.
The guard band will disable clipping, so we have to clip per-pixel.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Thu, 7 Apr 2016 20:38:47 +0000 (22:38 +0200)]
nv50/ir: do not try to attach JOIN ops to ATOM
This might result in an INVALID_OPCODE dmesg error in case a join is
attached to an atomic operation.
Spotted with arb_shader_image_load_store-host-mem-barrier on GK104.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Nicolai Hähnle [Wed, 6 Apr 2016 17:00:08 +0000 (12:00 -0500)]
radeonsi: raise number of samplers per shader to 32
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94835
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Apr 2016 16:58:42 +0000 (11:58 -0500)]
radeonsi: expand the compressed color and depth texture masks to 64 bits
This is in preparation of raising the number of exposed sampler views to 32
bits, which will raise the total number of sampler views to 33 for the
polygon stipple texture. That texture should never be compressed (and it's
certainly not a depth texture), but this approach seems cleaner to me than
special-casing the last slot in all affected code paths.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Apr 2016 16:45:37 +0000 (11:45 -0500)]
radeonsi: replace magic 16 by SI_NUM_USER_SAMPLERS
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Apr 2016 16:51:47 +0000 (11:51 -0500)]
gallium: raise PIPE_MAX_SAMPLERS to 32
The previous value of 18 was motivated by having drivers that want to expose
16 samplers but also use some additional samplers for internal use. Raising
the value even higher isn't going to hurt that case.
On the other hand, some drivers actually use PIPE_MAX_SAMPLERS as the number
of samplers they expose externally, so raising this number above 32 is fragile
(because several places in the code use bitfields, and tracking down and
widening all of them is prone to miss some case).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 6 Apr 2016 21:21:28 +0000 (16:21 -0500)]
st/glsl_to_tgsi: make samplers_used an uint32_t (v2)
It is used as a bitfield, so it seems cleaner to keep it unsigned.
The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.
v2: add an assert for bitfield size and use 1u << idx
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Nicolai Hähnle [Thu, 7 Apr 2016 17:19:56 +0000 (12:19 -0500)]
tgsi/scan: add an assert for the size of the samplers_declared bitfield
The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.
Reviewed-by: Brian Paul <brianp@vmware.com>
Nicolai Hähnle [Wed, 6 Apr 2016 21:27:21 +0000 (16:27 -0500)]
draw/aaline: stronger guard against no free samplers (v2)
Line anti-aliasing will fail when there is no free sampler available. Make
the corresponding guard more robust in preparation of raising
PIPE_MAX_SAMPLERS to 32.
The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.
v2: add an assert for bitfield size and use 1u << idx
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Nicolai Hähnle [Wed, 6 Apr 2016 17:57:51 +0000 (12:57 -0500)]
util/pstipple: stronger guard against no free samplers (v2)
When hasFixedUnit is false, polygon stippling will fail when there is no free
sampler available. Make the corresponding guard more robust in preparation
of raising PIPE_MAX_SAMPLERS to 32.
The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.
v2: add an assert for bitfield size and use 1u << idx
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Brian Paul [Tue, 5 Apr 2016 01:39:58 +0000 (19:39 -0600)]
svga: new SVGA_MSAA env var to disable/enable MSAA pixel formats
On by default.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Tue, 5 Apr 2016 15:56:49 +0000 (09:56 -0600)]
svga: add some trivial null pointer checks
These small mallocs will probably never fail, but static analysis tools
may complain about the missing checks.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Samuel Pitoiset [Tue, 5 Apr 2016 17:37:16 +0000 (19:37 +0200)]
trace: add missing set_shader_images()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 7 Apr 2016 00:27:01 +0000 (02:27 +0200)]
radeonsi: disable perfect ZPASS counts for PIPE_QUERY_OCCLUSION_PREDICATE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Apr 2016 22:49:32 +0000 (00:49 +0200)]
radeonsi: don't use the real barrier instruction in tess ctrl shaders
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Thu, 7 Apr 2016 06:05:33 +0000 (15:05 +0900)]
Revert "clover: Fix build against clang SVN >= r265359"
This reverts commit
0daab9878d2b96356cf667591a2c877d912be52d.
The corresponding clang change was reverted.
Trivial.
Jason Ekstrand [Fri, 25 Mar 2016 23:12:19 +0000 (16:12 -0700)]
nir/types: Add a wrapper for count_attribute_slots
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian Høgsberg Kristensen [Thu, 7 Apr 2016 00:07:08 +0000 (17:07 -0700)]
genxml: Add GEN6 genxml
Not used yet, but let's put it here for now.
Dave Airlie [Wed, 6 Apr 2016 21:38:21 +0000 (22:38 +0100)]
r600: use radeon_emit in a few more places in evergreen_compute
This is just a cleanup of the code.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:35:53 +0000 (22:35 +0100)]
r600: make compute global buffer functions static.
This moves things around so that the global buffer handling
functions in evergreen_compute.c are static.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:35:12 +0000 (22:35 +0100)]
r600: make two compute functions static.
These aren't used outside evergreen_compute.c
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:28:23 +0000 (22:28 +0100)]
r600: using pipe_grid_info more in evergreen_compute.
No reason to pull the pieces apart here, also make
one of the functions static as it's unused outside this.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:24:35 +0000 (22:24 +0100)]
r600: in evergreen_compute use ctx consistently instead of ctx_
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:23:32 +0000 (22:23 +0100)]
r600: use rctx consistently in evergreen_compute.c
Another step towards cleaning this up.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Apr 2016 21:20:17 +0000 (22:20 +0100)]
r600: cleanup whitespace in evergreen_compute.c
This aligns the code with the style of the rest of the driver.
Makes editing it a lot less painful.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Mon, 1 Feb 2016 00:18:15 +0000 (11:18 +1100)]
GL3.txt: Mark ARB_framebuffer_no_attachments as done
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Mon, 1 Feb 2016 01:12:12 +0000 (12:12 +1100)]
r600g: Enable ARB_framebuffer_no_attachments
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 1 Jan 2016 18:53:57 +0000 (05:53 +1100)]
radeonsi: Enable ARB_framebuffer_no_attachments
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sun, 20 Mar 2016 07:01:06 +0000 (18:01 +1100)]
radeonsi: Improve assert info out of si_set_framebuffer_state()
Lets give the developer a little hand if we are going to assert
on a zero literal at the end of a branch.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sun, 20 Mar 2016 03:50:04 +0000 (14:50 +1100)]
radeonsi: Allow 16 samples MSAA mode for PIPE_FORMAT_NONE
For ARB_framebuffer_no_attachment; A is_format_supported() query
with 'PIPE_FORMAT_NONE' passed implies a query of the number of
samples supported from the framebuffer with no attachment.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 12 Feb 2016 10:11:57 +0000 (21:11 +1100)]
softpipe: Set samples and layers in set_framebuffer_state() cb
Carries across the number of samples and layers state in the
'softpipe_set_framebuffer_state()' callback. This state is
part of 'ARB_framebuffer_no_attachments' support.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sun, 3 Jan 2016 10:08:33 +0000 (21:08 +1100)]
mesa/st: Update framebuffer state with no.of samples,layers
Handle the case of ARB_framebuffer_no_attachment.
Also, kill off a dead debug printf() call while we are here.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Mon, 1 Feb 2016 00:16:06 +0000 (11:16 +1100)]
gallium/trace: Dump no.of samples and layers in fb state
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sat, 2 Jan 2016 14:44:55 +0000 (01:44 +1100)]
gallium: Put no.of {samples,layers} into pipe_framebuffer_state
Here we store the number of samples and layers directly in the
pipe_framebuffer_state so that in the case of
ARB_framebuffer_no_attachment we may make use of them directly.
Further, we adjust various gallium/auxiliary helper functions
accordingly.
V2:
Convert branches in util_framebuffer_get_num_layers() and
util_framebuffer_get_num_samples() to their canonical form.
V3:
'git stash pop' the typo fix of 'cbufs' which should be
'nr_cbufs' that was missing in V2, woops! Thanks Marek for
pointing this out yet again.
V4:
Squash in the following patch:
'gallium/util: Ensure util_framebuffer_get_num_samples() is valid'
Upon context creation, internal driver structures are malloc()'ed
and memset() to zero them. This results in a invalid number of
samples 'by default'. Handle this in the simplest way to avoid
elaborate and probably equally sub-optimial solutions.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Tue, 16 Feb 2016 23:27:41 +0000 (10:27 +1100)]
mesa/st: Set _NumSamples in update_framebuffer_state()
Using PIPE_FORMAT_NONE to indicate what MSAA modes are supported
with a framebuffer using no attachment.
V.2:
Rewrite MSAA mode loop to be more general.
V.3:
Move comment to right place after loop was rewritten.
V.4: [airlied]
remove unneeded variable, and assert, and unneeded pipe assignment
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Wed, 17 Feb 2016 10:01:57 +0000 (21:01 +1100)]
gallium: Obtain ARB_framebuffer_no_attachment constants
Set default values for the constants required in
ARB_framebuffer_no_attachments and obtained the number
of layers from ``PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS``.
We also obtain the MaxFramebufferSamples value using
a query back to the driver for PIPE_FORMAT_NONE.
V.1:
Merge if branch predicates into one branch.
Move const init into st_init_limits()
[airlied: whitespace fixup]
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Wed, 17 Feb 2016 09:59:52 +0000 (20:59 +1100)]
gallium: Add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
Add PIPE_CAP to determine if the GL extension
'GL_ARB_framebuffer_no_attachments' shall be
supported.
The driver is required to support 'PIPE_FORMAT_NONE'
via its 'is_format_supported()' callback in order
to determine the MSAA modes the hardware supports so
that values requested from the application using
'GL_ARB_framebuffer_no_attachments' may be quantized
to what the hardware expects.
V.2:
Fix doc for a more detailed description of the PIPE_CAP
and the corresponding GL constant.
V.3:
Renamed and repurposed once again.
V.4:
Remove CAP from cap_mapping array.
[airlied: fix damaged whitespace]
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Fri, 1 Jan 2016 18:55:49 +0000 (05:55 +1100)]
mesa/st: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometric_ convenience functions
for those places where the geometry of the gl_framebuffer is needed.
This is in contrast to the geometry of the intersection of the
attachments of the gl_framebuffer.
This patch paves the way to enable GL_ARB_framebuffer_no_attachements
for all gallium drivers.
V.2:
Remove itermeditate variable state.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Wed, 17 Feb 2016 08:15:49 +0000 (19:15 +1100)]
mesa: Add comment to framebuffer_parameteri()
V.2:
Change 'N.B.,' to 'NOTE:'.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Wed, 6 Apr 2016 01:23:36 +0000 (18:23 -0700)]
i965/sf_state: Pull flat_enables out of prog_data
Previously, we were walking over the shader source to figure out which
inputs should be marked flat. Now, we can just pull it out of prog_data.
This is needed for properly setting up 3DSTATE_SF/SBE for Vulkan and it
also means that it will get properly cached.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 6 Apr 2016 01:19:34 +0000 (18:19 -0700)]
i965/fs: Add a flat_inputs field to prog_data
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Mon, 4 Apr 2016 21:50:03 +0000 (14:50 -0700)]
brw/device_info: Add a helper for getting a device name
This is needed by the Vulkan driver
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 19 Jan 2016 01:30:59 +0000 (17:30 -0800)]
i965/fs_surface_builder: Mask signed integers after conversion
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Mon, 4 Apr 2016 21:38:42 +0000 (14:38 -0700)]
i965/fs: Make the repclear shader support either a uniform or a flat input
In the Vulkan driver we use a single flat input instead of a uniform
because setting up push constants is more disruptive to the pipeline than
setting up another vertex input. This uses the number of uniforms as a key
to keep it working for the GL driver.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 22 Oct 2015 03:40:28 +0000 (20:40 -0700)]
i965: Move get_hw_prim_for_gl_prim to brw_util.c
It's used by brw_compile_gs in brw_vec4_gs_visitor.cpp so it needs to be in
a file that's linked into libi965_compiler.la.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Thu, 31 Mar 2016 09:58:26 +0000 (11:58 +0200)]
radeonsi: set shader calling conventions
Note that old mesa + new LLVM or new mesa + old LLVM breaks
with this change and the corresponding LLVM change (D18559).
For LLVM version <= 3.8 we use the old method, but we can't detect
people using a post 3.8 svn version that is still too old.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 31 Mar 2016 21:32:53 +0000 (23:32 +0200)]
drirc: add a workaround for blackness in Warsow
Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Mon, 4 Apr 2016 15:54:22 +0000 (11:54 -0400)]
glsl: use has_shader_storage_buffer_objects helper
Replaces open-coded logic with existing helper.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Sun, 3 Apr 2016 08:33:40 +0000 (18:33 +1000)]
glsl: remove remaining tabs in link_uniform_blocks.cpp
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Sun, 3 Apr 2016 05:14:14 +0000 (15:14 +1000)]
mesa: remove unused IsShaderStorage field
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Sun, 3 Apr 2016 02:44:33 +0000 (12:44 +1000)]
glsl: fully split apart buffer block arrays
With this change we create the UBO and SSBO arrays separately from the
beginning rather than putting them into a combined array and splitting
it apart later.
A bug is with UBO and SSBO stage reference querying is also fixed as
we now use the block index to lookup the references in the separate arrays
not the combined buffer block array.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Rob Clark [Tue, 5 Apr 2016 17:45:34 +0000 (13:45 -0400)]
freedreno/ir3: insert extra move into phi
We had an implicit assumption that the phi src was assigned in it's
source (pred) block leading into the phi. But this is not true with
NIR, so we can't just ignore the source block specified in the
nir_phi_src. Insert an extra mov in the source block. If it is not
required the CP pass will take it back out again.
Fixes:
./tests/spec/glsl-1.10/execution/vs-call-in-nested-loop.shader_test
./tests/spec/glsl-1.10/execution/vs-inner-loop-modifies-outer-loop-var.shader_test
and probably others.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 5 Apr 2016 16:39:47 +0000 (12:39 -0400)]
freedreno/ir3: eliminate unnecessary absneg's
The frontend inserts (abs) and (neg)'s to convert between NIR boolean
(~0/0) and native boolean (1/0). So we'd end up with things like:
cmps.s.ge r1.x, ...
absneg.s r1.x, (neg)r1.x
absneg.s r1.x, (abs)r1.x
sel.b32 r2.x, r0.x, r1.x, r0.y
The (neg) already gets collapsed due to the following (abs). Now by
realizing that r1.x comes from a cmps.s instruction, we can drop the
(abs) as well.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Michel Dänzer [Tue, 5 Apr 2016 06:43:35 +0000 (15:43 +0900)]
clover: Fix build against clang SVN >= r265359
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Bas Nieuwenhuizen [Sun, 3 Apr 2016 09:45:02 +0000 (11:45 +0200)]
radeonsi: use bounded indexing for samplers
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bas Nieuwenhuizen [Sun, 3 Apr 2016 09:39:52 +0000 (11:39 +0200)]
radeonsi: use bounded indexing for constant buffers
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 28 Mar 2016 23:36:40 +0000 (01:36 +0200)]
gallium/radeon: allow multiple exports of the same texture with different usage
Instead of failing an assertion, disable DCC and CMASK on the first export
that needs it, and merge the external usage flags.
v2: clear the EXPLICIT_FLUSH flag if it's not set; whitespace fixes
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Tue, 5 Apr 2016 13:32:16 +0000 (15:32 +0200)]
docs/relnotes: document EGL_KHR_reusable_sync
Dongwon Kim [Tue, 5 Apr 2016 00:14:10 +0000 (17:14 -0700)]
egl: add EGL_KHR_reusable_sync to egl_dri
This patch enables an EGL extension, EGL_KHR_reusable_sync.
This new extension basically provides a way for multiple APIs or
threads to be excuted synchronously via a "reusable sync"
primitive shared by those threads/API calls.
This was implemented based on the specification at
https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_reusable_sync.txt
v2
- use thread functions defined in C11/threads.h instead of
using direct pthread calls
- make the timeout set with reference to CLOCK_MONOTONIC
- cleaned up the way expiration time is calculated
- (bug fix) in dri2_client_wait_sync, case EGL_SYNC_CL_EVENT_KHR
has been added.
- (bug fix) in dri2_destroy_sync, return from cond_broadcast
call is now stored in 'err' intead of 'ret' to prevent 'ret'
from being reset to 'EGL_FALSE' even in successful case
- corrected minor syntax problems
v3
- dri2_egl_unref_sync now became 'void' type. No more error check
is needed for this function call as a result.
- (bug fix) resolved issue with duplicated unlocking of display in
eglClientWaitSync when type of sync is "EGL_KHR_REUSABLE_SYNC"
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Mon, 4 Apr 2016 21:38:01 +0000 (17:38 -0400)]
freedreno/ir3: deal with duplicate phi sources
Otherwise we end up with funny things like:
mov.f32f32 r0.x, r1.y
mov.f32f32 r0.x, r1.y
(It doesn't happen as much after fixing the problem w/ CP into phi src,
but it can still happen since we aren't too clever about generating phi
sources in the first place.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 4 Apr 2016 21:36:41 +0000 (17:36 -0400)]
freedreno/ir3: fix silly brain-fart in RA
We want to consider all the vars, not 1/32nd of them, when extending
live-ranges.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 4 Apr 2016 21:34:57 +0000 (17:34 -0400)]
freedreno/ir3: don't cp into phi's
The block defining a phi source might not have been executed. If we
allow copy propagation, we could end up pointing to a src instruction in
the wrong block.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 4 Apr 2016 21:33:19 +0000 (17:33 -0400)]
freedreno/ir3: we can't store immediate values
Fixes some transform-feedback piglits, like:
bin/ext_transform_feedback-nonflat-integral
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 4 Apr 2016 18:16:12 +0000 (14:16 -0400)]
freedreno/ir3: add dumping for use/def/live-in/live-out
Turned out to be useful to debug an issue in RA. Let's keep it.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 4 Apr 2016 21:54:39 +0000 (17:54 -0400)]
freedreno/ir3: drop unused instr category arg
No longer used, so drop the extra arg to ir3_instr_create()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 27 Mar 2016 17:43:45 +0000 (13:43 -0400)]
freedreno/ir3: remove ir3_instruction::category
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 27 Mar 2016 15:40:36 +0000 (11:40 -0400)]
freedreno/ir3: encode instruction category in opc_t
Been on my TODO list for a while. If nothing else this will make gdb
properly grok the opc_t enum.
This first step preserves ir3_instruction::category (with an added
assert that category matches what is encoded in opc_t). Next step is
to drop the category field (and arg to ir3_instr_create()), but that
is split into next commit for bisectability and so that we can run
piglit in the intermediate state to flush out any problems.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Jason Ekstrand [Fri, 25 Mar 2016 18:19:53 +0000 (11:19 -0700)]
i965/fs: Move the code for load/store_shared to emit_cs_intrinsic
They are compute-shader only and that's where the code for doing atomics on
shared variables lives so it seemes to make sense.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 25 Mar 2016 21:02:50 +0000 (14:02 -0700)]
i965/nir: Provide a default LOD for buffer textures
Our hardware requires an LOD for all texelFetch commands even if they are
on buffer textures. GLSL IR gives us an LOD of 0 in that case, but the LOD
is really rather meaningless. This commit allows other NIR producers to be
more lazy and not provide one at all.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Mon, 4 Apr 2016 21:51:35 +0000 (14:51 -0700)]
i965/compiler: Remove a redundant declaration of brw_compiler_create
Kenneth Graunke [Mon, 4 Apr 2016 02:51:22 +0000 (19:51 -0700)]
nir: Use PRIi64 and PRIu64 instead of %ld and %lu.
%ld and %lu aren't the right format specifiers for int64_t and uint64_t
on 32-bit (x86) systems. They're %zu on Linux and %Iu on Windows.
Use the standard C99 macros in hopes that they work everywhere.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 30 Mar 2016 19:00:02 +0000 (12:00 -0700)]
i965: Fix invalid pointer read in dead_control_flow_eliminate().
There may not be a previous block. In this case, there's no real work
to do, so just continue on to the next one.
v2: Update for bblock->prev() API change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 30 Mar 2016 19:00:02 +0000 (12:00 -0700)]
i965: Make bblock_t::next and friends return NULL at sentinels.
The bblock_t::prev/prev_const/next/next_const API returns bblock_t
pointers, rather than exec_nodes. So it's a bit surprising.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 4 Apr 2016 07:31:45 +0000 (00:31 -0700)]
glsl: Lower variable indexing of system value arrays unconditionally.
lower_variable_index_to_cond_assign() did not handle system values.
gl_SampleMaskIn[] is a system value, and also an array. Accessing it
with a variable index would trigger an unreachable() assert.
Rather than adding a new EmitNoIndirectSystemValues flag, we simply
lower unconditionally. There is exactly one case where this occurs,
and for all current drivers, lowering produces optimal code. Even
for future drivers with 32x MSAA, it produces reasonable code.
Fixes Piglit's new samplemaskin-indirect test. Also fixes many ES31-CTS
tests when OES_sample_variables is enabled.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Mon, 4 Apr 2016 21:25:36 +0000 (14:25 -0700)]
i965/defines: Unconditionally define primitives
Jason Ekstrand [Mon, 4 Apr 2016 20:58:05 +0000 (13:58 -0700)]
Merge remote-tracking branch 'public/master' into vulkan
Jason Ekstrand [Mon, 28 Mar 2016 18:47:27 +0000 (11:47 -0700)]
i965/peephole_ffma: Only match a mul+add if none of the ops are exact
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Mon, 28 Mar 2016 18:12:33 +0000 (11:12 -0700)]
nir/search: Don't match inexact expressions with exact subexpressions
In the first pass of implementing exact handling, I made a mistake with
search-and-replace. In particular, we only reallly handled exact/inexact
on the root of the tree. Instead, we need to check every node in the tree
for an exact/inexact match. As an example of this, consider the following
GLSL code
precise float a = b + c;
if (a < 0) {
do_stuff();
}
In that case, only the add will be declared "exact" and an expression that
looks for "b + c < 0" will still match and replace it with "b < -c" which
may yield different results. The solution is to simply bail if any of the
values are exact when matching an inexact expression.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Mon, 4 Apr 2016 19:10:20 +0000 (12:10 -0700)]
nir: Stop double-printing function arguments
Jason Ekstrand [Mon, 4 Apr 2016 19:09:10 +0000 (12:09 -0700)]
glsl: Stop force-enabling compute shaders
This isn't needed since we no longer use the GLSL compiler in Vulkan.
Jason Ekstrand [Mon, 4 Apr 2016 19:05:07 +0000 (12:05 -0700)]
glsl/standalone: Get rid of the unneeded _mesa_error_no_memory stub
This hasn't been needed since we stopped using the GLSL compiler in the
Vulkan driver and it was tripping up scons. Removing it fixes the scons
build.
Kenneth Graunke [Wed, 27 Jan 2016 20:21:04 +0000 (12:21 -0800)]
i965: Add an INTEL_PRECISE_TRIG=1 option to fix SIN/COS output range.
The SIN and COS instructions on Intel hardware can produce values
slightly outside of the [-1.0, 1.0] range for a small set of values.
Obviously, this can break everyone's expectations about trig functions.
According to an internal presentation, the COS instruction can produce
a value up to 1.000027 for inputs in the range (0.08296, 0.09888). One
suggested workaround is to multiply by 0.99997, scaling down the
amplitude slightly. Apparently this also minimizes the error function,
reducing the maximum error from 0.00006 to about 0.00003.
When enabled, fixes 16 dEQP precision tests
dEQP-GLES31.functional.shaders.builtin_functions.precision.
{cos,sin}.{highp,mediump}_compute.{scalar,vec2,vec4,vec4}.
at the cost of making every sin and cos call more expensive (about
twice the number of cycles on recent hardware). Enabling this
option has been shown to reduce GPUTest Volplosion performance by
about 10%.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Mon, 4 Apr 2016 18:24:48 +0000 (11:24 -0700)]
Remove more spirv2nir remnants
Kenneth Graunke [Mon, 4 Apr 2016 07:45:25 +0000 (00:45 -0700)]
i965: Allow 8x MSAA on >= 64bpp formats on Gen8+.
See commit
3b0279a69 - this restriction is documented in the "Surface
Format" field of RENDER_SURFACE_STATE.
Looking at newer documentation, this restriction appears to exist on
Haswell, but no longer applies on Gen8+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Brian Paul [Mon, 4 Apr 2016 16:33:11 +0000 (10:33 -0600)]
docs: remove stray 'TBD' in 11.2.0 relnotes file
Emil Velikov [Mon, 4 Apr 2016 11:57:56 +0000 (12:57 +0100)]
docs: add news item and link release notes for 11.2.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>