OSDN Git Service
Jakob Stoklund Olesen [Sat, 9 Jul 2011 01:02:44 +0000 (01:02 +0000)]
Oops, didn't mean to commit that.
Spills should be hoisted out of loops, but we don't want to hoist them
to dominating blocks at the same loop depth. That could cause the spills
to be executed more often.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134782
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Lang Hames [Sat, 9 Jul 2011 00:36:54 +0000 (00:36 +0000)]
Added test cases for GVN signed intrinsics recognition, r134777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134778
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Lang Hames [Sat, 9 Jul 2011 00:25:11 +0000 (00:25 +0000)]
Added recognition for signed add/sub/mul with overflow intrinsics to GVN as per Chris and Frits suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134777
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Jakob Stoklund Olesen [Sat, 9 Jul 2011 00:25:03 +0000 (00:25 +0000)]
Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.
This fixes PR10221.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776
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Eli Friedman [Fri, 8 Jul 2011 23:43:01 +0000 (23:43 +0000)]
Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134773
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Eli Friedman [Fri, 8 Jul 2011 23:07:42 +0000 (23:07 +0000)]
Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134768
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Evan Cheng [Fri, 8 Jul 2011 22:49:55 +0000 (22:49 +0000)]
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134764
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Evan Cheng [Fri, 8 Jul 2011 22:49:42 +0000 (22:49 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134763
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Cameron Zwarich [Fri, 8 Jul 2011 22:49:34 +0000 (22:49 +0000)]
Add an fma TableGen node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134762
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Evan Cheng [Fri, 8 Jul 2011 22:36:29 +0000 (22:36 +0000)]
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760
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Bob Wilson [Fri, 8 Jul 2011 22:33:59 +0000 (22:33 +0000)]
Update comments for SandyBridge CPU identifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134759
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Jim Grosbach [Fri, 8 Jul 2011 22:33:49 +0000 (22:33 +0000)]
Mark tBRIND as predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134758
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Evan Cheng [Fri, 8 Jul 2011 22:30:25 +0000 (22:30 +0000)]
Restore old behavior. Always auto-detect features unless cpu or features are specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134757
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Evan Cheng [Fri, 8 Jul 2011 22:29:33 +0000 (22:29 +0000)]
Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756
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Jim Grosbach [Fri, 8 Jul 2011 22:25:23 +0000 (22:25 +0000)]
Pseudo-ize tBRIND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134755
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Eli Friedman [Fri, 8 Jul 2011 22:16:47 +0000 (22:16 +0000)]
Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753
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Cameron Zwarich [Fri, 8 Jul 2011 22:13:55 +0000 (22:13 +0000)]
Use add instead of accumulate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134752
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Bob Wilson [Fri, 8 Jul 2011 22:09:35 +0000 (22:09 +0000)]
Recognize Intel CPUs with Family=6 and Model=44.
According to Intel Application Note 485, this value is used for
"Intel Core i7 and Intel Xeon processor". Just include it with the other
"corei7-avx" entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134750
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Bob Wilson [Fri, 8 Jul 2011 22:09:33 +0000 (22:09 +0000)]
Reapply a fixed version of r133285.
This tightens up checking for overflow in alloca sizes, based on feedback
from Duncan and John about the change in r132926.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134749
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Jim Grosbach [Fri, 8 Jul 2011 21:50:04 +0000 (21:50 +0000)]
Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746
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Julien Lerouge [Fri, 8 Jul 2011 21:40:25 +0000 (21:40 +0000)]
Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744
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Cameron Zwarich [Fri, 8 Jul 2011 21:39:21 +0000 (21:39 +0000)]
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742
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Evan Cheng [Fri, 8 Jul 2011 21:14:14 +0000 (21:14 +0000)]
For non-x86 host, used generic as CPU name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134741
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Jim Grosbach [Fri, 8 Jul 2011 21:10:35 +0000 (21:10 +0000)]
Pseudo-ize tBX_RET and tBX_RET_vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134739
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Benjamin Kramer [Fri, 8 Jul 2011 21:06:23 +0000 (21:06 +0000)]
Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134738
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Jim Grosbach [Fri, 8 Jul 2011 21:04:05 +0000 (21:04 +0000)]
Shuffle productions around a bit.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134737
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Jakob Stoklund Olesen [Fri, 8 Jul 2011 20:46:18 +0000 (20:46 +0000)]
Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.
To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.
Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.
Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735
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Jim Grosbach [Fri, 8 Jul 2011 20:39:19 +0000 (20:39 +0000)]
Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134734
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Jim Grosbach [Fri, 8 Jul 2011 20:32:21 +0000 (20:32 +0000)]
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732
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Benjamin Kramer [Fri, 8 Jul 2011 20:18:13 +0000 (20:18 +0000)]
Silence compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134730
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Jim Grosbach [Fri, 8 Jul 2011 20:18:11 +0000 (20:18 +0000)]
Add more info to FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134729
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Jim Grosbach [Fri, 8 Jul 2011 20:13:35 +0000 (20:13 +0000)]
Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134727
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Eli Friedman [Fri, 8 Jul 2011 20:07:05 +0000 (20:07 +0000)]
Fix dangling pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134725
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Evan Cheng [Fri, 8 Jul 2011 19:33:14 +0000 (19:33 +0000)]
TargetAsmParser doesn't need reference to Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134721
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Benjamin Kramer [Fri, 8 Jul 2011 19:32:06 +0000 (19:32 +0000)]
Remove unused copy of UpdateInlinedAtInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134720
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Jim Grosbach [Fri, 8 Jul 2011 18:50:22 +0000 (18:50 +0000)]
Use ARMPseudoExpand for ARM tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719
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Jim Grosbach [Fri, 8 Jul 2011 18:26:27 +0000 (18:26 +0000)]
Shuffle productions around a bit.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134714
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Jim Grosbach [Fri, 8 Jul 2011 18:15:12 +0000 (18:15 +0000)]
Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134712
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Evan Cheng [Fri, 8 Jul 2011 18:04:22 +0000 (18:04 +0000)]
Fix a dangling reference. Patch by Dave Abrahams. pr10311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134709
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Devang Patel [Fri, 8 Jul 2011 18:01:31 +0000 (18:01 +0000)]
Refactor. It is inliner's responsibility to update line number information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134708
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Chandler Carruth [Fri, 8 Jul 2011 17:54:08 +0000 (17:54 +0000)]
Add CMake support for the new TableGen file introduced in r134705.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134707
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Jim Grosbach [Fri, 8 Jul 2011 17:40:42 +0000 (17:40 +0000)]
Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705
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Jim Grosbach [Fri, 8 Jul 2011 17:36:35 +0000 (17:36 +0000)]
TableGen'erated MC lowering for simple pseudo-instructions.
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704
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Devang Patel [Fri, 8 Jul 2011 17:09:57 +0000 (17:09 +0000)]
Refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134703
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Devang Patel [Fri, 8 Jul 2011 16:49:43 +0000 (16:49 +0000)]
Make provision to have floating point constants in .debug_loc expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134702
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Benjamin Kramer [Fri, 8 Jul 2011 12:08:24 +0000 (12:08 +0000)]
Apparently we can't expect a BinaryOperator here.
Should fix llvm-gcc selfhost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134699
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NAKAMURA Takumi [Fri, 8 Jul 2011 10:45:15 +0000 (10:45 +0000)]
cmake/modules/LLVMLibDeps.cmake: Update to appease cmake builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134696
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Benjamin Kramer [Fri, 8 Jul 2011 10:31:30 +0000 (10:31 +0000)]
Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.
struct foo { char x[24]; };
long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
movl 4(%esp), %eax
subl 8(%esp), %eax
sarl $3, %eax
imull $-
1431655765, %eax, %eax
instead of
movl 4(%esp), %eax
subl 8(%esp), %eax
movl $
715827883, %ecx
imull %ecx
movl %edx, %eax
shrl $31, %eax
sarl $2, %edx
addl %eax, %edx
movl %edx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695
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Evan Cheng [Fri, 8 Jul 2011 01:53:10 +0000 (01:53 +0000)]
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678
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Lang Hames [Fri, 8 Jul 2011 01:50:54 +0000 (01:50 +0000)]
Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134677
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Akira Hatanaka [Fri, 8 Jul 2011 00:42:35 +0000 (00:42 +0000)]
Raise assertion when MachineOperand has unexpected target flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134671
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Akira Hatanaka [Fri, 8 Jul 2011 00:26:25 +0000 (00:26 +0000)]
Make sure variable Kind is assigned a value to suppress warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134668
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Jakob Stoklund Olesen [Fri, 8 Jul 2011 00:24:06 +0000 (00:24 +0000)]
Fix more register allocation sensitive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134667
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Jakob Stoklund Olesen [Fri, 8 Jul 2011 00:24:03 +0000 (00:24 +0000)]
Remove a test that no longer makes sense.
It was testing a linear scan feature:
Test if linearscan is unfavoring registers for allocation to allow
more reuse of reloads from stack slots.
The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134666
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Nick Lewycky [Fri, 8 Jul 2011 00:19:27 +0000 (00:19 +0000)]
Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665
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Eric Christopher [Fri, 8 Jul 2011 00:04:56 +0000 (00:04 +0000)]
Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.
Fixes PR9675 and rdar://
9740801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664
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Akira Hatanaka [Thu, 7 Jul 2011 23:56:50 +0000 (23:56 +0000)]
Lower MachineInstr to MC Inst and print to .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661
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Chandler Carruth [Thu, 7 Jul 2011 23:45:45 +0000 (23:45 +0000)]
Fix CMake build's library dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134658
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Eric Christopher [Thu, 7 Jul 2011 22:54:12 +0000 (22:54 +0000)]
Handle fpcr register.
Part of PR10299 and rdar://
9740322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134653
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Eric Christopher [Thu, 7 Jul 2011 22:29:07 +0000 (22:29 +0000)]
Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://
9738585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648
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Eric Christopher [Thu, 7 Jul 2011 22:29:03 +0000 (22:29 +0000)]
Remove a FIXME. All of the standard ones are in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134647
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Akira Hatanaka [Thu, 7 Jul 2011 22:06:18 +0000 (22:06 +0000)]
Remove unnecessary newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134645
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Devang Patel [Thu, 7 Jul 2011 21:44:42 +0000 (21:44 +0000)]
Add DEBUG message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134643
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Evan Cheng [Thu, 7 Jul 2011 21:06:52 +0000 (21:06 +0000)]
Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641
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Bill Wendling [Thu, 7 Jul 2011 21:05:13 +0000 (21:05 +0000)]
Move a function out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640
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Akira Hatanaka [Thu, 7 Jul 2011 20:54:20 +0000 (20:54 +0000)]
Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637
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Akira Hatanaka [Thu, 7 Jul 2011 20:30:33 +0000 (20:30 +0000)]
This patch adds a flag in MCAsmInfo that indicates whether dwarf register
numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134635
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Akira Hatanaka [Thu, 7 Jul 2011 20:24:54 +0000 (20:24 +0000)]
Define class MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633
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Akira Hatanaka [Thu, 7 Jul 2011 20:10:52 +0000 (20:10 +0000)]
Change visibility of MipsAsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630
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Akira Hatanaka [Thu, 7 Jul 2011 19:27:22 +0000 (19:27 +0000)]
Define class MipsMCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134629
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Akira Hatanaka [Thu, 7 Jul 2011 19:13:09 +0000 (19:13 +0000)]
Simplify MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628
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Evan Cheng [Thu, 7 Jul 2011 19:09:06 +0000 (19:09 +0000)]
Rewrite comment in English.
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Evan Cheng [Thu, 7 Jul 2011 19:05:12 +0000 (19:05 +0000)]
Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
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Akira Hatanaka [Thu, 7 Jul 2011 18:57:00 +0000 (18:57 +0000)]
Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625
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Akira Hatanaka [Thu, 7 Jul 2011 18:27:36 +0000 (18:27 +0000)]
Add missing return statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622
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Devang Patel [Thu, 7 Jul 2011 17:45:33 +0000 (17:45 +0000)]
If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.
310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
DBG_VALUE 3.
310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]
These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620
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Joerg Sonnenberger [Thu, 7 Jul 2011 16:53:52 +0000 (16:53 +0000)]
Recognize mipseb as alias for mips for symmetry with mipsel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134617
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Oscar Fuentes [Thu, 7 Jul 2011 16:33:00 +0000 (16:33 +0000)]
Update CMake library dependencies
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Douglas Gregor [Thu, 7 Jul 2011 15:59:22 +0000 (15:59 +0000)]
Fix CMake build
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Cameron Zwarich [Thu, 7 Jul 2011 08:28:52 +0000 (08:28 +0000)]
The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609
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Evan Cheng [Thu, 7 Jul 2011 08:26:46 +0000 (08:26 +0000)]
Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608
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Evan Cheng [Thu, 7 Jul 2011 07:45:49 +0000 (07:45 +0000)]
Feature bits are 64-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134607
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Evan Cheng [Thu, 7 Jul 2011 07:07:08 +0000 (07:07 +0000)]
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606
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Chris Lattner [Thu, 7 Jul 2011 05:29:18 +0000 (05:29 +0000)]
type can be null
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Chris Lattner [Thu, 7 Jul 2011 05:12:37 +0000 (05:12 +0000)]
use a more efficient check for 'is metadata'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134599
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Bill Wendling [Thu, 7 Jul 2011 04:42:01 +0000 (04:42 +0000)]
Use ArrayRef instead of a std::vector&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134595
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Lang Hames [Thu, 7 Jul 2011 04:31:51 +0000 (04:31 +0000)]
Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.
X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)
Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).
Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134592
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Evan Cheng [Thu, 7 Jul 2011 03:55:05 +0000 (03:55 +0000)]
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590
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Bill Wendling [Thu, 7 Jul 2011 00:54:13 +0000 (00:54 +0000)]
Add a target hook to encode the compact unwind information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134577
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Jim Grosbach [Thu, 7 Jul 2011 00:48:02 +0000 (00:48 +0000)]
Add isCodeGenOnly value to the CodeGenInstruction class.
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134576
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Lang Hames [Thu, 7 Jul 2011 00:36:02 +0000 (00:36 +0000)]
Added a testcase for PR10220.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134573
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Devang Patel [Thu, 7 Jul 2011 00:14:27 +0000 (00:14 +0000)]
Add DEBUG messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134572
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Evan Cheng [Thu, 7 Jul 2011 00:08:19 +0000 (00:08 +0000)]
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569
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Devang Patel [Thu, 7 Jul 2011 00:05:58 +0000 (00:05 +0000)]
Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134568
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Jakub Staszak [Wed, 6 Jul 2011 23:50:16 +0000 (23:50 +0000)]
Fix a bug in the "expect" intrinsic lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134566
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Eli Friedman [Wed, 6 Jul 2011 23:41:48 +0000 (23:41 +0000)]
When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.
<rdar://problem/
9716278>
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Jim Grosbach [Wed, 6 Jul 2011 23:38:13 +0000 (23:38 +0000)]
Typo.
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Devang Patel [Wed, 6 Jul 2011 23:26:18 +0000 (23:26 +0000)]
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134561
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Devang Patel [Wed, 6 Jul 2011 23:09:51 +0000 (23:09 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134559
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Bill Wendling [Wed, 6 Jul 2011 22:52:32 +0000 (22:52 +0000)]
Clean up the #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134557
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