OSDN Git Service
Vedant Kumar [Mon, 4 Jun 2018 03:33:01 +0000 (03:33 +0000)]
[Debugify] Add debug intrinsics before terminating musttail calls
After r333856, opt -debugify would just stop emitting debug value
intrinsics after encountering a musttail call. This wasn't sufficient to
avoid verifier failures.
Debug value intrinicss for all instructions preceding a musttail call
must also be emitted before the musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333866
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Mon, 4 Jun 2018 02:52:36 +0000 (02:52 +0000)]
[InstCombine] Fix div handling
When we optimize select basing on fact that div by 0 is undef
we should not traverse the instruction which are not guaranteed to
transfer execution to next instruction. Guard intrinsic is an example.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333864
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Mon, 4 Jun 2018 00:11:49 +0000 (00:11 +0000)]
[Debugify] Don't apply DI before the bitcode writer pass
Applying synthetic debug info before the bitcode writer pass has no
testing-related purpose. This commit prevents that from happening.
It also adds tests which check that IR produced with/without
-debugify-each enabled is identical after stripping. This makes it
possible to check that individual passes (or full pipelines) are
invariant to debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333861
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Mon, 4 Jun 2018 00:11:48 +0000 (00:11 +0000)]
[opt] Add a -strip-module-flags option
The -strip-module-flags option strips llvm.module.flags metadata from a
module at the beginning of the opt pipeline.
This will be used to test whether the output of a pass is debug info
(DI) invariant.
E.g, after applying synthetic debug info to a test case, we'd like to
strip out all DI-related metadata and check that the final IR is
identical to a baseline file without any DI applied, to check that
optimizations aren't inhibited by debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333860
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Mon, 4 Jun 2018 00:11:47 +0000 (00:11 +0000)]
Reformat overflowing lines, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333859
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 3 Jun 2018 23:24:17 +0000 (23:24 +0000)]
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333857
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Sun, 3 Jun 2018 22:50:22 +0000 (22:50 +0000)]
[Debugify] Skip dbg.value placement for EH pads, musttail
Placing meta-instructions into EH pads breaks certain IR invariants, as
does placing instructions after a musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333856
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Sun, 3 Jun 2018 20:33:42 +0000 (20:33 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333854
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Sun, 3 Jun 2018 19:22:48 +0000 (19:22 +0000)]
[ORC] Add a constructor to create an IRMaterializationUnit from a module and
pre-existing SymbolFlags and SymbolToDefinition maps.
This constructor is useful when delegating work from an existing
IRMaterialiaztionUnit to a new one, as it avoids the cost of re-computing these
maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333852
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 18:15:06 +0000 (18:15 +0000)]
[X86][TBM] Use realistic BEXTR control bits
Avoid constant values that are guaranteed to give zero
Found while investigating BEXTR optimizations for PR34042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333849
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 3 Jun 2018 16:35:26 +0000 (16:35 +0000)]
[InstCombine] improve sub with bool folds
There's a patchwork of existing transforms trying to handle
these cases, but as seen in the changed test, we weren't
catching them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333845
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 14:56:04 +0000 (14:56 +0000)]
[X86][AVX512] Cleanup intrinsics tests
Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333843
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 14:31:30 +0000 (14:31 +0000)]
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
Require manual stripping of existing CHECKs as update_llc_test_checks doesn't remove them if they're outside the function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333842
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 14:11:34 +0000 (14:11 +0000)]
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests
Further refactoring will wait until D47452 has landed.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333841
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 13:55:17 +0000 (13:55 +0000)]
[X86][BMI] Remove CTTZ tests - this is fully covered in clz.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333840
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 3 Jun 2018 13:38:52 +0000 (13:38 +0000)]
[X86][TBM] Branch off i32 intrinsics and test on 32/64 bits
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333839
91177308-0d34-0410-b5e6-
96231b3b80d8
Amaury Sechet [Sun, 3 Jun 2018 12:56:24 +0000 (12:56 +0000)]
Remove SETCCE use from Lanai's backend
Summary: This creates a small perf regression, but after talking with Jacques Pienaar, he was good with it to get things moving toward removng SETCCE.
Reviewers: jpienaar, bryant
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333838
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Sun, 3 Jun 2018 02:18:03 +0000 (02:18 +0000)]
[ORC] Use JITEvaluatedSymbol for IndirectStubsManager findStub and findPointer.
Existing implementations of these methods do not require lazy materialization,
and switching to JITEvaluatedSymbol allows us to remove error checking on the
client side.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333835
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 21:35:48 +0000 (21:35 +0000)]
[X86][SSE] Cleanup AVX1 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary, strip -mcpu usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333834
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 20:25:56 +0000 (20:25 +0000)]
[X86][SSE] Cleanup SSE1 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333833
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 19:43:14 +0000 (19:43 +0000)]
[X86][SSE] Cleanup SSE2 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333832
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 18:41:46 +0000 (18:41 +0000)]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333831
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 18:01:09 +0000 (18:01 +0000)]
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333830
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 17:33:26 +0000 (17:33 +0000)]
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
Added some missing encoding checks to SSE4A tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333828
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 17:22:13 +0000 (17:22 +0000)]
[X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests
I had to tweak the i32 tests so we check both reg-reg and reg-mem cases.
I also added i64 load tests.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333827
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 2 Jun 2018 17:02:27 +0000 (17:02 +0000)]
[X86][BMI1] Remove test for non-existent andn i16 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333826
91177308-0d34-0410-b5e6-
96231b3b80d8
Ivan A. Kosarev [Sat, 2 Jun 2018 16:40:03 +0000 (16:40 +0000)]
[NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)
We currently support them only in AArch64. The NEON Reference,
however, says they are 'ARMv7, ARMv8' intrinsics.
Differential Revision: https://reviews.llvm.org/D47120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333825
91177308-0d34-0410-b5e6-
96231b3b80d8
Ivan A. Kosarev [Sat, 2 Jun 2018 16:38:38 +0000 (16:38 +0000)]
Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)"
The LLVM part was committed instead of the Clang part.
Differential Revision: https://reviews.llvm.org/D47121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333824
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Sat, 2 Jun 2018 16:33:01 +0000 (16:33 +0000)]
[MC] Add assembler support for .cg_profile.
Object FIle Representation
At codegen time this is emitted into the ELF file a pair of symbol indices and a weight. In assembly it looks like:
.cg_profile a, b, 32
.cg_profile freq, a, 11
.cg_profile freq, b, 20
When writing an ELF file these are put into a SHT_LLVM_CALL_GRAPH_PROFILE (0x6fff4c02) section as (uint32_t, uint32_t, uint64_t) tuples as (from symbol index, to symbol index, weight).
Differential Revision: https://reviews.llvm.org/D44965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333823
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 2 Jun 2018 16:30:39 +0000 (16:30 +0000)]
[X86] Add tied source operand to AVX5124FMAPS and AVX5124VNNIW instructions.
This doesn't affect the assembly or disassembly, but is more accurate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333822
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 2 Jun 2018 16:30:36 +0000 (16:30 +0000)]
[X86] Fix warning message for AVX5124FMAPS and AVX5124VNNIW instructions in the assembly parser.
The caret was positioned on the wrong operand. It's too hard to get right so just put the caret at the beginning of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333821
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 2 Jun 2018 16:27:44 +0000 (16:27 +0000)]
[InstCombine] call simplify before trying vector folds
As noted in the review thread for rL333782, we could have
made a bug harder to hit if we were simplifying instructions
before trying other folds.
The shuffle transform in question isn't ever a simplification;
it's just a canonicalization. So I've renamed that to make that
clearer.
This is NFCI at this point, but I've regenerated the test file
to show the cosmetic value naming difference of using
instcombine's RAUW vs. the builder.
Possible follow-ups:
1. Move reassociation folds after simplifies too.
2. Refactor common code; we shouldn't have so much repetition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333820
91177308-0d34-0410-b5e6-
96231b3b80d8
Ivan A. Kosarev [Sat, 2 Jun 2018 16:26:42 +0000 (16:26 +0000)]
[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)
We currently support them only in AArch64. The NEON Reference,
however, says they are 'ARMv7, ARMv8' intrinsics.
Differential Revision: https://reviews.llvm.org/D47121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333819
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 2 Jun 2018 16:16:42 +0000 (16:16 +0000)]
[InstCombine] add more tests for shuffle-binop; NFC
As noted in the review thread for rL333782, we're lacking coverage
for this transform, so add tests for each binop opcode with constant
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333818
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Sat, 2 Jun 2018 06:00:35 +0000 (06:00 +0000)]
[Support] Remove unused raw_ostream::handle whose anchor role was superseded by anchor()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333817
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 2 Jun 2018 02:15:10 +0000 (02:15 +0000)]
[X86] Add encoding information for the AVX5124FMAPS and AVX5124VNNIW instructions so they can be assembled and disassembled.
These instructions are unusual in that they operate on 4 consecutive registers so supporting them in codegen will be more difficult than normal.
Includes an assembler check to warn if the source register is not the first register of a 4 register group.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333812
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sat, 2 Jun 2018 01:29:01 +0000 (01:29 +0000)]
[PM/LoopUnswitch] Fix how the cloned loops are handled when updating analyses.
Summary:
I noticed this issue because we didn't put the primary cloned loop into
the `NonChildClonedLoops` vector and so never iterated on it. Once
I fixed that, it made it clear why I had to do a really complicated and
unnecesasry dance when updating the loops to remain in canonical form --
I was unwittingly working around the fact that the primary cloned loop
wasn't in the expected list of cloned loops. Doh!
Now that we include it in this vector, we don't need to return it and we
can consolidate the update logic as we correctly have a single place
where it can be handled.
I've just added a test for the iteration order aspect as every time
I changed the update logic partially or incorrectly here, an existing
test failed and caught it so that seems well covered (which is also
evidenced by the extensive working around of this missing update).
Reviewers: asbirlea, sanjoy
Subscribers: mcrosier, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333811
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Sat, 2 Jun 2018 00:05:17 +0000 (00:05 +0000)]
Remove the test from r333801
In r333801 I added a test for a dump method that, for reasons I don't
understand, fails on an msvc bot:
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/12306/
I'll remove the test for now to unblock the bot and try to look into why
there's a discrepancy on this platform later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333807
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Tereshin [Fri, 1 Jun 2018 23:15:09 +0000 (23:15 +0000)]
[DebugInfo] Refactoring DIType::setFlags to DIType::cloneWithFlags, NFC
and using the latter in DIBuilder::createArtificialType and
DIBuilder::createObjectPointerType methods as well as introducing
mirroring DISubprogram::cloneWithFlags and
DIBuilder::createArtificialSubprogram methods.
The primary goal here is to add createArtificialSubprogram to support
a pass downstream while keeping the method consistent with the
existing ones and making sure we don't encourage changing already
created DI-nodes.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D47615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333806
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Fri, 1 Jun 2018 23:09:37 +0000 (23:09 +0000)]
Revert "Re-land: [MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333803.
Still breaking on big endian. Will sort this out later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333805
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 22:59:07 +0000 (22:59 +0000)]
[X86] Do something sensible when an expand load intrinsic is passed a 0 mask.
Previously we just returned undef, but really we should be returning the pass thru input. We also need to make sure we preserve the chain output that the original intrinsic node had to maintain connectivity in the DAG. So we should just return the incoming chain as the output chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333804
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Fri, 1 Jun 2018 22:52:59 +0000 (22:52 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333803
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Fri, 1 Jun 2018 22:33:15 +0000 (22:33 +0000)]
Add a debug dump for DbgValueHistoryMap
This makes it easier to inspect the results of
DbgValueHistoryCalculator.
Differential Revision: https://reviews.llvm.org/D47663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333801
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 22:28:28 +0000 (22:28 +0000)]
[X86] Add isel patterns to use vexpand with zero masking when the passthru value is a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333800
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Fri, 1 Jun 2018 22:28:23 +0000 (22:28 +0000)]
Revert "[MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333797.
This patch is failing on BigEndian bots. I will fix and re-land:
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/19505/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333799
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Fri, 1 Jun 2018 22:23:46 +0000 (22:23 +0000)]
Move some function declarations out of WindowsSupport.h
The idea behind WindowsSupport.h is that it's in the source directory so
that windows.h'isms don't leak out into the larger LLVM project. To that
end, any symbol that references a symbol from windows.h must be in this
private header, and not in a public header.
However, we had some useful utility functions in WindowsSupport.h which
have no dependency on the Windows API, but still only make sense on
Windows. Those functions should be usable outside of Support since there
is no risk of causing a windows.h leak. Although this introduces some
preprocessor logic in some header files, It's not too egregious and it's
better than the alternative of duplicating a ton of code.
Differential Revision: https://reviews.llvm.org/D47662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333798
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Fri, 1 Jun 2018 22:07:36 +0000 (22:07 +0000)]
[MachO] Fixing ub in MachO BinaryFormat
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333797
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 21:59:24 +0000 (21:59 +0000)]
[X86] Expand the testing of expand and compress intrinsics
The avx512f intrinsic tests were in the avx512vl file. We were also missing some combinations of masking.
This does show that we fail to use the zero masking form of expand loads when the passthru is zero. I'll try to get that fixed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333795
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 21:59:22 +0000 (21:59 +0000)]
[X86] Add fast-isel tests for avx512vbmi2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333794
91177308-0d34-0410-b5e6-
96231b3b80d8
Karl-Johan Karlsson [Fri, 1 Jun 2018 19:34:35 +0000 (19:34 +0000)]
[ConstantFold] Disallow folding vector geps into bitcasts
Summary:
Getelementptr returns a vector of pointers, instead of a single address,
when one or more of its arguments is a vector. In such case it is not
possible to simplify the expression by inserting a bitcast of operand(0)
into the destination type, as it will create a bitcast between different
sizes.
Reviewers: majnemer, mkuper, mssimpso, spatel
Reviewed By: spatel
Subscribers: lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D46379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333783
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 1 Jun 2018 19:23:18 +0000 (19:23 +0000)]
[InstCombine] fix vector shuffle transform to replace undef elements (PR37648)
This bug:
https://bugs.llvm.org/show_bug.cgi?id=37648
...was created with the enhancement to this transform with rL332479.
The urem test shows the disaster potential: any undef divisor lane makes
the whole op undef.
The test diffs show that vector demanded elements turns some of the potential,
but not all, unused binop operands back into undef already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333782
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 1 Jun 2018 18:52:38 +0000 (18:52 +0000)]
[InstCombine] add tests for broken shuffle transform (PR37648)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333779
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Fri, 1 Jun 2018 16:37:53 +0000 (16:37 +0000)]
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.
The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.
Differential Revision: https://reviews.llvm.org/D47316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333774
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Fri, 1 Jun 2018 16:37:42 +0000 (16:37 +0000)]
[mips] Extend list of relocations supported by the `.reloc` directive
Supporting GOT and TLS related relocations by the `.reloc` directive is
useful for purpose of testing various tools like a linker, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333773
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Semel [Fri, 1 Jun 2018 16:19:46 +0000 (16:19 +0000)]
[llvm-objcopy] Fix null symbol handling
This fixes the bug where strip-all option was
leading to a malformed outputted ELF file.
Differential Revision: https://reviews.llvm.org/D47414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333772
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 1 Jun 2018 15:39:10 +0000 (15:39 +0000)]
[Hexagon] Avoid UB when shifting unsigned integer left by 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333771
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 1 Jun 2018 15:21:14 +0000 (15:21 +0000)]
[LangRef] fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333770
91177308-0d34-0410-b5e6-
96231b3b80d8
Vlad Tsyrklevich [Fri, 1 Jun 2018 15:20:47 +0000 (15:20 +0000)]
[ThinLTOBitcodeWriter] Emit summaries for regular LTO modules
Summary:
Emit summaries for bitcode modules that are only destined for the
regular LTO portion of the build so they can participate in
summary-based dead stripping.
This change reduces the size of a nacl_helper build with cfi-icall
enabled by 7%, removing the majority of the overhead due to enabling
cfi-icall. The cfi-icall size increase was caused by compiling in lots
of unused code and cfi-icall generating jumptable references to unused
symbols that could no longer be removed by -Wl,-gc-sections. Increasing
the visibility of summary-based dead stripping prevented jumptable
entries being created for unused symbols from the regular LTO portion
of the build.
Reviewers: pcc
Reviewed By: pcc
Subscribers: dschuff, mehdi_amini, inglorion, eraman, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D47594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333768
91177308-0d34-0410-b5e6-
96231b3b80d8
Karl-Johan Karlsson [Fri, 1 Jun 2018 15:08:14 +0000 (15:08 +0000)]
[ConstantFold] Add lit testcase for bitcast problem. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333767
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 1 Jun 2018 15:05:55 +0000 (15:05 +0000)]
[DAG] Avoid checking for consecutive stores in store merge. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333766
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 1 Jun 2018 15:05:30 +0000 (15:05 +0000)]
[DAG] Simplify Expression. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333765
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 1 Jun 2018 15:05:05 +0000 (15:05 +0000)]
[DAG] Remove untriggerable check. NFCI.
Candidate check precludes this check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333764
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Fri, 1 Jun 2018 15:04:40 +0000 (15:04 +0000)]
[DAG] Prune store merge legal store check to stop invalid size. NFCI.
Do not consider store sizes large than the maximum legal store size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333763
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 1 Jun 2018 14:52:58 +0000 (14:52 +0000)]
[Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333760
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Fri, 1 Jun 2018 14:49:06 +0000 (14:49 +0000)]
[llvm-exegesis] Fix off-by-one in llvm-exegesis documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333759
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 1 Jun 2018 14:39:05 +0000 (14:39 +0000)]
[InstCombine] add baseline test for bug with div+select transform (D47576)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333756
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 1 Jun 2018 14:35:21 +0000 (14:35 +0000)]
[llvm-mca] Move the logic that computes the block throughput into Support.h. NFC
This will allow us to share the logic that computes the block throughput with
other views.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333755
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Inoue [Fri, 1 Jun 2018 14:23:15 +0000 (14:23 +0000)]
[NFC] Zero initialize local variables
This patch makes local variables zero initialized to avoid broken values in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333754
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Fri, 1 Jun 2018 14:18:02 +0000 (14:18 +0000)]
[llvm-exegesis] Analysis: Display idealized sched class port pressure.
Summary: Screenshot in phabricator diff.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D47329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333753
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 1 Jun 2018 14:00:32 +0000 (14:00 +0000)]
[SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for target
Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing
the UADDO/USUBO expansion.
Differential Revision: https://reviews.llvm.org/D47559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333751
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Ivchenko [Fri, 1 Jun 2018 13:51:53 +0000 (13:51 +0000)]
[x86] NFC. Reautogenerate test/CodeGen/X86/vector-half-conversions.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333750
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 1 Jun 2018 13:37:01 +0000 (13:37 +0000)]
[Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003)
This patch replaces the --x86_extra_scrub command line argument to automatically support a second level of regex-scrubbing if it improves the matching of nearly-identical code patterns. The argument '--extra_scrub' is there now to force extra matching if required.
This is mostly useful to help us share 32-bit/64-bit x86 vector tests which only differs by retl/retq instructions, but any scrubber can now technically support this, meaning test checks don't have to be needlessly obfuscated.
I've updated some of the existing checks that had been manually run with --x86_extra_scrub, to demonstrate the extra "ret{{[l|q]}}" scrub now only happens when useful, and re-run the sse42-intrinsics file to show extra matches - most sse/avx intrinsics files should be able to now share 32/64 checks.
Tested with the opt/analysis scripts as well which share common code - AFAICT the other update scripts use their own versions.
Differential Revision: https://reviews.llvm.org/D47485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333749
91177308-0d34-0410-b5e6-
96231b3b80d8
Amaury Sechet [Fri, 1 Jun 2018 13:21:33 +0000 (13:21 +0000)]
Set ADDE/ADDC/SUBE/SUBC to expand by default
Summary:
They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while.
Target that uses these opcodes are changed in order to ensure their behavior doesn't change.
Reviewers: efriedma, craig.topper, dblaikie, bkramer
Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D47422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333748
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Fri, 1 Jun 2018 13:20:32 +0000 (13:20 +0000)]
[AArch64][GlobalISel] Zero-extend s1 values when returning.
Before we were relying on the any extend of the s1 to s32, but
for AAPCS we need to zero-extend it to at least s8.
Fixes PR36719
Differential Revision: https://reviews.llvm.org/D47425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333747
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 1 Jun 2018 12:58:43 +0000 (12:58 +0000)]
Revert r333740: IPSCCP] Use PredicateInfo to propagate facts from cmp.
This is breaking the clang-with-thin-lto-ubuntu bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333745
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Fri, 1 Jun 2018 12:54:46 +0000 (12:54 +0000)]
[AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.
Unpredicated copy of floating-point immediate value into SVE vector,
along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333744
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Fri, 1 Jun 2018 10:57:13 +0000 (10:57 +0000)]
[mips] Guard more aliases correctly.
Also, duplicate an alias for microMIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333741
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 1 Jun 2018 10:48:54 +0000 (10:48 +0000)]
Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.
As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.
Reviewers: davide, mssimpso, dberlin, efriedma
Reviewed By: davide, dberlin
Differential Revision: https://reviews.llvm.org/D45330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333740
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Fri, 1 Jun 2018 10:46:00 +0000 (10:46 +0000)]
[mips] Guard 'nop' properly and add mips16's nop instruction
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333739
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Fri, 1 Jun 2018 10:33:11 +0000 (10:33 +0000)]
DWARFAcceleratorTable: Add an iterator-based api for accessing names in the index
Summary:
Back when we were introducing the DWARF v5 name index, there was a
short discussion whether we shouldn't have a nicer api for iterating
over the index. At that time, I did not find it necessary since the
iteration over names was done only from within the index itself (and I
figured the internal implementation can deal with a slightly rough
interface).
However, now I ran into a use for this kind of API in LLDB (for finding
all names matching a regular expression), so it looked like a nice
opportunity to introduce one. To make the API more useful, I've made the
NameTableEntry class a bit smarter: it now stores the string section
reference (so it can return its name) and its position in the name index
(mainly useful for dumping/logging).
I also convert the internal users to use the new API, which also gives
test coverage for the added code.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333738
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Fri, 1 Jun 2018 10:07:10 +0000 (10:07 +0000)]
[mips] Select the correct instruction for computing frameindexes
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333736
91177308-0d34-0410-b5e6-
96231b3b80d8
Gabor Buella [Fri, 1 Jun 2018 07:47:46 +0000 (07:47 +0000)]
NFC Avoid a warning in WasmEHPrepare.cpp
```
../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic]
false, false);
^
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333732
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Fri, 1 Jun 2018 07:25:46 +0000 (07:25 +0000)]
[AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.
Unpredicated copy of repeating immediate pattern to SVE vector, along
with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333731
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Fri, 1 Jun 2018 07:06:03 +0000 (07:06 +0000)]
AMDGPU: Switch some half using-tests to use amdhsa
The default clover ABI weirdly promotes half to float,
which should probably be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333730
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 06:11:29 +0000 (06:11 +0000)]
[X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR.
This is different than the behavior of EVEX.X extending modrm.rm to 5 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333728
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 05:36:08 +0000 (05:36 +0000)]
[X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when modrm.rm encodes a k-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333727
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Cederman [Fri, 1 Jun 2018 05:31:58 +0000 (05:31 +0000)]
Implemented sane default for llvm-objdump's relocation Value format
Summary:
"Unknown" for platforms that were not manually added into the switch
did not make sense at all. Now it prints Target + addend for all
elf-machines that were not explicitly mentioned.
Addresses PR21059 and PR25124.
Original author: fedor.sergeev
Reviewers: jyknight, espindola, fedor.sergeev
Reviewed By: jyknight
Subscribers: eraman, dcederman, jfb, dschuff, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333726
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 05:12:44 +0000 (05:12 +0000)]
[X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.
A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333725
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 05:12:43 +0000 (05:12 +0000)]
[X86] Add a test case showing a bad disassembling of an EVEX instruction with EVEX.X=0 and a GPR encoded in modrm.rm.
EVEX.X is used to extended modrm.rm when the instruction encodes a XMM/YMM/ZMM register. But we aren't properly ignoring it when it encodes a GPR and we end up printing whatever registers exist in X86 register enum after the GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333724
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 04:29:34 +0000 (04:29 +0000)]
[X86][Disassembler] Make sure EVEX.X is not used to extend base registers of memory operations.
This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3.
I think there are still more bugs related to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333722
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 04:29:30 +0000 (04:29 +0000)]
[X86][Disassembler] Use a local variable instead of using a field in the instruction object. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333721
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Fri, 1 Jun 2018 02:19:46 +0000 (02:19 +0000)]
AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D47487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333720
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 01:23:52 +0000 (01:23 +0000)]
[X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333717
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 00:10:36 +0000 (00:10 +0000)]
[X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333714
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 1 Jun 2018 00:10:32 +0000 (00:10 +0000)]
[X86] Add test cases showing the disassembler producing an xmm16-xmm31 register in 32-bit mode.
We aren't properly suppressing the reading of VEX.R' and VEX.V' in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333713
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Fri, 1 Jun 2018 00:03:21 +0000 (00:03 +0000)]
Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.
Summary:
`getEHScopeMembership()` function is used not only for funclet-based
EHs; they apply to all EH schemes that use the scoped IR
(catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of
the term 'funclet' to 'EH scopes' in case they apply to all scoped EH,
and this fixes more of them. For `FuncletLayout` pass, I left it as is
because the pass is only used for funclet-based EH.
Reviewers: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333711
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Thu, 31 May 2018 22:35:25 +0000 (22:35 +0000)]
[WebAssembly] Update to the new names for the memory intrinsics.
The WebAssembly committee has decided on the names `memory.size` and
`memory.grow` for the memory intrinsics, so update the LLVM intrinsics to
follow those names, keeping both sets of old names in place for
compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333708
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 31 May 2018 22:31:02 +0000 (22:31 +0000)]
[LoopVectorize, x86] add tests to show missing SVML transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333707
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Thu, 31 May 2018 22:27:24 +0000 (22:27 +0000)]
[WebAssembly] Fix the signatures for the __mulo* libcalls.
The __mulo* libcalls have an extra i32* to return the overflow value.
Fixes PR37401.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333706
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 31 May 2018 22:25:54 +0000 (22:25 +0000)]
[WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.
Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.
This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)
Reviewers: dschuff, majnemer
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D44090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333705
91177308-0d34-0410-b5e6-
96231b3b80d8