OSDN Git Service
Marek Olšák [Fri, 24 Jun 2016 00:22:42 +0000 (02:22 +0200)]
radeonsi: fix a compute shader hang with big threadgroups on SI & CI
ported from Vulkan
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
1e8adb0ee43062210ca54821a880ef08bfdba1b7)
[Emil Velikov: resolve trivial conflict in si_launch_grid()]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeonsi/si_compute.c
Ilia Mirkin [Fri, 24 Jun 2016 02:33:59 +0000 (22:33 -0400)]
nvc0: when mapping directly, provide accurate xfer info + start
We were ignoring the incoming box parameters, and were providing totally
bogus stride/layer stride, and other bits, for when a non-full-surface
map was requested.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b433cb51e50cab878cbaa023662bacd1f923a183)
Nicolai Hähnle [Thu, 23 Jun 2016 23:11:09 +0000 (01:11 +0200)]
radeonsi: drop the DRAW_PREAMBLE packet on Polaris
It will be removed from the firmware for the Polaris.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
0da890e62cf14fef273500491d14fb8d980fe452)
Nicolai Hähnle [Thu, 23 Jun 2016 13:00:53 +0000 (15:00 +0200)]
radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris
The non-MULTI variants will be removed in Polaris firmware.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
2aa0485902cdb4cd02b72627a760b00e71bffecf)
Jordan Justen [Wed, 22 Jun 2016 17:34:08 +0000 (17:34 +0000)]
i965: Preserve the internal format of the dri image
Since the OpenGLES API is strict about the internal format matching
the for many operations, we need to preserve it.
See _mesa_es3_error_check_format_and_type in
src/mesa/main/glformats.c.
Fixes ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96351
Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
(cherry picked from commit
c36a363a2d305a987ef2ea843fe9fc860b576eed)
Kenneth Graunke [Wed, 22 Jun 2016 18:25:26 +0000 (11:25 -0700)]
i965: Implement rasterizer discard via SOL unless required for queries.
We currently use CL_INVOCATION_COUNT for the GL_PRIMITIVES_GENERATED
query, which involves passing all primitives to the clipper. When
rasterizer discard is enabled, we program the clipper in REJECT_ALL
mode, rather than using the SOL stage's "Rendering Disable" feature.
See commit
f09b91f78247409f54c975f56cb10d5f350fe64e for an explanation
of why we implement GL_PRIMITIVES_GENERATED this way.
Apparently the SOL stage's "Rendering Disable" feature is a lot faster
than having the clipper reject all primitives. It's safe to use when
no GL_PRIMITIVES_GENERATED query is active, as we don't care about
CL_INVOCATION_COUNT incrementing.
This patch makes us use SO_RENDERING_DISABLE when no query is active,
but continues falling back to the clipper in REJECT_ALL mode when the
queries are enabled. It brings back the perf_debug for the clipper
case (which I removed in commit
1f9445ff57b, thinking it wasn't useful).
Improves performance in Gl32GSCloth by 84.8303% +/- 2.07132% (n = 10)
on my Broadwell GT2 laptop.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
b0629e6894513a2c49a018bc3342a4e55435a236)
Kenneth Graunke [Wed, 22 Jun 2016 07:33:46 +0000 (00:33 -0700)]
i965: Combine 3DSTATE_STREAMOUT emitters and genX_sol_state atoms.
They're basically the same. Let's avoid the code duplication.
v2: Fix SO_BUFFER_ENABLE stuff to only happen on Gen < 8 (caught
by Jason Ekstrand).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
4db98f8beb990676be0833dda6c37566d0283911)
Kenneth Graunke [Sat, 30 Apr 2016 00:57:46 +0000 (17:57 -0700)]
glsl: Don't constant propagate arrays.
Constant propagation on arrays doesn't make a lot of sense. If the
array is only accessed with constant indexes, then opt_array_splitting
would split it up. Otherwise, we have variable indexing. If there's
multiple accesses, then constant propagation would end up replicating
the data.
The lower_const_arrays_to_uniforms pass creates uniforms for each
ir_constant with array type that it encounters. This means that it
creates redundant uniforms for each copy of the constant, which means
uploading too much data. It can even mean exceeding the maximum number
of uniform components, causing link failures.
We could try and teach the pass to de-duplicate the data by hashing
constants, but it makes more sense to avoid duplicating it in the first
place. We should promote constant arrays to uniforms, then propagate
the uniform access.
Fixes the TressFX shaders from Tomb Raider, which exceeded the maximum
number of uniform components by a huge margin and failed to link.
On Broadwell:
total instructions in shared programs:
9067702 ->
9068202 (0.01%)
instructions in affected programs: 10335 -> 10835 (4.84%)
helped: 10 (Hoard, Shadow of Mordor, Amnesia: The Dark Descent)
HURT: 20 (Natural Selection 2)
loops in affected programs: 4 -> 0
The hurt programs appear to no longer have a constarray uniform, as
all constants were successfully propagated. Apparently before this
patch, we successfully unrolled a loop containing array access, but
only after promoting constant arrays to uniforms. With this patch,
we unroll it first, so all array access is direct, and the array
is split up, and individual constants are propagated. This seems
better.
Cc: mesa-stable@lists.freedesktop.org
Reported-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
fb857b5eea43640bfe19dcc12a88a09a6448e55a)
Kenneth Graunke [Sat, 30 Apr 2016 01:05:26 +0000 (18:05 -0700)]
glsl: Make lower_const_arrays_to_uniforms work directly on constants.
There's really no point in looking at ir_dereference_array of a
constant. It also misses cases like:
(assign () (var_ref tmp) (constant (array ...) ...))
No changes in shader-db, but keeps it working after the next commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7)
Kenneth Graunke [Sat, 30 Apr 2016 04:12:15 +0000 (21:12 -0700)]
i965: Copy propagate before doing variable index lowering.
The scalar backend currently doesn't support variable indexing on
temporary arrays, but it does support it on uniform arrays, and
some stages support it for input arrays. Make sure these are
propagated through before exploding indirects into piles of
if-ladders unnecessarily.
On Broadwell, no instruction count change in shader-db.
total cycles in shared programs:
80675652 ->
80674928 (-0.00%)
cycles in affected programs: 649972 -> 649248 (-0.11%)
helped: 386
HURT: 165
This will help avoid code quality regressions in a future commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
f7741c521119ce147215d94a4c238e84fc8b1130)
Kenneth Graunke [Wed, 22 Jun 2016 00:42:59 +0000 (17:42 -0700)]
glsl: Propagate invariant/precise after lowering const arrays.
The new uniform may need precise as well.
Fixes copy propagation of constant array uniforms in Tomb Raider shaders.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
586f4a42e78f171c28c3ae37adb8671e09bd74b4)
Kenneth Graunke [Mon, 20 Jun 2016 18:20:51 +0000 (11:20 -0700)]
glsl: Split arrays even in the presence of whole-array copies.
Previously, we failed to split constant arrays. Code such as
int[2] numbers = int[](1, 2);
would generates a whole-array assignment:
(assign () (var_ref numbers)
(constant (array int 4) (constant int 1) (constant int 2)))
opt_array_splitting generally tried to visit ir_dereference_array nodes,
and avoid recursing into the inner ir_dereference_variable. So if it
ever saw a ir_dereference_variable, it assumed this was a whole-array
read and bailed. However, in the above case, there's no array deref,
and we can totally handle it - we just have to "unroll" the assignment,
creating assignments for each element.
This was mitigated by the fact that we constant propagate whole arrays,
so a dereference of a single component would usually get the desired
single value anyway. However, I plan to stop doing that shortly;
early experiments with disabling constant propagation of arrays
revealed this shortcoming.
This patch causes some arrays in Gl32GSCloth's geometry shaders to be
split, which allows other optimizations to eliminate unused GS inputs.
The VS then doesn't have to write them, which eliminates the entire VS
(5 -> 2 instructions). It still renders correctly.
No other change in shader-db.
v2: Drop !AOA check and improve a comment (feedback from Tim Arceri).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
c264fdbc073a0dfc393f53a8be880f535fd4b988)
Kenneth Graunke [Mon, 20 Jun 2016 23:48:02 +0000 (16:48 -0700)]
glsl: Make constant propagation's folder not propagate into an LHS.
opt_constant_propagation.cpp contains constant folding code which can
actually do constant propagation in some cases. It was happily
propagating constants into the left-hand-side of assignments.
For example,
(assign () (var_ref temp) (constant ...))
would brilliantly be turned into:
(assign () (constant ...) (constant ....))
This is a bigger hammer than necessary - it prevents propagation
into the left-hand-side altogether. We could certainly do better
someday. Notably, the constant propagation pass itself already
takes this approach - it's just the constant propagation pass's
built-in constant folding code (which actually propagates, too)
that was broken.
No change in shader-db, but prevents regressions after future commits.
It seems plausible that this could be hit today, but I haven't seen it
happen.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
acf544404472488eec85fff249cbface7fa477b1)
Ardinartsev Nikita [Thu, 23 Jun 2016 01:28:11 +0000 (18:28 -0700)]
i965: Avoid division by zero.
Fixes regression introduced by
af5ca43f2676bff7499f93277f908b681cb821d0
Cc: "12.0 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
(cherry picked from commit
01c89ccc5d1529aa1efbae80c8ef641a59abbd93)
Tim Rowley [Fri, 17 Jun 2016 02:09:35 +0000 (21:09 -0500)]
swr: push/pop DEBUG macro around llvm includes
llvm redefines DEBUG; adding push/pop prevents a undefined reference
to debug_refcnt_state in llvm-3.7+.
v2: add undef DEBUG
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit
9ca741c64524a57f972ce050919a0e2dec3e64f3)
Jose Fonseca [Thu, 23 Jun 2016 10:18:21 +0000 (11:18 +0100)]
include: Require MSVC 2013 Update 4.
Earlier MSVC 2013 releases have troubles compiling some of our C99 code,
so make sure we have Update 4 to avoid confusion.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit
805dbdf06d98e6dcfe0b24e38cc13c88eb5f36be)
Jason Ekstrand [Thu, 16 Jun 2016 22:26:54 +0000 (15:26 -0700)]
anv: Use different BOs for different scratch sizes and stages
This solves a race condition where we can end up having different stages
stomp on each other because they're all trying to scratch in the same BO
but they have different views of its layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c2f2c8e407207c31c29aab5570d23cd6e98d287a)
Jason Ekstrand [Thu, 16 Jun 2016 21:58:25 +0000 (14:58 -0700)]
genxml: Make ScratchSpaceBasePointer an address instead of an offset
While we're here, we also fixup MEDIA_VFE_STATE and rename the field in
3DSTATE_VS on gen6-7.5 to be consistent with the others.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
45c0f60999587ed29a7a9b81f09950dd8f58fb49)
Jason Ekstrand [Thu, 16 Jun 2016 21:43:41 +0000 (14:43 -0700)]
anv: Add an allocator for scratch buffers
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
966bed17c1a04854b4a422d90de81744556204b6)
Jason Ekstrand [Tue, 7 Jun 2016 18:37:46 +0000 (11:37 -0700)]
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
The pack header generation scripts can't handle the case where you have
two addresses in the same dword; they just take whatever is the last one.
This meant that the MCS address wasn't properly getting handled. Since we
don't care about append counters, we can just re-arrange the XML for now.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
89ded099f840275d278c408e132ad5db39fdf5af)
Jason Ekstrand [Thu, 9 Jun 2016 20:56:16 +0000 (13:56 -0700)]
anv,isl: Lower storage image formats in anv
ISL was being a bit too clever for its own good and lowering the format for
us. This is all well and good *if* we always want to lower it. However,
the GL driver selectively lowers the format depending on whether the
surface is write-only or not.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d82322eb188f258a7dca9ea2b59cc0332dbc4d61)
Jason Ekstrand [Fri, 10 Jun 2016 17:45:43 +0000 (10:45 -0700)]
isl/state: Allow for full 31-bit buffer texture sizes
Ivy Bridge and above can handle up to 2^31 elements for RAW buffer
surfaces.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
97f12773b89a409d1368ce6b3b5badb9e75bbf53)
Jason Ekstrand [Sat, 11 Jun 2016 01:28:49 +0000 (18:28 -0700)]
isl/state: Don't use designated initializers for buffer surface state
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
bb64e666ba91ce9b1a7405a1c14d41d294062b9a)
Jason Ekstrand [Fri, 10 Jun 2016 01:48:07 +0000 (18:48 -0700)]
isl/state: Add assertions for buffer surface restrictions
Acked-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
4061fde66e9feefa051a02fe258d69fe817e6a8c)
Jason Ekstrand [Thu, 9 Jun 2016 22:08:13 +0000 (15:08 -0700)]
isl/state: Don't set SurfacePitch for gen9 1-D textures
This field is ignored by the hardware in this case and, on very large 1-D
textures, it can end up being larger than the maximum allowed value.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
ce24097abe1427463ac300a686e4c36ea07464fc)
Jason Ekstrand [Tue, 7 Jun 2016 21:33:40 +0000 (14:33 -0700)]
isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
This matches better what happens on gen8 where the "Tiled Surface" and
"Tile Walke" bits are combined into a single two-bit value. This is also
more consistent with what the GL driver does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
f47e23a8b6abd3bbc1d2d60c023c5a7ffaf70d72)
Jason Ekstrand [Tue, 7 Jun 2016 01:22:21 +0000 (18:22 -0700)]
isl/state: Emit no-op mip tail setup on SKL
This hasn't ever been a problem in the past but it is recommended by the
hardware docs.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
96706bad5ff37e56ee48f9bbb143d39a6e113a62)
Jason Ekstrand [Tue, 7 Jun 2016 01:21:17 +0000 (18:21 -0700)]
isl/state: Only set cube face enables if usage includes CUBE_BIT
It seems safe to set it all the time, but this reduces the diff between
the way i965 does it and what ISL does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
14d7c16e50f88720fa27722522d4ff89972a4f9d)
Jason Ekstrand [Sun, 5 Jun 2016 04:22:21 +0000 (21:22 -0700)]
isl/state: Use the layout for computing qpitch rather than dimensions
For depth/stencil 1-D textures on SKL, we want them layed out in the old
format that has been used since gen4. In order for the surface state
fill-out code to handle, this it needs to distinguish based on layout
rather than just dimensionality.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
5d24e9cfa126971518be662e57021322ebf67a9a)
Jason Ekstrand [Tue, 7 Jun 2016 15:05:45 +0000 (08:05 -0700)]
isl/state: Set the IntegerSurfaceFormat bit on Haswell
This fixes 688 Vulkan CTS tests on Haswell.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6a43204afa40359f73684d3ccc7db8c4dad6288b)
Jason Ekstrand [Tue, 7 Jun 2016 21:40:47 +0000 (14:40 -0700)]
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
324103da75abab5003b63ec996a2e8eb8de67049)
Jason Ekstrand [Fri, 17 Jun 2016 23:40:24 +0000 (16:40 -0700)]
isl/state: Don't set RenderTargetViewExtent for texture surfaces
The docs specify that this only matters for render targets and surfaces
used with typed dataport messages. On some platforms (gen4-6) the Depth
field has more bits than RenderTargetViewExtent so we can have textures
with more levels than we can render to.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
215282c9f41432a245e79cdf5f8328c6785e924a)
Jason Ekstrand [Tue, 7 Jun 2016 22:30:00 +0000 (15:30 -0700)]
isl/state: Set SurfaceArray based on the surface dimension
According to the PRM, you can't set SurfaceArray for 3D or buffer textures.
There doesn't seem to be a good reason not to set it when we can. On the
other hand, if we don't set it we can end up getting strange results for
1-layer array textures such as textureSize() returning the wrong results.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
bb326f7b01daeb97e544873f20a23614ed54c548)
Jason Ekstrand [Sun, 5 Jun 2016 03:48:55 +0000 (20:48 -0700)]
isl/state: Don't force-disable L2 bypass for everything
We already set the bit in the few cases where it's required by the docs so
there's no need to set it all the time. This has no noticable perf impact
for Dota 2 on Vulkan with the time demo I have.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d050ffbce950f8ececd12200145eb209819a421e)
Jason Ekstrand [Fri, 3 Jun 2016 02:02:23 +0000 (19:02 -0700)]
isl/state: Refactor the setup of clear colors
This commit switches clear colors to use #if's instead of a C if. This
lets us properly handle SNB where the clear color field doesn't exist.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
87f0ffa646e97def0f81ba2ad12eab2702dfd7b1)
Jason Ekstrand [Fri, 3 Jun 2016 02:00:10 +0000 (19:00 -0700)]
isl/state: Refactor the per-gen isl_to_gen_h/valign tables
This moves the #if's around so that halign and valign have different sets
of #if conditions. This also prepares us for SNB because isl_to_gen_halign
is not defined at all on gen6.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
62a5e6e03117e5eb3f777633409cb8036be6877d)
Jason Ekstrand [Fri, 3 Jun 2016 01:40:07 +0000 (18:40 -0700)]
isl/state: Return an extent3d from the halign/valign helper
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b1b0d6fb5415c874cbbd1346e50d04e33b0e9c21)
Jason Ekstrand [Wed, 8 Jun 2016 00:01:56 +0000 (17:01 -0700)]
isl/state: Put pitch calculations together
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a60ae9e10ab8cd22f80dc91ba29e27db17ab3372)
Jason Ekstrand [Tue, 7 Jun 2016 23:58:54 +0000 (16:58 -0700)]
isl/state: Put all dimension setup together and towards the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
70c8afc0c892c2a3819ea01cf5b9467d80b4d7b5)
Jason Ekstrand [Wed, 8 Jun 2016 00:14:39 +0000 (17:14 -0700)]
isl/state: Put surface format setup at the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
e66e70ef47907264757751206878b703bd95390b)
Jason Ekstrand [Tue, 7 Jun 2016 23:55:21 +0000 (16:55 -0700)]
isl/state: Remove some unused fields
They're already zero-initialized and we have no plans of doing anything
more interesting with them.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
39baea551fe228cfc4647d6a56e80639b7129b6a)
Jason Ekstrand [Tue, 7 Jun 2016 23:53:19 +0000 (16:53 -0700)]
isl/state: Don't use designated initializers for the surface state
While designated initializers are nice, they also force us to put some
things in the initializer and some things later. Surface state setup is
complicated enough that this really hurts readability in the long run.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
caf2af4181c66df8af31662de22120dcf1d16c7c)
Jason Ekstrand [Fri, 3 Jun 2016 01:43:59 +0000 (18:43 -0700)]
genxml/gen8,9: Prefix the multisample format enum with MSFMT
This is what gen7 does and it's nice to have a prefix
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
de1d194856ddcfc946df2df0f076cb42ff1c165d)
Jason Ekstrand [Sat, 11 Jun 2016 04:11:02 +0000 (21:11 -0700)]
i965/gen4: Subtract 1 from buffer sizes
The PRM states that the values put in Width, Height, and Depth should be
various bits from the value size - 1. We seem to have done this wrong
more-or-less from the start.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
2a1cc94d27c80929d91e38b4843333a5408d563e)
Jason Ekstrand [Tue, 7 Jun 2016 02:15:39 +0000 (19:15 -0700)]
i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
Previously, we were incrementing length but not actually putting anything
in the Y coordinate. This meant that 1-D TXF operations had a garbage
array index. If the surface is emitted as 1-D non-array, the coordinate
gets discarded and it works fine. If it happens to be bound as an array
surface, it may count as an out-of-bounds array access and you get zero.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
0195299c868ec99bc6c595c641da81bb2632252e)
Jason Ekstrand [Sat, 4 Jun 2016 21:32:37 +0000 (14:32 -0700)]
i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
1436238b75e0352439306f120ac1ca03c9fc7df3)
Jason Ekstrand [Sat, 4 Jun 2016 06:25:19 +0000 (23:25 -0700)]
i965/blorp/gen8: Use the correct max level and layer in emit_surface_states
We were adding in the base which is wrong because the values given in the
miptree are relative to zero and not the base layer/level.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
620f81d2edb20ffd9803ee318f60845441459fac)
Jason Ekstrand [Thu, 9 Jun 2016 21:57:33 +0000 (14:57 -0700)]
i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be
set to the depth of a 3-D texture when rendering. Unfortunatley, that
field is only 9 bits on Sandy Bridge and prior so we can't actually bind
a 3-D texturing for rendering if it has depth > 512. On Ivy Bridge, this
field was bumpped to 11 bits so we can go all the way up to 2048. On Iron
Lake and prior, we don't support layered rendering and we use OffsetX/Y
hacks to render to particular layers so 2048 is ok there too.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6ba88bce64b343761aabe3a6c7ee285c6020a959)
Jason Ekstrand [Wed, 22 Jun 2016 18:11:29 +0000 (11:11 -0700)]
i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctly
This is basically a direct translation of what we do for gen7.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
0f9cd74aab021da81a7e5a2f0fbf66213471628f)
Jason Ekstrand [Wed, 22 Jun 2016 04:58:23 +0000 (21:58 -0700)]
i965/gen4: Pull texture formats from the texture object not the miptree
This makes texture views sort-of work. It doesn't add full texture view
support for gen4-5 but it is enough to fix the GL_ARB_copy_image formats
piglit test on Iron Lake.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
ee39d3ba918de9d52d79bdee6db2c120bcf0f28e)
Ilia Mirkin [Tue, 21 Jun 2016 20:16:17 +0000 (16:16 -0400)]
glsl: only match gl_FragData and not gl_SecondaryFragDataEXT
There's special logic around finding gl_FragData. It latches onto any
array with FRAG_RESULT_DATA0. However gl_SecondaryFragDataEXT[], added
by GL_EXT_blend_func_extended, fits those parameters as well. The real
frag data array should have index 0 though, so we can use that to
distinguish them.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96617
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
36ed1b695e5a0ae5714b79cae3a089b5e7e8bd29)
Ilia Mirkin [Sun, 19 Jun 2016 01:54:37 +0000 (21:54 -0400)]
nv50,nvc0: fix start_instance in manual push path
The start instance is applied as an offset into the buffer directly,
ignoring the divisor, not as an instance id offset that respects the
divisor.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
1f4bca798dda155ad0615ba81d8373c771d1ec94)
Ilia Mirkin [Sun, 19 Jun 2016 04:43:06 +0000 (00:43 -0400)]
translate: fix start_instance parameter in sse version
The generic version gets this right already, but this was using an
incorrect formula in SSE.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
5b0d64886dfe9d42d02666ee1b07f2aa375197a5)
Jason Ekstrand [Tue, 21 Jun 2016 22:32:09 +0000 (15:32 -0700)]
anv/cmd: Dirty descriptor sets when a new pipeline is bound
Ever since
c2581a9375ea, the binding table layout has depended on the
pipeline. This means that whenever we change pipelines we also need to
re-emit binding tables for the new layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
35b53c8d47d3a0b53ee2549d73296d5db8e3cca0)
Jason Ekstrand [Tue, 21 Jun 2016 22:31:14 +0000 (15:31 -0700)]
anv/cmd: Move emit_descriptor_pointers to genX_cmd_buffer.c
It's tiny and fully generic so there's really no reason for it to be in a
gen7-specific file.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
2bfe0c33748b9fd96d48cb93656b6dc643bf024e)
Jason Ekstrand [Tue, 21 Jun 2016 22:28:15 +0000 (15:28 -0700)]
anv/cmd: Move flush_descriptor_sets to anv_cmd_buffer.c
There's no good reason for recompiling it
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
9df4d6bb36268d5dd248b872611e3787de9608be)
Jason Ekstrand [Tue, 21 Jun 2016 06:41:11 +0000 (23:41 -0700)]
spirv: Use the system value version of gl_FrontFace
SPIR-V treats it as an input but NIR wants the system value. This
shouldn't have been too much of a surprise given that we have to do the
same conversion in the GLSL IR to NIR pass.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
295e03c980a7ff6dde77abcb6bbfa2f8d015323b)
Kenneth Graunke [Tue, 14 Jun 2016 06:09:31 +0000 (23:09 -0700)]
i965: Reorganize prog_data->total_scratch code a bit.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
40013c50333caf7a4a66204ac29695aad0d9b06d)
Emil Velikov [Tue, 21 Jun 2016 12:32:04 +0000 (13:32 +0100)]
Update version to 12.0.0-rc4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Nicolai Hähnle [Fri, 10 Jun 2016 13:59:58 +0000 (15:59 +0200)]
st/mesa: flush bitmap cache before CopyImageSubData
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
f9ddd52317caf14a21ec7c040fd4bb944f9842e4)
Nicolai Hähnle [Thu, 9 Jun 2016 10:22:31 +0000 (12:22 +0200)]
st/mesa: flush bitmap cache before texture functions
As far as I can tell, a sequence of glBitmap followed by texture functions
that refer to a texture bound as the framebuffer is well within what should
be allowed.
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
e7fff3cfe156e13198107e5e76a77fb79ed02173)
Nicolai Hähnle [Thu, 9 Jun 2016 10:12:34 +0000 (12:12 +0200)]
st/mesa: flush bitmap cache before compute dispatch
In the unlikely case that a program uses glBitmap to render to a framebuffer
whose texture is bound in a compute shader.
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
c542b7e43d3a504456518c9f407e21c4e7e5fa88)
Kenneth Graunke [Wed, 8 Jun 2016 23:09:02 +0000 (16:09 -0700)]
i965: Fix multiplication of immediates on Cherryview/Broxton.
Cherryview and Broxton don't support DW x DW multiplication. We have
piles of code to handle this, but apparently weren't retyping in the
immediate case.
For example,
tests/spec/arb_tessellation_shader/execution/dvec3-vs-tcs-tes
makes the simulator angry about instructions such as:
mul(8) r18<1>:D r10.0<8;8,1>:D 0x00000003:D
Just retype to W or UW. It should be safe on all platforms.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
cd89c834a8b3b4e5f5874c8e1f90c9b01d541181)
Jason Ekstrand [Tue, 14 Jun 2016 15:40:49 +0000 (08:40 -0700)]
anv: Add proper support for depth clamping
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
eb6764c4a73006eee32e19e3afc6eab100a2ce16)
Jason Ekstrand [Tue, 14 Jun 2016 15:15:34 +0000 (08:15 -0700)]
anv/cmd_buffer: Split emit_viewport in two
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
8a46b505cb2c7255ad430b56c1ce0dfa9c13c559)
Jason Ekstrand [Tue, 14 Jun 2016 00:09:37 +0000 (17:09 -0700)]
anv/cmd_buffer: Set depth/stencil extent based on the image
It used to be based on the framebuffer which isn't quite right.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
20e95a746df34923eb4aac5e7f1ab6d722432d89)
Jason Ekstrand [Wed, 15 Jun 2016 21:30:33 +0000 (14:30 -0700)]
anv/cmd_buffer: Don't crash if push constants are provided for missing stages
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b65f2e4163c9180e6a022c0afec018b08e4c5aa5)
Jason Ekstrand [Thu, 16 Jun 2016 17:57:39 +0000 (10:57 -0700)]
anv/pipeline: Do invariance propagation on SPIR-V shaders
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
e6c2fe451962e364f30f689dc48c34e2b6161b25)
Jason Ekstrand [Mon, 13 Jun 2016 21:41:05 +0000 (14:41 -0700)]
nir/alu_to_scalar: Respect the exact ALU operation qualifier
Just setting builder->exact isn't sufficient because that only applies to
instructions that are built with the builder but instructions created
manually and only inserted using the builder are left alone.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
bec07b729242f6a2dcf5a12ce75bf8b07ea658e0)
Jason Ekstrand [Mon, 13 Jun 2016 19:47:19 +0000 (12:47 -0700)]
nir: Add a pass for propagating invariant decorations
This pass is similar to propagate_invariance in the GLSL compiler. The
real "output" of this pass is that any algebraic operations which are
eventually consumed by an invariant variable get marked as "exact".
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
202751fbb7e3d35c1aa84f325f862245dab67f6c)
Jason Ekstrand [Sat, 18 Jun 2016 19:30:36 +0000 (12:30 -0700)]
nir/algebraic: Remove imprecise flog2 optimizations
While mathematically correct, these two optimizations result in an
expression with substantially lower precision than the original. For any
positive finite floating-point value, log2(x) is well-defined and finite.
More precisely, it is in the range [-150, 150] so any sum of logarithms
log2(a) + log2(b) is also well-defined and finite as long as a and b are
both positive and finite. However, if a and b are either very small or
very large, their product may get flushed to infinity or zero causing
log2(a * b) to be nowhere close to log2(a) + log2(b).
This imprecision was causing incorrect rendering in Talos Principal because
part of its HDR rendering process involves doing 8 texture operations,
clamping the result to [0, 65000], taking a dot-product with a constant,
and then taking the log2. This is done 6 or 8 times and summed to produce
the final result which is written to a red texture. In cases where you
have a region of the screen that is very dark, it can end up getting a
result value of -inf which is not what is intended.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96425
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
68e308d85355079ad93bd4e16cba164784740fdf)
Nicolai Hähnle [Fri, 17 Jun 2016 08:48:53 +0000 (10:48 +0200)]
radeonsi: fix calculation of valid RB mask per SE
The old calculation treated too many RBs as disabled.
Cc: 11.0 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
c95175581e983642dc4b23d059e6eaff5b79d2db)
Nicolai Hähnle [Fri, 17 Jun 2016 08:30:44 +0000 (10:30 +0200)]
radeonsi: raise SI_PM4_MAX_DW
The old limit, introduced in commit
afa752d3f03ac6697581ff5d324e8ac0512ef513,
was exceeded by 4 SE configurations which hit si_write_harvested_raster_configs.
Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
6c2e63698290d3ea868eefcc3e4dd51dc1e16c64)
Roland Scheidegger [Sun, 19 Jun 2016 01:56:11 +0000 (03:56 +0200)]
gallivm: don't use integer min/max sse intrinsics with llvm >= 3.9
Apparently, these are deprecated. There's some AutoUpgrade feature which
is supposed to promote these to cmp/select, which apparently doesn't work
with jit code. It is possible it's not actually even meant to work (see
the bug filed against llvm which couldn't provide an answer neither)
but in any case this is meant to be only temporary unless the intrinsics
are really illegal. So, just use the fallback code (which should be cmp/select,
we're actually doing cmp/sext/trunc/select, but in any case llvm 3.9 manages
to optimize this back to pmin/pmax in the end).
This addresses https://llvm.org/bugs/show_bug.cgi?id=28176
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Aaron Watry <awatry@gmail.com>
(cherry picked from commit
b0cf99165af445adc4c5c1f66a3a3e0d882211cd)
Ilia Mirkin [Sun, 19 Jun 2016 04:28:36 +0000 (00:28 -0400)]
nvc0: don't make use of push hint if there are no non-const user vbos
This makes the check match up what we do on nv50 as well - there's no
point in switching over the push path if everything's in managed
buffers. This can happen when a shader uses a vertex without an enabled
array - we end up passing it a constant attribute.
This also has the effect of "fixing" some flickering in Talos. I have no
idea why. I've stared at the push logic forwards, backwards, and
sideways. By always forcing the push path (which is slow), the
flickering also goes away, but other rendering is still wrong
(specifically draw 383068 as identified in the bug). However by not
switching over to the push path, draw 383068 is correct.
Note that other flickering remains in Talos, like the red/green
walls/floors. This takes care of the shadow flickering though.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90513
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
154c0a42a23187c61ea0a1307198fae667398eba)
Ilia Mirkin [Sat, 18 Jun 2016 19:22:09 +0000 (15:22 -0400)]
gk104/ir: fix tex use generation to be more careful about eliding uses
If we have a loop, instructions before the tex might be added as tex
uses, and those may in fact dominate all other uses of the tex results.
This however doesn't mean that we don't need a texbar after the tex.
Only check if uses dominate each other they are dominated by the tex.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96565
Fixes:
7752bbc44 (gk104/ir: simplify and fool-proof texbar algorithm)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
1804aa0b80cf5b1ee5d97bc33a12808c78673a12)
Samuel Iglesias Gonsálvez [Mon, 13 Jun 2016 06:29:53 +0000 (08:29 +0200)]
i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT
From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region
Restrictions, page 844:
"When source or destination datatype is 64b or operation is integer DWord
multiply, indirect addressing must not be used."
v2:
- Fix it for Broxton too.
v3:
- Simplify code by using subscript() and not creating a new num_components
variable (Kenneth).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
bdab572a86f27b92ba10124f85d278e9c8861fff)
Iago Toral Quiroga [Mon, 13 Jun 2016 07:13:23 +0000 (03:13 -0400)]
i965/fs: Fix single-precision to double-precision conversions for CHV/BSW/BXT
From the Cherryview PRM, Volume 7, 3D Media GPGPU Engine,
Register Region Restrictions:
"When source or destination is 64b (...), regioning in Align1
must follow these rules:
1. Source and destination horizontal stride must be aligned to
the same qword.
(...)"
v2:
- Fix it for Broxton too.
v3:
- Remove inst->regs_written change as it is not necessary (Ken)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
0177dbb6c2fe876a9761a4a97eec44accfa4c007)
Ian Romanick [Mon, 13 Jun 2016 16:59:10 +0000 (09:59 -0700)]
mesa: If validation fails in a debug context just emit a debug message
There are quite a few pipelines that desktop applications (including a
bunch of piglit test) can expect to have run but don't meet the GLES
requirements. Instead of failing validation, just emit a debug message.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
6bec55a780b0e95445c6d77c6e35cc0c74290ac0)
Ian Romanick [Mon, 13 Jun 2016 22:22:34 +0000 (15:22 -0700)]
glsl: Always strip arrayness in precision_qualifier_allowed
Previously some callers of precision_qualifier_allowed would strip the
arrayness from the type and some would not. As a result, some places
would not notice that float[6], for example, needed a precision
qualifier.
Fixes the new piglit test no-default-float-array-precision.frag.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
9c872820413f6183db0eb47828a7afcf703f9930)
Kenneth Graunke [Wed, 1 Jun 2016 07:08:55 +0000 (00:08 -0700)]
i965: Use a uniform for gl_PatchVerticesIn in the TCS on Gen8+.
We still need to recompile the passthrough shader when this value
changes, as it also affects the output vertex count. But otherwise,
we can eliminate recompiles on Gen8+.
We probably want to do this for Gen7 as well, but that requires
rewriting the input release code to use a loop, which is a trade-off
I'd need to consider in more detail.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
c319512e16f19bf1f558670981bbb4af510ba9f4)
Kenneth Graunke [Fri, 27 May 2016 03:21:58 +0000 (20:21 -0700)]
glsl: Optionally lower TCS gl_PatchVerticesIn to a uniform.
i965 has no special hardware for this, so the best way to implement
this is to pass it in via a uniform.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
2b867264d2cce59bd65bd3599ff0e3c5439bc9d4)
Kenneth Graunke [Wed, 1 Jun 2016 07:08:55 +0000 (00:08 -0700)]
i965: Use a uniform for gl_PatchVerticesIn in the TES.
Fixes three GL44-CTS.tessellation_shader subtests:
- max_patch_vertices
- single.max_patch_vertices
- tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn
These use gl_PatchVerticesIn in the TES, but don't link against a
TCS (which would allow the linker to lower it to a constant). We had
no handling for the system value in the backend, so it would just
assert fail.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
1bc194cd64085d07f1aae319cb6fb3c99d69aaeb)
Kenneth Graunke [Fri, 27 May 2016 03:21:58 +0000 (20:21 -0700)]
glsl: Optionally lower TES gl_PatchVerticesIn to a uniform.
i965 has no special hardware for this, so we need to pass this value in
as a uniform (unless the TES is linked against a TCS, in which case the
linker can just replace this with a constant).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
0be210513797d3a0245588df915b9510c201bea4)
Nicolai Hähnle [Fri, 13 May 2016 06:48:04 +0000 (01:48 -0500)]
mesa/main: fix integer overflows in _mesa_image_offset
Found using -fsanitize=undefined.
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit
6510e0734563ff8d30e45b8781153367db15cc5b)
Kenneth Graunke [Fri, 27 May 2016 02:56:48 +0000 (19:56 -0700)]
mesa: Pass gl_constant_value union into _mesa_fetch_state().
We've had some trouble in the past with copying integers around via
float pointers, as the C compiler sometimes uses x87 floating point
registers to load values on 32-bit systems. Passing the
gl_constant_value union should be safer.
To avoid churn, this patch creates a "GLfloat *value" variable so
existing uses can stay the same.
Not observed to fix anything, but I was in the area adding more integer
state vars, and thought it'd be wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
8b408972ff5476f1e23ad24a329f89442e6df054)
Emil Velikov [Wed, 15 Jun 2016 08:21:11 +0000 (09:21 +0100)]
Update version to 12.0.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Nicolai Hähnle [Tue, 14 Jun 2016 16:00:13 +0000 (18:00 +0200)]
radeonsi: mark buffer texture range valid for shader images
When a shader image view into a buffer texture can be written to, the buffer's
valid range must be updated, or subsequent transfers may incorrectly skip
synchronization.
This fixes a bug that was exposed in Xephyr by PBO acceleration for glReadPixels,
reported by Michel Dänzer.
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
a64c7cd2bac33a3a2bf908b5ef538dff03b93b73)
Back-ported from commit
a64c7cd2bac33a3a2bf908b5ef538dff03b93b73:
- include util/u_format.h
- code was extracted to si_set_shader_image in master, move it back
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
--
src/gallium/drivers/radeonsi/si_descriptors.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
Ilia Mirkin [Sat, 28 May 2016 18:23:35 +0000 (14:23 -0400)]
nv50/ir: record number of threads in a compute shader
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
27a51ff9b420909334898785cf194b5998776e88)
Ilia Mirkin [Sat, 28 May 2016 18:28:07 +0000 (14:28 -0400)]
nvc0/ir: limit max number of regs based on availability in SM
This effectively limits registers to 32 and 64 for fermi and kepler when
1024 threads are used, but allows the full amount to be used with
smaller thread sizes.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
1f895caba0accc0af3e637d6193ac0b673ce98bc)
Tomasz Figa [Mon, 13 Jun 2016 10:53:21 +0000 (19:53 +0900)]
i965: Check return value of screen->image.loader->getBuffers (v2)
The images struct is an uninitialized local variable on the stack. If the
callback returns 0, the struct might not have been updated and so should
be considered uninitialized. Currently the code ignores the return value,
which (depending on stack contents) might end up in reading a non-zero
value from images.image_mask and dereferencing further fields.
Another solution would be to initialize image_mask with 0, but checking
the return value seems more sensible and it is what Gallium is doing.
v2: fix typos in commit message,
fix indentation,
remove unnecessary parentheses and pointer dereference to keep line
length reasonable.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
e7ab358e8186dd8651cf920d4db1500c60ccd2fc)
Dylan Baker [Mon, 13 Jun 2016 18:19:18 +0000 (11:19 -0700)]
isl: Replace bash generator with python generator
This replaces the current bash generator with a python based generator
using mako. It's quite fast and works with both python 2.7 and python
3.5, and should work with 3.3+ and maybe even 3.2.
It produces an almost identical file except for a minor layout changes,
and the addition of a "generated file, do not edit" warning.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
5a87bc718197deab7577a028c64a7f591bbfaec4)
Bas Nieuwenhuizen [Mon, 6 Jun 2016 20:49:57 +0000 (22:49 +0200)]
radeonsi: Reinitialize all descriptors in CE preamble.
This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.
To illustrate suppose we have two graphics IB's 1 and 2, which are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.
The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.
Fix this by always restoring the entire CE RAM.
v2: - Just load all descriptor set buffers instead of load and store the entire
CE RAM.
- Leave the ce_ram_dirty tracking in place for the non-preamble case.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Note: This commit differs from the one in master -
54f755fa0fd
("radeonsi: Reinitialize all descriptors in CE preamble.")
Emil Velikov [Tue, 14 Jun 2016 14:52:41 +0000 (15:52 +0100)]
cherry-ignore: drop the "i965 bring back INTEL_PRECISE_TRIG"
The commit that removes it isn't in branch, thus there's nothing to do
here.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Samuel Iglesias Gonsálvez [Thu, 9 Jun 2016 11:03:59 +0000 (13:03 +0200)]
i965: Defeat the register stride checker in pull uniform messages.
Pulling DF uniforms from pull constant buffer generates messages like:
send(4) g12<1>DF g12<0,1,0>F
sampler ld SIMD4x2 Surface = 1 Sampler = 0 mlen 1 rlen 1
which produces GPU hangs in Cherryview/Braswell:
"For 64-bit Align1 operation or multiplication of dwords in CHV,
source horizontal stride must be aligned to qword."
This seems to be documented in the Cherryview PRM, Volume 7, Page 843:
"When source or destination datatype is 64b or operation is integer
DWord multiply, regioning in Align1 must follow these rules:
1. Source and Destination horizontal stride must be aligned to the
same qword."
We should set the destination type to UD, D, or F so that
the register stride checker doesn't notice. The destination type of
send messages is basically irrelevant anyway.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
a0ed8503b753574b14df3dc280fd917ae7c207f8)
Kenneth Graunke [Wed, 8 Jun 2016 23:24:50 +0000 (16:24 -0700)]
i965: Defeat the register stride checker in URB reads.
Pulling DF inputs from the URB generates messages like:
send(8) g23<1>DF g1<8,8,1>UD
urb 3 SIMD8 read mlen 1 rlen 2 { align1 1Q };
which makes the simulator angry:
"For 64-bit Align1 operation or multiplication of dwords in CHV,
source horizontal stride must be aligned to qword."
This seems to be documented in the Cherryview PRM, Volume 7, Page 823:
"When source or destination datatype is 64b or operation is integer
DWord multiply, regioning in Align1 must follow these rules:
1. Source and Destination horizontal stride must be aligned to the
same qword."
Setting the source horizontal stride to QWord is insane, as it's the
message header containing 8 URB handles in a single 32-bit DWord.
Instead, we should whack the destination type to UD, D, or F so that
the register stride checker doesn't notice. The destination type of
send messages is basically irrelevant anyway.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
ed3ba651f6faa4ea94dde16fa880781090785477)
Kenneth Graunke [Wed, 8 Jun 2016 22:55:18 +0000 (15:55 -0700)]
i965: Fix issues with number of VS URB entries on Cherryview/Broxton.
Cherryview/Broxton annoyingly have a minimum number of VS URB entries
of 34, which is not a multiple of 8. When the VS size is less than 9,
the number of VS entries has to be a multiple of 8.
Notably, BLORP programmed the minimum number of VS URB entries (34), with
a size of 1 (less than 9), which is invalid.
It seemed like this could be a problem in the regular URB code as well,
so I went ahead and updated that to be safe.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
9f37df06dafbf54cec6749543cac1baa77d0b5e2)
Timothy Arceri [Tue, 14 Jun 2016 00:13:41 +0000 (10:13 +1000)]
glsl: make sure UBO arrays are sized in ES
This check was removed in
5b2675093e86 add it back in.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
https://bugs.freedesktop.org/show_bug.cgi?id=96349
(cherry picked from commit
b010fa85675b98962426fe8961466fbae2d25499)
Vedran Miletić [Mon, 6 Jun 2016 10:43:33 +0000 (12:43 +0200)]
clover: Update OpenCL version string to match OpenGL
Change MESA into Mesa in CL_PLATFORM_VERSION and CL_DEVICE_VERSION. For
both, always append git version suffix from git_sha1.h.
v5: move semicolon to same line as MESA_GIT_SHA1.
v4: drop #ifdef guards.
v3: add missing include.
v2: change CL_DEVICE_VERSION as well.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit
4825264f75c83576f251290547f121f066b46a70)
Squashed with commit
clover: Include generated sources in AM_CPPFLAGS
git_sha1.c is generated in $(top_builddir)/src.
Fixes out-of-tree builds since
4825264f75c83576.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96516
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit
fafe026dbe0680c971bf3ba2452954eea84287f2)
Francisco Jerez [Sat, 11 Jun 2016 00:55:39 +0000 (17:55 -0700)]
i965/fs: Fix regs_written for SIMD-lowered instructions some more.
ISTR having suggested this during review of the recent FP64 changes to
the SIMD lowering pass, but it doesn't look like it was taken into
account in the end. Using the fs_reg::component_size helper instead
of this open-coded variant makes sure that the stride is taken into
account correctly. Fixes at least the following piglit tests with
spilling forced on (since otherwise regs_written would be calculated
incorrectly and the spilling code would be rather confused about how
much data needs to be spilled):
spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-shader
spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-mixed-shader
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
bd9f9726519fad94e88b9266b0c255aa00251f4d)