OSDN Git Service
Richard Henderson [Sat, 5 Sep 2020 19:37:36 +0000 (12:37 -0700)]
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
This is saturating add and subtract, signed and unsigned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 5 Sep 2020 19:30:17 +0000 (12:30 -0700)]
tcg/arm: Implement TCG_TARGET_HAS_mul_vec
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 5 Sep 2020 19:24:28 +0000 (12:24 -0700)]
tcg/arm: Implement TCG_TARGET_HAS_shi_vec
This consists of the three immediate shifts: shli, shri, sari.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 5 Sep 2020 18:58:47 +0000 (11:58 -0700)]
tcg/arm: Implement andc, orc, abs, neg, not vector operations
These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 5 Sep 2020 22:54:33 +0000 (15:54 -0700)]
tcg/arm: Implement minimal vector operations
Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 5 Sep 2020 07:03:27 +0000 (00:03 -0700)]
tcg/arm: Implement tcg_out_dup*_vec
Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 3 May 2021 23:48:07 +0000 (16:48 -0700)]
tcg/arm: Implement tcg_out_mov for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 3 May 2021 23:48:03 +0000 (16:48 -0700)]
tcg/arm: Implement tcg_out_ld/st for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 3 May 2021 23:47:52 +0000 (16:47 -0700)]
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 3 May 2021 23:47:37 +0000 (16:47 -0700)]
tcg: Change parameters for tcg_target_const_match
Change the return value to bool, because that's what is should
have been from the start. Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.
Change the value argument to int64_t. We will need the extra
width for 32-bit hosts wanting to match vector constants.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 4 Jun 2021 12:38:48 +0000 (13:38 +0100)]
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging
# gpg: Signature made Fri 04 Jun 2021 08:26:16 BST
# gpg: using RSA key
EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* remotes/jasowang/tags/net-pull-request:
MAINTAINERS: Added eBPF maintainers information.
docs: Added eBPF documentation.
virtio-net: Added eBPF RSS to virtio-net.
ebpf: Added eBPF RSS loader.
ebpf: Added eBPF RSS program.
net: Added SetSteeringEBPF method for NetClientState.
net/tap: Added TUNSETSTEERINGEBPF code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 4 Jun 2021 09:04:11 +0000 (10:04 +0100)]
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fpu-
20210603' into staging
Finish conversion of float128 and floatx80 to FloatParts.
Implement float128_muladd and float128_{min,max}*.
Optimize int-to-float conversion with hard-float.
# gpg: Signature made Thu 03 Jun 2021 22:13:10 BST
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-fpu-
20210603: (29 commits)
softfloat: Use hard-float for {u}int64_to_float{32,64}
tests/fp: Enable more tests
softfloat: Convert modrem operations to FloatParts
softfloat: Move floatN_log2 to softfloat-parts.c.inc
softfloat: Convert float32_exp2 to FloatParts
softfloat: Convert floatx80 compare to FloatParts
softfloat: Convert floatx80_scalbn to FloatParts
softfloat: Convert floatx80 to integer to FloatParts
softfloat: Convert floatx80 float conversions to FloatParts
softfloat: Convert integer to floatx80 to FloatParts
softfloat: Convert floatx80_round_to_int to FloatParts
softfloat: Convert floatx80_round to FloatParts
softfloat: Convert floatx80_sqrt to FloatParts
softfloat: Convert floatx80_div to FloatParts
softfloat: Convert floatx80_mul to FloatParts
softfloat: Convert floatx80_add/sub to FloatParts
tests/fp/fp-test: Reverse order of floatx80 precision tests
softfloat: Adjust parts_uncanon_normal for floatx80
softfloat: Introduce Floatx80RoundPrec
softfloat: Reduce FloatFmt
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Andrew Melnychenko [Fri, 14 May 2021 11:48:35 +0000 (14:48 +0300)]
MAINTAINERS: Added eBPF maintainers information.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:34 +0000 (14:48 +0300)]
docs: Added eBPF documentation.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:33 +0000 (14:48 +0300)]
virtio-net: Added eBPF RSS to virtio-net.
When RSS is enabled the device tries to load the eBPF program
to select RX virtqueue in the TUN. If eBPF can be loaded
the RSS will function also with vhost (works with kernel 5.8 and later).
Software RSS is used as a fallback with vhost=off when eBPF can't be loaded
or when hash population requested by the guest.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:32 +0000 (14:48 +0300)]
ebpf: Added eBPF RSS loader.
Added function that loads RSS eBPF program.
Added stub functions for RSS eBPF loader.
Added meson and configuration options.
By default, eBPF feature enabled if libbpf is present in the build system.
libbpf checked in configuration shell script and meson script.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:31 +0000 (14:48 +0300)]
ebpf: Added eBPF RSS program.
RSS program and Makefile to build it.
The bpftool used to generate '.h' file.
The data in that file may be loaded by libbpf.
EBPF compilation is not required for building qemu.
You can use Makefile if you need to regenerate rss.bpf.skeleton.h.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:30 +0000 (14:48 +0300)]
net: Added SetSteeringEBPF method for NetClientState.
For now, that method supported only by Linux TAP.
Linux TAP uses TUNSETSTEERINGEBPF ioctl.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Andrew Melnychenko [Fri, 14 May 2021 11:48:29 +0000 (14:48 +0300)]
net/tap: Added TUNSETSTEERINGEBPF code.
Additional code that will be used for eBPF setting steering routine.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Richard Henderson [Sun, 16 May 2021 14:52:52 +0000 (09:52 -0500)]
softfloat: Use hard-float for {u}int64_to_float{32,64}
For the normal case of no additional scaling, this reduces the
profile contribution of int64_to_float64 to the testcase in the
linked issue from 0.81% to 0.04%.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/134
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alex Bennée [Wed, 12 May 2021 00:47:49 +0000 (19:47 -0500)]
tests/fp: Enable more tests
Fix the trivial typo in extF80_lt_quiet, and re-enable
all of the floatx80 tests that are now fixed.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <87bl9iyahr.fsf@linaro.org>
[rth: Squash the fix for lt_quiet, and enable that too.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 8 May 2021 01:40:28 +0000 (18:40 -0700)]
softfloat: Convert modrem operations to FloatParts
Rename to parts$N_modrem. This was the last use of a lot
of the legacy infrastructure, so remove it as required.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 18:42:22 +0000 (10:42 -0800)]
softfloat: Move floatN_log2 to softfloat-parts.c.inc
Rename to parts$N_log2. Though this is partly a ruse, since I do not
believe the code will succeed for float128 without work. Which is ok
for now, because we do not need this for more than float32 and float64.
Since berkeley-testfloat-3 doesn't support log2, compare float64_log2
vs the system log2. Fix the errors for inputs near 1.0:
test:
3ff00000000000b0 +0x1.00000000000b0p+0
sf:
3d2fa00000000000 +0x1.fa00000000000p-45
libm:
3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45
Error in fraction:
32170028290927 ulp
test:
3feec24f6770b100 +0x1.ec24f6770b100p-1
sf:
bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5
libm:
bfad3740d13c9e98 -0x1.d3740d13c9e98p-5
Error in fraction: 40 ulp
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 03:20:23 +0000 (19:20 -0800)]
softfloat: Convert float32_exp2 to FloatParts
Keep the intermediate results in FloatParts instead of
converting back and forth between float64. Use muladd
instead of separate mul+add.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 02:34:39 +0000 (18:34 -0800)]
softfloat: Convert floatx80 compare to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 02:32:06 +0000 (18:32 -0800)]
softfloat: Convert floatx80_scalbn to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 02:13:10 +0000 (18:13 -0800)]
softfloat: Convert floatx80 to integer to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 02:02:23 +0000 (18:02 -0800)]
softfloat: Convert floatx80 float conversions to FloatParts
This is the last use of commonNaNT and all of the routines
that use it, so remove all of them for Werror.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 01:40:25 +0000 (17:40 -0800)]
softfloat: Convert integer to floatx80 to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 21:06:18 +0000 (13:06 -0800)]
softfloat: Convert floatx80_round_to_int to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 20:51:14 +0000 (12:51 -0800)]
softfloat: Convert floatx80_round to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 02:27:24 +0000 (18:27 -0800)]
softfloat: Convert floatx80_sqrt to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 20:44:47 +0000 (12:44 -0800)]
softfloat: Convert floatx80_div to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 20:42:02 +0000 (12:42 -0800)]
softfloat: Convert floatx80_mul to FloatParts
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 00:40:57 +0000 (16:40 -0800)]
softfloat: Convert floatx80_add/sub to FloatParts
Since this is the first such, this includes all of the
packing and unpacking routines as well.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 01:32:01 +0000 (17:32 -0800)]
tests/fp/fp-test: Reverse order of floatx80 precision tests
Many qemu softfloat will check floatx80_rounding_precision
even when berkeley testfloat will not. So begin with
floatx80_precision_x, so that's the one we use
when !FUNC_EFF_ROUNDINGPRECISION.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 22 Nov 2020 00:35:54 +0000 (16:35 -0800)]
softfloat: Adjust parts_uncanon_normal for floatx80
With floatx80_precision_x, the rounding happens across
the break between words. Notice this case with
frac_lsb = round_mask + 1 -> 0
and check the bits in frac_hi as needed.
In addition, since frac_shift == 0, we won't implicitly clear
round_mask via the right-shift, so explicitly clear those bits.
This fixes rounding for floatx80_precision_[sd].
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 17:33:36 +0000 (09:33 -0800)]
softfloat: Introduce Floatx80RoundPrec
Use an enumeration instead of raw 32/64/80 values.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 21 Nov 2020 02:28:31 +0000 (18:28 -0800)]
softfloat: Reduce FloatFmt
Remove frac_lsb, frac_lsbm1, roundeven_mask. Compute
these from round_mask in parts$N_uncanon_normal.
With floatx80, round_mask will not be tied to frac_shift.
Everything else is easily computable.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 20 Nov 2020 20:11:08 +0000 (12:11 -0800)]
softfloat: Split out parts_uncanon_normal
We will need to treat the non-normal cases of floatx80 specially,
so split out the normal case that we can reuse.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Nov 2020 20:14:37 +0000 (12:14 -0800)]
softfloat: Move sqrt_float to softfloat-parts.c.inc
Rename to parts$N_sqrt.
Reimplement float128_sqrt with FloatParts128.
Reimplement with the inverse sqrt newton-raphson algorithm from musl.
This is significantly faster than even the berkeley sqrt n-r algorithm,
because it does not use division instructions, only multiplication.
Ordinarily, changing algorithms at the same time as migrating code is
a bad idea, but this is the only way I found that didn't break one of
the routines at the same time.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 15 Nov 2020 04:28:02 +0000 (20:28 -0800)]
softfloat: Move scalbn_decomposed to softfloat-parts.c.inc
Rename to parts$N_scalbn.
Reimplement float128_scalbn with FloatParts128.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 15 Nov 2020 03:20:36 +0000 (19:20 -0800)]
softfloat: Move compare_floats to softfloat-parts.c.inc
Rename to parts$N_compare. Rename all of the intermediate
functions to ftype_do_compare. Rename the hard-float functions
to ftype_hs_compare. Convert float128 to FloatParts128.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
David Hildenbrand [Mon, 17 May 2021 14:27:36 +0000 (16:27 +0200)]
softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag)
The float128 implementation is straight-forward.
Unfortuantely, we don't have any tests we can simply adjust/unlock.
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <
20210517142739.38597-24-david@redhat.com>
[rth: Update for changed parts_minmax return value]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 15 Nov 2020 00:52:38 +0000 (16:52 -0800)]
softfloat: Move minmax_flags to softfloat-parts.c.inc
Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask.
Introduce ftype_minmax functions as a common optimization point.
Fold bfloat16 expansions into the same macro as the other types.
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 14 Nov 2020 22:48:31 +0000 (14:48 -0800)]
softfloat: Move uint_to_float to softfloat-parts.c.inc
Rename to parts$N_uint_to_float.
Reimplement uint64_to_float128 with FloatParts128.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 14 Nov 2020 22:40:27 +0000 (14:40 -0800)]
softfloat: Move int_to_float to softfloat-parts.c.inc
Rename to parts$N_sint_to_float.
Reimplement int{32,64}_to_float128 with FloatParts128.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 14 Nov 2020 22:21:16 +0000 (14:21 -0800)]
softfloat: Move round_to_uint_and_pack to softfloat-parts.c.inc
Rename to parts$N_float_to_uint. Reimplement
float128_to_uint{32,64}{_round_to_zero} with FloatParts128.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Thu, 3 Jun 2021 15:59:46 +0000 (16:59 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210603' into staging
target-arm queue:
* Some not-yet-enabled preliminaries for M-profile MVE support
* Consistently use "Cortex-Axx", not "Cortex Axx" in docs, comments
* docs: Fix installation of man pages with Sphinx 4.x
* Mark LDS{MIN,MAX} as signed operations
* Fix missing syndrome value for DAIF and PAC check exceptions
* Implement BFloat16 extensions
* Refactoring of hvf accelerator code in preparation for aarch64 support
* Fix some coverity nits in test code
# gpg: Signature made Thu 03 Jun 2021 16:58:02 BST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210603: (45 commits)
tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed
tests/qtest/tpm-tests: Remove unnecessary NULL checks
tests/qtest/pflash-cfi02-test: Avoid potential integer overflow
tests/qtest/hd-geo-test: Fix checks on mkstemp() return value
tests/qtest/e1000e-test: Check qemu_recv() succeeded
tests/qtest/bios-tables-test: Check for dup2() failure
hvf: Simplify post reset/init/loadvm hooks
hvf: Introduce hvf vcpu struct
hvf: Remove hvf-accel-ops.h
hvf: Make synchronize functions static
hvf: Use cpu_synchronize_state()
hvf: Split out common code on vcpu init and destroy
hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t
hvf: Make hvf_set_phys_mem() static
hvf: Move hvf internal definitions into common header
hvf: Move cpu functions into common directory
hvf: Move vcpu thread functions into common directory
hvf: Move assert_hvf_ok() into common directory
target/arm: Enable BFloat16 extensions
linux-user/aarch64: Enable hwcap bits for bfloat16
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 25 May 2021 13:44:58 +0000 (14:44 +0100)]
tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed
Coverity complains that we don't check for failures from dup()
and mkstemp(); add asserts that these syscalls succeeded.
Fixes: Coverity CID
1432516,
1432574
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210525134458.6675-7-peter.maydell@linaro.org
Peter Maydell [Tue, 25 May 2021 13:44:57 +0000 (14:44 +0100)]
tests/qtest/tpm-tests: Remove unnecessary NULL checks
Coverity points out that in tpm_test_swtpm_migration_test() we
assume that src_tpm_addr and dst_tpm_addr are non-NULL (we
pass them to tpm_util_migration_start_qemu() which will
unconditionally dereference them) but then later explicitly
check them for NULL. Remove the pointless checks.
Fixes: Coverity CID
1432367,
1432359
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20210525134458.6675-6-peter.maydell@linaro.org
Peter Maydell [Tue, 25 May 2021 13:44:56 +0000 (14:44 +0100)]
tests/qtest/pflash-cfi02-test: Avoid potential integer overflow
Coverity points out that we calculate a 64-bit value using 32-bit
arithmetic; add the cast to force the multiply to be done as 64-bits.
(The overflow will never happen with the current test data.)
Fixes: Coverity CID
1432320
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20210525134458.6675-5-peter.maydell@linaro.org
Peter Maydell [Tue, 25 May 2021 13:44:55 +0000 (14:44 +0100)]
tests/qtest/hd-geo-test: Fix checks on mkstemp() return value
Coverity notices that the checks against mkstemp() failing in
create_qcow2_with_mbr() are wrong: mkstemp returns -1 on failure but
the check is just "g_assert(fd)". Fix to use "g_assert(fd >= 0)",
matching the correct check in create_test_img().
Fixes: Coverity CID
1432274
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20210525134458.6675-4-peter.maydell@linaro.org
Peter Maydell [Tue, 25 May 2021 13:44:54 +0000 (14:44 +0100)]
tests/qtest/e1000e-test: Check qemu_recv() succeeded
The e1000e_send_verify() test calls qemu_recv() but doesn't
check that the call succeeded, which annoys Coverity. Add
an explicit test check for the length of the data.
(This is a test check, not a "we assume this syscall always
succeeds", so we use g_assert_cmpint() rather than g_assert().)
Fixes: Coverity CID
1432324
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20210525134458.6675-3-peter.maydell@linaro.org
Peter Maydell [Tue, 25 May 2021 13:44:53 +0000 (14:44 +0100)]
tests/qtest/bios-tables-test: Check for dup2() failure
Coverity notes that we don't check for dup2() failing. Add some
assertions so that if it does ever happen we get some indication.
(This is similar to how we handle other "don't expect this syscall to
fail" checks in this test code.)
Fixes: Coverity CID
1432346
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20210525134458.6675-2-peter.maydell@linaro.org
Alexander Graf [Thu, 3 Jun 2021 13:42:41 +0000 (14:42 +0100)]
hvf: Simplify post reset/init/loadvm hooks
The hooks we have that call us after reset, init and loadvm really all
just want to say "The reference of all register state is in the QEMU
vcpu struct, please push it".
We already have a working pushing mechanism though called cpu->vcpu_dirty,
so we can just reuse that for all of the above, syncing state properly the
next time we actually execute a vCPU.
This fixes PSCI resets on ARM, as they modify CPU state even after the
post init call has completed, but before we execute the vCPU again.
To also make the scheme work for x86, we have to make sure we don't
move stale eflags into our env when the vcpu state is dirty.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-13-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:34 +0000 (14:09 +0100)]
hvf: Introduce hvf vcpu struct
We will need more than a single field for hvf going forward. To keep
the global vcpu struct uncluttered, let's allocate a special hvf vcpu
struct, similar to how hax does it.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-12-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:33 +0000 (14:09 +0100)]
hvf: Remove hvf-accel-ops.h
We can move the definition of hvf_vcpu_exec() into our internal
hvf header, obsoleting the need for hvf-accel-ops.h.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-11-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:33 +0000 (14:09 +0100)]
hvf: Make synchronize functions static
The hvf accel synchronize functions are only used as input for local
callback functions, so we can make them static.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-10-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:33 +0000 (14:09 +0100)]
hvf: Use cpu_synchronize_state()
There is no reason to call the hvf specific hvf_cpu_synchronize_state()
when we can just use the generic cpu_synchronize_state() instead. This
allows us to have less dependency on internal function definitions and
allows us to make hvf_cpu_synchronize_state() static.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-9-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:32 +0000 (14:09 +0100)]
hvf: Split out common code on vcpu init and destroy
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch splits the vcpu init and destroy functions into a generic and
an architecture specific portion. This also allows us to move the generic
functions into the generic hvf code, removing exported functions.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-8-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:32 +0000 (14:09 +0100)]
hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t
The ARM version of Hypervisor.framework no longer defines these two
types, so let's just revert to standard ones.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-7-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:32 +0000 (14:09 +0100)]
hvf: Make hvf_set_phys_mem() static
The hvf_set_phys_mem() function is only called within the same file.
Make it static.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-6-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:31 +0000 (14:09 +0100)]
hvf: Move hvf internal definitions into common header
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves a few internal struct and constant defines over.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-5-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:31 +0000 (14:09 +0100)]
hvf: Move cpu functions into common directory
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves CPU and memory operations over. While at it, make sure
the code is consumable on non-i386 systems.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-4-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:31 +0000 (14:09 +0100)]
hvf: Move vcpu thread functions into common directory
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves the vCPU thread loop over.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-3-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 3 Jun 2021 13:09:30 +0000 (14:09 +0100)]
hvf: Move assert_hvf_ok() into common directory
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves assert_hvf_ok() and introduces generic build infrastructure.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210519202253.76782-2-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:17 +0000 (15:58 -0700)]
target/arm: Enable BFloat16 extensions
Disable BF16 again for !have_neon and !have_vfp during realize.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:16 +0000 (15:58 -0700)]
linux-user/aarch64: Enable hwcap bits for bfloat16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:15 +0000 (15:58 -0700)]
target/arm: Implement bfloat widening fma (indexed)
This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE,
and VFMA{B,T}.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:14 +0000 (15:58 -0700)]
target/arm: Implement bfloat widening fma (vector)
This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE,
and VFMA{B,T}.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:13 +0000 (15:58 -0700)]
target/arm: Implement bfloat16 matrix multiply accumulate
This is BFMMLA for both AArch64 AdvSIMD and SVE,
and VMMLA.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:12 +0000 (15:58 -0700)]
target/arm: Implement bfloat16 dot product (indexed)
This is BFDOT for both AArch64 AdvSIMD and SVE,
and VDOT.BF16 for AArch32 NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:11 +0000 (15:58 -0700)]
target/arm: Implement bfloat16 dot product (vector)
This is BFDOT for both AArch64 AdvSIMD and SVE,
and VDOT.BF16 for AArch32 NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:10 +0000 (15:58 -0700)]
softfpu: Add float_round_to_odd_inf
For Arm BFDOT and BFMMLA, we need a version of round-to-odd
that overflows to infinity, instead of the max normal number.
Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:09 +0000 (15:58 -0700)]
target/arm: Implement vector float32 to bfloat16 conversion
This is BFCVT{N,T} for both AArch64 AdvSIMD and SVE,
and VCVT.BF16.F32 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:08 +0000 (15:58 -0700)]
target/arm: Implement scalar float32 to bfloat16 conversion
This is the 64-bit BFCVT and the 32-bit VCVT{B,T}.BF16.F32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:07 +0000 (15:58 -0700)]
target/arm: Unify unallocated path in disas_fp_1src
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 25 May 2021 22:58:06 +0000 (15:58 -0700)]
target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16
Note that the SVE BFLOAT16 support does not require SVE2,
it is an independent extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210525225817.400336-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jamie Iles [Wed, 26 May 2021 12:18:47 +0000 (13:18 +0100)]
target/arm: use raise_exception_ra for stack limit exception
The sequence cpu_restore_state() + raise_exception() is equivalent to
raise_exception_ra(), so use that instead. (In this case we never
cared about the syndrome value, because M-profile doesn't use the
syndrome; the old code was just written unnecessarily awkwardly.)
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: Retain edited version of comment; rewrite commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jamie Iles [Wed, 26 May 2021 12:18:46 +0000 (13:18 +0100)]
target/arm: use raise_exception_ra for MTE check failure
Now that raise_exception_ra restores the state before raising the
exception we can use restore_exception_ra to perform the state restore +
exception raising without clobbering the syndrome.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: Keep the one line of the comment that is still relevant]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jamie Iles [Wed, 26 May 2021 12:18:45 +0000 (13:18 +0100)]
target/arm: fold do_raise_exception into raise_exception
Now that there are no other users of do_raise_exception, fold it into
raise_exception.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jamie Iles [Wed, 26 May 2021 12:18:44 +0000 (13:18 +0100)]
target/arm: fix missing exception class
The DAIF and PAC checks used raise_exception_ra to raise an exception
and unwind CPU state but raise_exception_ra is currently designed for
handling data aborts as the syndrome is partially precomputed and
encoded in the TB and then merged in merge_syn_data_abort when handling
the data abort. Using raise_exception_ra for DAIF and PAC checks
results in an empty syndrome being retrieved from data[2] in
restore_state_to_opc and setting ESR to 0. This manifested as:
kvm [571]: Unknown exception class: esr: 0x000000 –
Unknown/Uncategorized
when launching a KVM guest when the host qemu used a CPU supporting
EL2+pointer authentication and enabling pointer authentication in the
guest.
Rework raise_exception_ra such that the state is restored before raising
the exception so that the exception is not clobbered by
restore_state_to_opc.
Fixes:
0d43e1a2d29a ("target/arm: Add PAuth helpers")
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: added comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 2 Jun 2021 02:07:20 +0000 (19:07 -0700)]
target/arm: Mark LDS{MIN,MAX} as signed operations
The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must
be signed, so that the inputs are properly extended.
Zero extend the result afterward, as needed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20210602020720.47679-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Damien Goutte-Gattat [Mon, 3 May 2021 16:14:22 +0000 (17:14 +0100)]
docs: Fix installation of man pages with Sphinx 4.x
The 4.x branch of Sphinx introduces a breaking change, as generated man
pages are now written to subdirectories corresponding to the manual
section they belong to. This results in `make install` erroring out when
attempting to install the man pages, because they are not where it
expects to find them.
This patch restores the behavior of Sphinx 3.x regarding man pages.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/256
Signed-off-by: Damien Goutte-Gattat <dgouttegattat@incenp.org>
Message-id:
20210503161422.15028-1-dgouttegattat@incenp.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 27 May 2021 09:51:52 +0000 (10:51 +0100)]
arm: Consistently use "Cortex-Axx", not "Cortex Axx"
The official punctuation for Arm CPU names uses a hyphen, like
"Cortex-A9". We mostly follow this, but in a few places usage
without the hyphen has crept in. Fix those so we consistently
use the same way of writing the CPU name.
This commit was created with:
git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20210527095152.10968-1-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:40 +0000 (16:28 +0100)]
target/arm: Allow board models to specify initial NS VTOR
Currently we allow board models to specify the initial value of the
Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M
object which is plumbed through to the CPU. Allow board models to
also specify the initial value of the Non-secure VTOR via a similar
init-nsvtor property.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-10-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:38 +0000 (16:28 +0100)]
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-8-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:37 +0000 (16:28 +0100)]
target/arm: Implement M-profile VPR register
If MVE is implemented for an M-profile CPU then it has a VPR
register, which tracks predication information.
Implement the read and write handling of this register, and
the migration of its state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-7-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:36 +0000 (16:28 +0100)]
target/arm: Fix return values in fp_sysreg_checks()
The fp_sysreg_checks() function is supposed to be returning an
FPSysRegCheckResult, which is an enum with three possible values.
However, three places in the function "return false" (a hangover from
a previous iteration of the design where the function just returned a
bool). Make these return FPSysRegCheckFailed instead (for no
functional change, since both false and FPSysRegCheckFailed are
zero).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-6-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:35 +0000 (16:28 +0100)]
target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp
Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can
permit the insns if either FP or MVE are present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-5-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:34 +0000 (16:28 +0100)]
target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp
The do_vfp_2op_sp() and do_vfp_2op_dp() functions currently check
whether floating point is supported via the aa32_fpdp_v2 and
aa32_fpsp_v2 isar checks. For v8.1M MVE support, the VMOV_reg trans
functions (but not any of the others) need to update this to also
allow the insn if MVE is implemented. Move the check out of the do_
function and into its callsites (which are all implemented via the
DO_VFP_2OP macro), so we have a place to change the check for the
VMOV insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-4-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:33 +0000 (16:28 +0100)]
target/arm: Update feature checks for insns which are "MVE or FP"
Some v8M instructions are present if either the floating point
extension or MVE is implemented. Update our implementation of them
to check for MVE as well as for FP.
This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or
CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are
essentially the loads and stores, moves and sysreg accesses, except
for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent
patches because they need a refactor to provide a place to put the
new MVE check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-3-peter.maydell@linaro.org
Peter Maydell [Thu, 20 May 2021 15:28:32 +0000 (16:28 +0100)]
target/arm: Add isar feature check functions for MVE
Add the isar feature check functions we will need for v8.1M MVE:
* a check for MVE present: this corresponds to the pseudocode's
CheckDecodeFaults(ExtType_Mve)
* a check for the optional floating-point part of MVE: this
corresponds to CheckDecodeFaults(ExtType_MveFp)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210520152840.24453-2-peter.maydell@linaro.org
Peter Maydell [Thu, 3 Jun 2021 09:00:35 +0000 (10:00 +0100)]
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-
20210603' into staging
ppc patch queue 2021-06-03
Next batch of ppc target patches. Highlights are:
* A fix for a regression with single-step mode
* Start of moving ppc to use decodetree
* Implementation of some POWER10 64-bit prefixed instructions
* Several cleanups to softmmu code
* Continued progress towards allowing --disable-tcg
* Fix for the POWER PEF implementation
* Fix for LPCR handling of hotplugged CPUs
* Assorted other bugfixes and cleanups
This patchset does contain a couple of changes to code outside my
normal scope of maintainership, related to the removal of cpu_dump and
cpu_statistics hooks. ppc was the last target arch implementing these
at all, and they didn't really do anything there either. The patches
should have relevant acks.
# gpg: Signature made Thu 03 Jun 2021 09:20:59 BST
# gpg: using RSA key
75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dg-gitlab/tags/ppc-for-6.1-
20210603: (42 commits)
target/ppc: fix single-step exception regression
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
target/ppc: Move addpcis to decodetree
target/ppc: Implement vcfuged instruction
target/ppc: Implement cfuged instruction
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
target/ppc: Implement prefixed integer store instructions
target/ppc: Move D/DS/X-form integer stores to decodetree
target/ppc: Implement prefixed integer load instructions
target/ppc: Move D/DS/X-form integer loads to decodetree
target/ppc: Implement PNOP
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
target/ppc: Add infrastructure for prefixed insns
target/ppc: Move page crossing check to ppc_tr_translate_insn
target/ppc: Introduce macros to check isa extensions
target/ppc: powerpc_excp: Consolidade TLB miss code
target/ppc: powerpc_excp: Remove dump_syscall_vectored
target/ppc: powerpc_excp: Move lpes code to where it is used
target/ppc: overhauled and moved logic of storing fpscr
target/ppc: removed all mentions to PPC_DUMP_CPU
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Luis Pires [Wed, 2 Jun 2021 12:51:03 +0000 (09:51 -0300)]
target/ppc: fix single-step exception regression
Commit
6086c75 (target/ppc: Replace POWERPC_EXCP_BRANCH with
DISAS_NORETURN) broke the generation of exceptions when
CPU_SINGLE_STEP or CPU_BRANCH_STEP were set, due to nip always being
reset to the address of the current instruction.
This fix leaves nip untouched when generating the exception.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reported-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <
20210602125103.332793-1-luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Tue, 1 Jun 2021 19:35:28 +0000 (16:35 -0300)]
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The
Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the
instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the
L bit [1]. The stricter behavior, however, can help users that test
software with qemu, making it more likely to detect bugs that would
otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on
the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states
that the L bit is ignored, but we also observe this behavior in a 7447A
v1.2.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <
20210601193528.
2533031-15-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[dwg: Corrected whitespace error]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Tue, 1 Jun 2021 19:35:27 +0000 (16:35 -0300)]
target/ppc: Move addpcis to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <
20210601193528.
2533031-14-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Tue, 1 Jun 2021 19:35:26 +0000 (16:35 -0300)]
target/ppc: Implement vcfuged instruction
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <
20210601193528.
2533031-13-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Tue, 1 Jun 2021 19:35:25 +0000 (16:35 -0300)]
target/ppc: Implement cfuged instruction
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <
20210601193528.
2533031-12-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>