OSDN Git Service
Mark Searles [Tue, 30 Jan 2018 17:17:06 +0000 (17:17 +0000)]
[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output."
Patch caused a buildbot failure; arg; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17373/s\
teps/build_Lld/logs/stdio :
/Users/buildslave/as-bldslv9/lld-x86_64-darwin13/llvm.src/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:1563:18: error: unused variable 'InstCnt' [-Werror,-Wunused-variable]
static int32_t InstCnt = 0;
"
This reverts commit
4f4a7d61e306b67044d9f16bc2016fee806bc2cc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323791
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Zachary Turner [Tue, 30 Jan 2018 17:12:04 +0000 (17:12 +0000)]
[CodeView] Micro-optimizations to speed up type merging.
Based on a profile, a couple of hot spots were identified in the
main type merging loop. The code was simplified, a few loops
were re-arranged, and some outlined functions were inlined. This
speeds up type merging by a decent amount, shaving around 3-4 seconds
off of a 40 second link in my test case.
Differential Revision: https://reviews.llvm.org/D42559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323790
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Mark Searles [Tue, 30 Jan 2018 16:49:38 +0000 (16:49 +0000)]
[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output.
-amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs
This patch was pushed (
abb190fd51cd2f9a9eef08c024e109f7f7e909fc ), which caused a buildbot failure, reverted (
6227480d74da507cf8e1b4bcaffbdb9fb875b4b8 ), and then updated to fix buildbot failures (this patch).
Differential Revision: https://reviews.llvm.org/D40091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323788
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Changpeng Fang [Tue, 30 Jan 2018 16:42:40 +0000 (16:42 +0000)]
AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace.
Reviewer:
Dmitry (dp).
Differential Revision:
https://reviews.llvm.org/D42596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323785
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Petar Jovanovic [Tue, 30 Jan 2018 16:42:04 +0000 (16:42 +0000)]
[DeadArgumentElimination] Preserve llvm.dbg.values's first argument
When removing return value Dead Argument Elimination pass clobbers first
llvm.dbg.value’s argument for live arguments of that function by replacing
it with nullptr. In the next pass it will be deleted, so debug location
about those arguments are lost. This change fixes it.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D42541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323784
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Saleem Abdulrasool [Tue, 30 Jan 2018 16:29:29 +0000 (16:29 +0000)]
CodeGen: support an extension to pass linker options on ELF
Introduce an extension to support passing linker options to the linker.
These would be ignored by older linkers, but newer linkers which support
this feature would be able to process the linker.
Emit a special discarded section `.linker-option`. The content of this
section is a pair of strings (key, value). The key is a type identifier for
the parameter. This allows for an argument free parameter that will be
processed by the linker with the value being the parameter. As an example,
`lib` identifies a library to be linked against, traditionally the `-l`
argument for Unix-based linkers with the parameter being the library name.
Thanks to James Henderson, Cary Coutant, Rafael Espinolda, Sean Silva
for the valuable discussion on the design of this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323783
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Evandro Menezes [Tue, 30 Jan 2018 16:28:01 +0000 (16:28 +0000)]
[AArch64] Add new target feature to fuse address generation with load or store
This feature enables the fusion of the address generation and a
corresponding load or store together.
Differential revision: https://reviews.llvm.org/D42393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323782
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Simon Dardis [Tue, 30 Jan 2018 16:24:10 +0000 (16:24 +0000)]
[mips] Fix incorrect sign extension for fpowi libcall
PR36061 showed that during the expansion of ISD::FPOWI, that there
was an incorrect zero extension of the integer argument which for
MIPS64 would then give incorrect results. Address this with the
existing mechanism for correcting sign extensions.
This resolves PR36061.
Thanks to James Cowgill for reporting the issue!
Reviewers: atanasyan, hfinkel
Differential Revision: https://reviews.llvm.org/D42537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323781
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Zaara Syeda [Tue, 30 Jan 2018 16:17:22 +0000 (16:17 +0000)]
Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass to mark
candidates with coldcc attribute.
This recommits r322721 reverted due to sanitizer memory leak build bot failures.
Original commit message:
This patch adds support for the coldcc calling convention for Power.
This changes the set of non-volatile registers. It includes a pass to stress
test the implementation by marking all static directly called functions with
the coldcc attribute through the option -enable-coldcc-stress-test. It also
includes an option, -ppc-enable-coldcc, to add the coldcc attribute to
functions which are cold at all call sites based on BlockFrequencyInfo when
the containing function does not call any non cold functions.
Differential Revision: https://reviews.llvm.org/D38413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323778
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Daniel Sanders [Tue, 30 Jan 2018 16:02:32 +0000 (16:02 +0000)]
Add more initializers to quiet a clang warning
Summary:
`struct crashreporter_annotations_t` gained one more `uint64_t` field in
`CRASHREPORTER_ANNOTATIONS_VERSION` 5
causing an annoying clang warning:
```
llvm/lib/Support/PrettyStackTrace.cpp:92:65: warning: missing field 'abort_cause' initializer [-Wmissing-field-initializers]
= { CRASHREPORTER_ANNOTATIONS_VERSION, 0, 0, 0, 0, 0, 0 };
^
1 warning generated
```
Let's fix it.
Patch by Roman Tereshin
Reviewers: qcolombet, echristo, beanz, dexonsmith
Reviewed By: echristo
Subscribers: dsanders, dexonsmith, beanz, echristo, qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D42268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323777
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Simon Pilgrim [Tue, 30 Jan 2018 16:01:41 +0000 (16:01 +0000)]
[X86][AVX512] Add VBMI target shuffle-trunc tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323776
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Evandro Menezes [Tue, 30 Jan 2018 15:40:27 +0000 (15:40 +0000)]
[AArch64] Update test cases for Exynos M3
Update any test case relevant for Exynos M3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323775
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Evandro Menezes [Tue, 30 Jan 2018 15:40:22 +0000 (15:40 +0000)]
[AArch64] Add new target feature to handle cheap as move for Exynos
This feature enables special handling of cheap as move in the existing
custom handling specifically for Exynos processors.
Differential revision: https://reviews.llvm.org/D42387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323774
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Evandro Menezes [Tue, 30 Jan 2018 15:40:16 +0000 (15:40 +0000)]
[AArch64] Add pipeline model for Exynos M3
Add the scheduling and cost model for Exynos M3.
Differential revision: https://reviews.llvm.org/D42387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323773
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Daniel Neilson [Tue, 30 Jan 2018 14:43:41 +0000 (14:43 +0000)]
[RS4GC] Handle call/invoke instructions as base defining values of vectors
Summary:
There's an asymmetry in the definitions of findBaseDefiningValueOfVector() and
findBaseDefiningValue() of RS4GC. The later handles call and invoke instructions,
and the former does not. This appears to be simple oversight. This patch remedies
the oversight by adding the call and invoke cases to findBaseDefiningValueOfVector().
Reviewers: DaniilSuchkov, anna
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42653
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323764
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Andrei Elovikov [Tue, 30 Jan 2018 14:25:12 +0000 (14:25 +0000)]
[X86FixupBWInsts] mir-simplify fixup-bw-inst.mir test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323762
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Eric Liu [Tue, 30 Jan 2018 14:18:33 +0000 (14:18 +0000)]
Revert "[X86] Avoid using high register trick for test instruction"
This reverts commit r323690. This causes crash in llc. See the original commit thread for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323761
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Simon Pilgrim [Tue, 30 Jan 2018 14:15:51 +0000 (14:15 +0000)]
[X86] Add test case for PR32690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323760
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Sanjay Patel [Tue, 30 Jan 2018 13:53:59 +0000 (13:53 +0000)]
[DSE] make sure memory is not modified before partial store merging (PR36129)
We missed a critical check in D30703. We must make sure that no intermediate
store is sitting between the stores that we want to merge.
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=36129
Differential Revision: https://reviews.llvm.org/D42663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323759
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Martin Pelikan [Tue, 30 Jan 2018 13:41:34 +0000 (13:41 +0000)]
[XRay] clarify error messages when parsing broken traces
Summary:
When there's a mismatch of a function argument being right after the
wrong function, print an offset into the file where that happened, to
ease further debugging.
Reviewers: dberris, eizan, kpw
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323758
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Jonas Devlieghere [Tue, 30 Jan 2018 13:36:30 +0000 (13:36 +0000)]
[AccelTable] Move print methods to implementation. NFC
This patch moves the implementation of the print methods from the header
to the cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323757
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Brock Wyma [Tue, 30 Jan 2018 13:16:50 +0000 (13:16 +0000)]
Test commit.
As per the LLVM Developer Policy under "Obtainiing Commit Access".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323754
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Simon Pilgrim [Tue, 30 Jan 2018 12:18:51 +0000 (12:18 +0000)]
Spelling mistake in comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323752
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Amaury Sechet [Tue, 30 Jan 2018 11:07:36 +0000 (11:07 +0000)]
Change simple-register-allocation-read-undef.mir so that it doesn't fail if the file path contains 'dead' . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323748
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Diana Picus [Tue, 30 Jan 2018 09:15:27 +0000 (09:15 +0000)]
[ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP
These are handled by the TableGen'erated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323732
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Diana Picus [Tue, 30 Jan 2018 09:15:23 +0000 (09:15 +0000)]
[ARM GlobalISel] Map G_SITOFP and G_UITOFP
Straightforward mapping (integer operand to GPR, floating point operand
to FPR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323731
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Diana Picus [Tue, 30 Jan 2018 09:15:17 +0000 (09:15 +0000)]
[ARM GlobalISel] Legalize G_SITOFP and G_UITOFP
Legal if we have hardware support, libcall otherwise.
Also add supporting code to the legalizer helper for libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323730
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Diana Picus [Tue, 30 Jan 2018 07:55:02 +0000 (07:55 +0000)]
[ARM GlobalISel] Add inst selector tests for G_FPTOSI and G_FPTOUI
The work is done by the TableGen'erated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323728
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Diana Picus [Tue, 30 Jan 2018 07:54:58 +0000 (07:54 +0000)]
[ARM GlobalISel] Map G_FPTOSI and G_FPTOUI
Straightforward mapping (integer operand goes to GPR, floating point
operand goes to FPR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323727
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Diana Picus [Tue, 30 Jan 2018 07:54:52 +0000 (07:54 +0000)]
[ARM GlobalISel] Legalize G_FPTOSI and G_FPTOUI
Legal if we have hardware support for floating point, libcalls
otherwise.
Also add the necessary support for libcalls in the legalizer helper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323726
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Craig Topper [Tue, 30 Jan 2018 07:02:29 +0000 (07:02 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323724
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Wolfgang Pieb [Tue, 30 Jan 2018 01:11:46 +0000 (01:11 +0000)]
[DWARF] Corrected test committed in r323670 to use llc instead of llc_dwarf to avoid multiple triples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323721
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Fangrui Song [Tue, 30 Jan 2018 00:40:05 +0000 (00:40 +0000)]
[utils] De-duplicate utils/update_{llc_,}test_checks.py
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323718
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Sanjay Patel [Tue, 30 Jan 2018 00:18:37 +0000 (00:18 +0000)]
[InstSimplify] (X * Y) / Y --> X for relaxed floating-point ops
This is the FP counterpart that was mentioned in PR35709:
https://bugs.llvm.org/show_bug.cgi?id=35709
Differential Revision: https://reviews.llvm.org/D42385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323716
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Dan Gohman [Tue, 30 Jan 2018 00:14:40 +0000 (00:14 +0000)]
[SelectionDAG]: Ignore "returned" in the presence of an implicit sret.
When a function return value can't be directly lowered, such as
returning an i128 on WebAssembly, as indicated by the CanLowerReturn
target hook, SelectionDAGBuilder can translate it to return the
value through a hidden sret-like argument.
If such a function has an argument with the "returned" attribute,
the attribute can't be automatically lowered, because the function
no longer has a normal return value. For now, just discard the
"returned" attribute.
This fixes PR36128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323715
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Daniel Sanders [Mon, 29 Jan 2018 23:47:41 +0000 (23:47 +0000)]
[globalisel][legalizer] Fix a fallthrough case in the unittests debug printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323711
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Quentin Colombet [Mon, 29 Jan 2018 23:42:37 +0000 (23:42 +0000)]
[RAFast] Don't dereference MBB::end
When RAFast sees liveins in on a basic block, it uses that information
to initialize the availability of the registers. The called
method uses an instruction as one of its argument and in the liveins
case, RAFast was dereferencing MBB::begin which can be MBB::end for
empty basic block.
Change the API of definePhysReg to use MachineBasicBlock::iterator
instead of MachineInstr so that we don't dereference an
invalid iterator while making the call.
rdar://problem/
36952401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323710
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Tom Stellard [Mon, 29 Jan 2018 23:29:26 +0000 (23:29 +0000)]
AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
Summary: This is only used by R600.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D37114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323709
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Craig Topper [Mon, 29 Jan 2018 23:27:23 +0000 (23:27 +0000)]
[X86] Use VMOVDQA64 for aligned vXi32 stores.
I meant to do this with the unaligned stores in r322820, but looks like I missed it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323708
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Marek Olsak [Mon, 29 Jan 2018 23:19:10 +0000 (23:19 +0000)]
AMDGPU: Allow a SGPR for the conditional KILL operand
Patch by: Bas Nieuwenhuizen
Just use the _e64 variant if needed. This should be possible as per
def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
> ;
I don't think we can get an immediate for the other operand for which we
need the second 32-bit word.
https://reviews.llvm.org/D42302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323706
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Rafael Espindola [Mon, 29 Jan 2018 22:56:41 +0000 (22:56 +0000)]
Fix some regular expressions in llvm-mode.el.
In some cases it was using "\" unnecessarily. In another case it
needed an additional "\" to properly indicate a numbered sub-match.
Make comment-start buffer-local in llvm-mode.el
llvm-mode was setting comment-start globally. However, it is better
to only set it locally in the current buffer.
Don't use purecopy in llvm-mode.el
There's no reason to use purecopy in llvm-mode.el.
purecopy is only needed for files that are dumped in emacs.
Add a version header to llvm-mode.el
Adding a version header to llvm-mode.el allows it to be installed by
the Emacs package manager. There are not many requirements on the
version number; however it is useful to users to bump it when
something significant changes. Here I've chosen just to start at 1.0.
Patch by Tom Tromey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323705
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Sanjay Patel [Mon, 29 Jan 2018 22:50:08 +0000 (22:50 +0000)]
[DSE] add test for PR36129; NFC
We can miscompile because we're not checking is the memory might
me modified between the seemingly redundant store ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323704
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Matthias Braun [Mon, 29 Jan 2018 22:03:00 +0000 (22:03 +0000)]
LiveInterval: Print weight in print() function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323702
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Paul Robinson [Mon, 29 Jan 2018 22:02:56 +0000 (22:02 +0000)]
Stop tracking .debug_line_str in DWARFUnit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323701
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Craig Topper [Mon, 29 Jan 2018 21:56:48 +0000 (21:56 +0000)]
[X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to match skylake client.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323700
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Brian M. Rzycki [Mon, 29 Jan 2018 21:29:44 +0000 (21:29 +0000)]
[JumpThreading][NFC] Rename LoadInst variables
Summary:
The JumpThreading pass has several locations where to the variable name LI
refers to a LoadInst type. This is confusing and inhibits the ability to use
LI for LoopInfo as a member of the JumpThreading class. Minor formatting
and comments were also altered to reflect this change.
Reviewers: dberlin, kuba, spop, sebpop
Reviewed by: sebpop
Subscribers: sebpop, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D42601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323695
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Simon Pilgrim [Mon, 29 Jan 2018 21:24:31 +0000 (21:24 +0000)]
[X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965)
We currently emit up to 15-byte NOPs on all targets (apart from Silvermont), which stalls performance on some targets with decoders that struggle with 2 or 3 more '66' prefixes.
This patch flags recent AMD targets (btver1/znver1) to still emit 15-byte NOPs and bdver* targets to emit 11-byte NOPs. All other targets now emit 10-byte NOPs apart from SilverMont CPUs which still emit 7-byte NOPS.
Differential Revision: https://reviews.llvm.org/D42616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323693
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Daniel Sanders [Mon, 29 Jan 2018 21:09:12 +0000 (21:09 +0000)]
[ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern
Summary:
Apparently, we missed on constraining register classes of VReg-operands of all the instructions
built from a destination pattern but the root (top-level) one. The issue exposed itself
while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped
into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained,
while nested VTOSIZS (or rather its destination virtual register to be exact) does not.
Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI.
https://bugs.llvm.org/show_bug.cgi?id=35965
rdar://problem/
36886530
Patch by Roman Tereshin
Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan
Reviewed By: dsanders, qcolombet, rovka
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323692
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Paul Robinson [Mon, 29 Jan 2018 20:57:43 +0000 (20:57 +0000)]
[DWARFv5] Re-enable dumping a line table with no CU.
r323476 added support for DW_FORM_line_strp, and incorrectly made that
depend on having a DWARFUnit available. We shouldn't be tracking
.debug_line_str in DWARFUnit after all. After this patch, I can do an
NFC follow up and undo a bunch of the "plumbing" part of r323476.
Differential Revision: https://reviews.llvm.org/D42609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323691
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Amaury Sechet [Mon, 29 Jan 2018 20:54:33 +0000 (20:54 +0000)]
[X86] Avoid using high register trick for test instruction
Summary:
It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger.
The main noteworthy regression I was able to observe was pattern of the type (setcc (trunc (and X, C)), 0) where C is such as it would benefit from the hi register trick. To prevent this, a new pattern is added to materialize such pattern using a 32 bits test. This has the added benefit of working with any constant that is materializable as a 32bits immediate, not just the ones that can leverage the high register trick, as demonstrated by the test case in test-shrink.ll using the constant 2049 .
Reviewers: craig.topper, niravd, spatel, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323690
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Daniel Sanders [Mon, 29 Jan 2018 20:46:16 +0000 (20:46 +0000)]
[globalisel][legalizer] Change identity() to changeTo() to clarify that it changes things. NFC
Prior to committing r323681, we decided to change pick() to identity() since
it wasn't clear from the name what pick() did. However, identity() isn't a very
good name either since it implies that no changes are made. For some reason,
naming it changeTo() didn't occur to me until just after the commit. This
should resolve the lack of clarity that pick() had while still implying that
it changes the MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323689
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Shoaib Meenai [Mon, 29 Jan 2018 20:28:04 +0000 (20:28 +0000)]
[CodeGen] Simplify conditional. NFC
Rafael pointed out that `hasInternalLinkage() || hasPrivateLinkage()` is
equivalent to `hasLocalLinkage()` in post-commit review.
I'm intentionally not updating the comment, partly because I like it
being explicit, and partly because "global symbols with local linkage"
sounds like an oxymoron.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323688
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Amaury Sechet [Mon, 29 Jan 2018 20:22:46 +0000 (20:22 +0000)]
[X86] Add test case to ensure testw is generated when optimizing for size. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323687
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Evandro Menezes [Mon, 29 Jan 2018 20:22:24 +0000 (20:22 +0000)]
[AArch64] Change the filename of the Exynos M1 scheduling defs
After request by Matthias Braun in https://reviews.llvm.org/D42387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323686
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Jun Bum Lim [Mon, 29 Jan 2018 19:56:42 +0000 (19:56 +0000)]
Revert "AArch64: Omit callframe setup/destroy when not necessary"
This reverts commit r322917 due to multiple performance regressions in spec2006
and spec2017. XFAILed llvm/test/CodeGen/AArch64/big-callframe.ll which initially
motivated this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323683
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Daniel Sanders [Mon, 29 Jan 2018 19:54:49 +0000 (19:54 +0000)]
[globalisel][legalizer] Adapt LegalizerInfo to support inter-type dependencies and other things.
Summary:
As discussed in D42244, we have difficulty describing the legality of some
operations. We're not able to specify relationships between types.
For example, declaring the following
setAction({..., 0, s32}, Legal)
setAction({..., 0, s64}, Legal)
setAction({..., 1, s32}, Legal)
setAction({..., 1, s64}, Legal)
currently declares these type combinations as legal:
{s32, s32}
{s64, s32}
{s32, s64}
{s64, s64}
but we currently have no means to say that, for example, {s64, s32} is
not legal. Some operations such as G_INSERT/G_EXTRACT/G_MERGE_VALUES/
G_UNMERGE_VALUES have relationships between the types that are currently
described incorrectly.
Additionally, G_LOAD/G_STORE currently have no means to legalize non-atomics
differently to atomics. The necessary information is in the MMO but we have no
way to use this in the legalizer. Similarly, there is currently no way for the
register type and the memory type to differ so there is no way to cleanly
represent extending-load/truncating-store in a way that can't be broken by
optimizers (resulting in illegal MIR).
It's also difficult to control the legalization strategy. We've added support
for legalizing non-power of 2 types but there's still some hardcoded assumptions
about the strategy. The main one I've noticed is that type0 is always legalized
before type1 which is not a good strategy for `type0 = G_EXTRACT type1, ...` if
you need to widen the container. It will converge on the same result eventually
but it will take a much longer route when legalizing type0 than if you legalize
type1 first.
Lastly, the definition of legality and the legalization strategy is kept
separate which is not ideal. It's helpful to be able to look at a one piece of
code and see both what is legal and the method the legalizer will use to make
illegal MIR more legal.
This patch adds a layer onto the LegalizerInfo (to be removed when all targets
have been migrated) which resolves all these issues.
Here are the rules for shift and division:
for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV})
getActionDefinitions(BinOp)
.legalFor({s32, s64}) // If type0 is s32/s64 then it's Legal
.clampScalar(0, s32, s64) // If type0 is <s32 then WidenScalar to s32
// If type0 is >s64 then NarrowScalar to s64
.widenScalarToPow2(0) // Round type0 scalars up to powers of 2
.unsupported(); // Otherwise, it's unsupported
This describes everything needed to both define legality and describe how to
make illegal things legal.
Here's an example of a complex rule:
getActionDefinitions(G_INSERT)
.unsupportedIf([=](const LegalityQuery &Query) {
// If type0 is smaller than type1 then it's unsupported
return Query.Types[0].getSizeInBits() <= Query.Types[1].getSizeInBits();
})
.legalIf([=](const LegalityQuery &Query) {
// If type0 is s32/s64/p0 and type1 is a power of 2 other than 2 or 4 then it's legal
// We don't need to worry about large type1's because unsupportedIf caught that.
const LLT &Ty0 = Query.Types[0];
const LLT &Ty1 = Query.Types[1];
if (Ty0 != s32 && Ty0 != s64 && Ty0 != p0)
return false;
return isPowerOf2_32(Ty1.getSizeInBits()) &&
(Ty1.getSizeInBits() == 1 || Ty1.getSizeInBits() >= 8);
})
.clampScalar(0, s32, s64)
.widenScalarToPow2(0)
.maxScalarIf(typeInSet(0, {s32}), 1, s16) // If type0 is s32 and type1 is bigger than s16 then NarrowScalar type1 to s16
.maxScalarIf(typeInSet(0, {s64}), 1, s32) // If type0 is s64 and type1 is bigger than s32 then NarrowScalar type1 to s32
.widenScalarToPow2(1) // Round type1 scalars up to powers of 2
.unsupported();
This uses a lambda to say that G_INSERT is unsupported when type0 is bigger than
type1 (in practice, this would be a default rule for G_INSERT). It also uses one
to describe the legal cases. This particular predicate is equivalent to:
.legalFor({{s32, s1}, {s32, s8}, {s32, s16}, {s64, s1}, {s64, s8}, {s64, s16}, {s64, s32}})
In terms of performance, I saw a slight (~6%) performance improvement when
AArch64 was around 30% ported but it's pretty much break even right now.
I'm going to take a look at constexpr as a means to reduce the initialization
cost.
Future work:
* Make it possible for opcodes to share rulesets. There's no need for
G_LSHR/G_ASHR/G_SDIV/G_UDIV to have separate rule and ruleset objects. There's
no technical barrier to this, it just hasn't been done yet.
* Replace the type-index numbers with an enum to get .clampScalar(Type0, s32, s64)
* Better names for things like .maxScalarIf() (clampMaxScalar?) and the vector rules.
* Improve initialization cost using constexpr
Possible future work:
* It's possible to make these rulesets change the MIR directly instead of
returning a description of how to change the MIR. This should remove a little
overhead caused by parsing the description and routing to the right code, but
the real motivation is that it removes the need for LegalizeAction::Custom.
With Custom removed, there's no longer a requirement that Custom legalization
change the opcode to something that's considered legal.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar, volkan, reames, bogner
Reviewed By: bogner
Subscribers: hintonda, bogner, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323681
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Rafael Espindola [Mon, 29 Jan 2018 19:37:27 +0000 (19:37 +0000)]
Improve testcase.
We now test that pic and static produce different results for bar.
The function names were demangled.
The attributes are written inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323680
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Geoff Berry [Mon, 29 Jan 2018 18:57:07 +0000 (18:57 +0000)]
[MachineVerifier] Add check that renamable operands aren't reserved registers.
Summary:
Reviewers: qcolombet, MatzeB
Subscribers: arsenm, sdardis, nhaehnle, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D42449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323676
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Geoff Berry [Mon, 29 Jan 2018 18:47:48 +0000 (18:47 +0000)]
[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs
Summary:
Fix a few places that were modifying code after register
allocation to set the renamable bit correctly to avoid failing the
validation added in D42449.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323675
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Rafael Espindola [Mon, 29 Jan 2018 18:27:30 +0000 (18:27 +0000)]
Move getPlatformFlags to ELFObjectFileBase and simplify.
This removes a few std::error_code results that were ignored on every
call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323674
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Craig Topper [Mon, 29 Jan 2018 17:56:57 +0000 (17:56 +0000)]
[X86] Don't create SHRUNKBLEND when the condition is used by the true or false operand of the vselect.
Fixes PR34592.
Differential Revision: https://reviews.llvm.org/D42628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323672
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Craig Topper [Mon, 29 Jan 2018 17:56:55 +0000 (17:56 +0000)]
[X86] Add test case for pr34592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323671
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Wolfgang Pieb [Mon, 29 Jan 2018 17:49:10 +0000 (17:49 +0000)]
[DWARF] Recommitting a test reverted in r323560. Moved to x86 directory with explicit triple.
ELF support is required for type units.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323670
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Daniel Sanders [Mon, 29 Jan 2018 17:37:29 +0000 (17:37 +0000)]
[globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC
Summary:
The improvements to the LegalizerInfo discussed in D42244 require that
LegalizerInfo::LegalizeAction be available for use in other classes. As such,
it needs to be moved out of LegalizerInfo. This has been done separately to the
next patch to minimize the noise in that patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323669
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Jonas Devlieghere [Mon, 29 Jan 2018 17:28:51 +0000 (17:28 +0000)]
[AccelTable] Workaround for MSVC bug
Microsoft Visual Studio rejects the static constexpr static list of
atoms even though it's valid C++. This provides a workaround to unbreak
the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323667
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Tony Jiang [Mon, 29 Jan 2018 17:02:34 +0000 (17:02 +0000)]
Add myself to CREDITS.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323666
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Amaury Sechet [Mon, 29 Jan 2018 16:13:01 +0000 (16:13 +0000)]
Add test case for truncated and promotion to test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323663
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Alexey Bataev [Mon, 29 Jan 2018 16:08:52 +0000 (16:08 +0000)]
[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.
Reviewers: spatel, RKSimon, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323662
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Alexey Bataev [Mon, 29 Jan 2018 15:56:52 +0000 (15:56 +0000)]
[SLP] Add a test with extract for PR32086, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323661
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Jonas Devlieghere [Mon, 29 Jan 2018 15:23:34 +0000 (15:23 +0000)]
[AccelTable] Try making MSVC happy
MSVC complains that the constexpr "expression did not evaluate to a
constant". Trying to make it happy by adding a `const` specifier as
suggested in https://stackoverflow.com/questions/
37574343.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323659
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Jonas Devlieghere [Mon, 29 Jan 2018 15:07:55 +0000 (15:07 +0000)]
[AccelTable] Fix undefined reference
Fixes the missing reference in AppleAccelTableData by making the method
pure virtual as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323656
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Jonas Devlieghere [Mon, 29 Jan 2018 14:52:50 +0000 (14:52 +0000)]
[dsymutil] Generate Apple accelerator tables
This patch adds support for generating accelerator tables in dsymutil.
This feature was already present in our internal repository but not yet
upstreamed because it requires changes to the Apple accelerator table
implementation.
Differential revision: https://reviews.llvm.org/D42501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323655
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Jonas Devlieghere [Mon, 29 Jan 2018 14:52:41 +0000 (14:52 +0000)]
[NFC] Rename DwarfAccelTable and move header.
This patch renames DwarfAccelTable.{h,cpp} to AccelTable.{h,cpp} and
moves the header to the include dir so it is accessible by the
dsymutil implementation.
Differential revision: https://reviews.llvm.org/D42529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323654
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Jonas Devlieghere [Mon, 29 Jan 2018 14:52:34 +0000 (14:52 +0000)]
[NFC] Refactor Apple Accelerator Tables
This patch refactors the way data is stored in the accelerator table and
makes them truly generic. There have been several attempts to do this in
the past:
- D8215 & D8216: Using a union and partial hardcoding.
- D11805: Using inheritance.
- D42246: Using a callback.
In the end I didn't like either of them, because for some reason or
another parts of it felt hacky or decreased runtime performance. I
didn't want to completely rewrite them as I was hoping that we could
reuse parts for the successor in the DWARF standard. However, it seems
less and less likely that there will be a lot of opportunities for
sharing code and/or an interface.
Originally I choose to template the whole class, because it introduces
no performance overhead compared to the original implementation.
We ended up settling on a hybrid between a templated method and a
virtual call to emit the data. The motivation is that we don't want to
increase code size for a feature that should soon be superseded by the
DWARFv5 accelerator tables. While the code will continue to be used for
compatibility, it won't be on the hot path. Furthermore this does not
regress performance compared to Apple's internal implementation that
already uses virtual calls for this.
A quick summary for why these changes are necessary: dsymutil likes to
reuse the current implementation of the Apple accelerator tables.
However, LLDB expects a slightly different interface than what is
currently emitted. Additionally, in dsymutil we only have offsets and no
actual DIEs.
Although the patch suggests a lot of code has changed, this change is
pretty straightforward:
- We created an abstract class `AppleAccelTableData` to serve as an
interface for the different data classes.
- We created two implementations of this class, one for type tables and
one for everything else. There will be a third one for dsymutil that
takes just the offset.
- We use the supplied class to deduct the atoms for the header which
makes the structure of the table fully self contained, although not
enforced by the interface as was the case for the fully templated
approach.
- We renamed the prefix from DWARF- to Apple- to make space for the
future implementation of .debug_names.
This change is NFC and relies on the existing tests.
Differential revision: https://reviews.llvm.org/D42334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323653
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Dmitry Preobrazhensky [Mon, 29 Jan 2018 14:20:42 +0000 (14:20 +0000)]
[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16
See bugs 36092, 36093:
https://bugs.llvm.org/show_bug.cgi?id=36092
https://bugs.llvm.org/show_bug.cgi?id=36093
Differential Revision: https://reviews.llvm.org/D42583
Reviewers: vpykhtin, artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323651
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Pavel Labath [Mon, 29 Jan 2018 13:53:48 +0000 (13:53 +0000)]
Fix windows test failure caused by r323638
The test was failing because of an incorrect sizeof check in the name
index parsing code. This code was meant to check that we have enough
input to parse the fixed-size part of the dwarf header, which it did by
comparing the input to sizeof(Header). Originally struct Header only
contained the fixed-size part, but during review, we've moved additional
members into it, which rendered the sizeof check invalid.
I resolve this by moving the fixed-size part to a separate struct and
updating the sizeof-expression to use that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323648
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Sander de Smalen [Mon, 29 Jan 2018 13:05:38 +0000 (13:05 +0000)]
[AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code
Summary:
All variants of isLogicalImm[Not](32|64) can be combined into a single templated function, same for printLogicalImm(32|64).
By making it use a template instead, further SVE patches can use it for other data types as well (e.g. 8, 16 bits).
Reviewers: fhahn, rengolin, aadg, echristo, kristof.beyls, samparker
Reviewed By: samparker
Subscribers: aemerson, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D42294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323646
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Mikael Holmen [Mon, 29 Jan 2018 12:37:30 +0000 (12:37 +0000)]
[DebugInfo] Fix fragment offset emission order for symbol locations
Summary:
When emitting the location for a global variable with fragmented debug
expressions, make sure that the offset pieces, which represent
optimized-out parts of the variable, are emitted before their succeeding
fragments' expressions. Previously, if the succeeding fragment's
location was a symbol, the offset piece was emitted after, rather than
before, that symbol's expression. This effectively meant that the symbols
were associated with the wrong parts of the variable.
This fixes PR36085.
Patch by: David Stenberg
Reviewers: aprantl, probinson, dblaikie
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D42527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323644
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Jonas Devlieghere [Mon, 29 Jan 2018 12:10:32 +0000 (12:10 +0000)]
[Sparc] Account for bias in stack readjustment
Summary: This was broken long ago in D12208, which failed to account for
the fact that 64-bit SPARC uses a stack bias of 2047, and it is the
*unbiased* value which should be aligned, not the biased one. This was
seen to be an issue with Rust.
Patch by: jrtc27 (James Clarke)
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: jacob_hansen, JDevlieghere, fhahn, fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D39425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323643
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Pavel Labath [Mon, 29 Jan 2018 11:53:46 +0000 (11:53 +0000)]
Fix build broken by r323641
The call to ScopedPrinter::printNumber with size_t argument was
ambiguous (I think) on 32-bit builds. Explicitly cast to a 64-bit int to
avoid this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323642
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Pavel Labath [Mon, 29 Jan 2018 11:33:17 +0000 (11:33 +0000)]
Refactor dwarfdump -apple-names output
Summary:
This modifies the dwarfdump output to align it with the new .debug_names
dump. It also renames two header fields to match similar fields in the
dwarf5 header.
A couple of tests needed to be updated to match new output. The changes
were fairly straight-forward, although not really automatable.
Reviewers: JDevlieghere, aprantl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323641
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Sjoerd Meijer [Mon, 29 Jan 2018 11:28:06 +0000 (11:28 +0000)]
[ARM] FP16Pat and FullFP16Pat patterns. NFC.
Create and use FP16Pat FullFP16Pat helper patterns to make the difference
explicit.
Differential Revision: https://reviews.llvm.org/D42634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323640
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Pavel Labath [Mon, 29 Jan 2018 11:08:32 +0000 (11:08 +0000)]
[DebugInfo] Basic .debug_names dumping support
Summary:
This commit renames DWARFAcceleratorTable to AppleAcceleratorTable to free up
the first name as an interface for the different accelerator tables.
Then I add a DWARFDebugNames class for the dwarf5 table.
Presently, the only common functionality of the two classes is the dump()
method, because this is the only method that was necessary to implement
dwarfdump -debug-names; and because the rest of the
AppleAcceleratorTable interface does not directly transfer to the dwarf5
tables (the main reason for that is that the present interface assumes
the tables are homogeneous, but the dwarf5 tables can have different
keys associated with each entry).
I expect to make the common interface richer as I add more functionality
to the new class (and invent a way to represent it in generic way).
In terms of sharing the implementation, I found the format of the two
tables sufficiently different to frustrate any attempts to have common
parsing or dumping code, so presently the implementations share just low
level code for formatting dwarf constants.
Reviewers: vleschuk, JDevlieghere, clayborg, aprantl, probinson, echristo, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323638
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Andrei Elovikov [Mon, 29 Jan 2018 09:26:04 +0000 (09:26 +0000)]
[X86FixupBWInsts] Fix miscompilation if sibling sub-register is live.
Summary: The issues was found during D40524.
Reviewers: andrew.w.kaylor, craig.topper, MatzeB
Reviewed By: andrew.w.kaylor
Subscribers: aivchenk, llvm-commits
Differential Revision: https://reviews.llvm.org/D42533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323635
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Oliver Stannard [Mon, 29 Jan 2018 09:18:37 +0000 (09:18 +0000)]
[AArch64] Generate the CASP instruction for 128-bit cmpxchg
The Large System Extension added an atomic compare-and-swap instruction
that operates on a pair of 64-bit registers, which we can use to
implement a 128-bit cmpxchg.
Because i128 is not a legal type for AArch64 we have to do all of the
instruction selection in C++, and the instruction requires even/odd
register pairs, so we have to wrap it in REG_SEQUENCE and EXTRACT_SUBREG
nodes. This is very similar to what we do for 64-bit cmpxchg in the ARM
backend.
Differential revision: https://reviews.llvm.org/D42104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323634
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George Rimar [Mon, 29 Jan 2018 08:03:30 +0000 (08:03 +0000)]
[ThinLTO] - Stop internalizing and drop non-prevailing symbols.
Implementation marks non-prevailing symbols as not live in the summary.
Then them are dropped in backends.
Fixes https://bugs.llvm.org/show_bug.cgi?id=35938
Differential revision: https://reviews.llvm.org/D42107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323633
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Craig Topper [Mon, 29 Jan 2018 07:52:55 +0000 (07:52 +0000)]
[X86] Make foldLogicOfSetCCs work better for vectors pre legal types/operations
Summary:
There's a check in the code to only check getSetCCResultType after LegalOperations or if the type is MVT::i1. But the i1 check is only allowing scalar types through. I think it should check that the scalar type is MVT::i1 so that it will work for vectors.
The changed test already does this combine with AVX512VL where getSetCCResultType returns vXi1. But with avx512f and no VLX getSetCCResultType returns a type matching the width of the input type.
Reviewers: spatel, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323631
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Davide Italiano [Mon, 29 Jan 2018 05:59:55 +0000 (05:59 +0000)]
[CVP] Don't Replace incoming values from unreachable blocks with undef.
This pretty much reverts r322006, except that we keep the test,
because we work around the issue exposed in a different way (a
recursion limit in value tracking). There's still probably some
sequence that exposes this problem, and the proper way to fix that
for somebody who has time is outlined in the code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323630
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Hiroshi Inoue [Mon, 29 Jan 2018 05:17:03 +0000 (05:17 +0000)]
[NFC] fix trivial typos in comments and documents
"to to" -> "to"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323628
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Florian Hahn [Sun, 28 Jan 2018 19:11:49 +0000 (19:11 +0000)]
[InlineCost] Mark functions accessing varargs as not viable.
This prevents functions accessing varargs from being inlined if they
have the alwaysinline attribute.
Reviewers: efriedma, rnk, davide
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D42556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323619
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Jonas Devlieghere [Sun, 28 Jan 2018 11:05:10 +0000 (11:05 +0000)]
[Support] Move DJB hash to support. NFC
This patch moves the DJB hash to support. This is consistent with other
hashing algorithms living there. The hash is used by the DWARF
accelerator tables. We're doing this now because the hashing function is
needed by dsymutil and we don't want to link against libBinaryFormat.
Differential revision: https://reviews.llvm.org/D42594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323616
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Craig Topper [Sun, 28 Jan 2018 07:29:35 +0000 (07:29 +0000)]
[X86] Fix a crash that can occur in combineExtractVectorElt due to not checking the width of a ConstantSDNode before calling getConstantOperandVal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323614
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Craig Topper [Sun, 28 Jan 2018 00:56:30 +0000 (00:56 +0000)]
[X86] Remove VPTESTM/VPTESTNM ISD opcodes. Use isel patterns matching cmpm eq/ne with immallzeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323612
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Craig Topper [Sat, 27 Jan 2018 23:49:14 +0000 (23:49 +0000)]
[X86] Add patterns for using masked vptestnmd for 256-bit vectors without VLX.
We can widen the mask and extract it back down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323610
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Craig Topper [Sat, 27 Jan 2018 23:49:11 +0000 (23:49 +0000)]
[X86] Add test to demonstrate missed opportunity to merge kand into testnm when using 512-bit instruction due to lack of VLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323609
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Justin Bogner [Sat, 27 Jan 2018 23:31:09 +0000 (23:31 +0000)]
Add triples or specify REQUIRES: default_triple to some tests
These were all failing when building the X86 backend but specifying
LLVM_DEFAULT_TARGET_TRIPLE=''.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323608
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Simon Pilgrim [Sat, 27 Jan 2018 22:08:27 +0000 (22:08 +0000)]
[X86][AVX512] Add avx512dq fp2int/int2fp tests (PR31630)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323607
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Craig Topper [Sat, 27 Jan 2018 20:19:09 +0000 (20:19 +0000)]
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
We can use the same input for both operands to get a free compare with zero.
We already use this trick in a couple places where we explicitly create PTESTM with the same input twice. This generalizes it.
I'm hoping to remove the ISD opcodes and move this to isel patterns like we do for scalar cmp/test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323605
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Craig Topper [Sat, 27 Jan 2018 20:19:02 +0000 (20:19 +0000)]
[X86] Remove X86ISD::PCMPGTM/PCMPEQM and instead just use X86ISD::PCMPM and pattern match the immediate value during isel.
Legalization is still biased to turn LT compares in to GT by swapping operands to avoid needing extra isel patterns to commute.
I'm hoping to remove TESTM/TESTNM next and this should simplify that by making EQ/NE more similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323604
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Simon Pilgrim [Sat, 27 Jan 2018 19:49:46 +0000 (19:49 +0000)]
Regenerate test. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323603
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