OSDN Git Service
Mark Cave-Ayland [Wed, 25 May 2022 17:32:32 +0000 (18:32 +0100)]
tests/acpi: virt: update golden masters for VIOT
Differences between disassembled ASL files for VIOT:
+++ /tmp/asl-V69GM1.dsl 2022-05-18 10:22:27.
239796759 +0100
@@ -36,11 +36,11 @@
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
-[044h 0068 4] Endpoint start :
00003000
+[044h 0068 4] Endpoint start :
00001000
[048h 0072 2] PCI Segment start : 0000
[04Ah 0074 2] PCI Segment end : 0000
-[04Ch 0076 2] PCI BDF start : 3000
-[04Eh 0078 2] PCI BDF end : 30FF
+[04Ch 0076 2] PCI BDF start : 1000
+[04Eh 0078 2] PCI BDF end : 10FF
[050h 0080 2] Output node : 0030
[052h 0082 6] Reserved :
000000000000
@@ -48,11 +48,11 @@
[059h 0089 1] Reserved : 00
[05Ah 0090 2] Length : 0018
-[05Ch 0092 4] Endpoint start :
00001000
+[05Ch 0092 4] Endpoint start :
00003000
[060h 0096 2] PCI Segment start : 0000
[062h 0098 2] PCI Segment end : 0000
-[064h 0100 2] PCI BDF start : 1000
-[066h 0102 2] PCI BDF end : 10FF
+[064h 0100 2] PCI BDF start : 3000
+[066h 0102 2] PCI BDF end : 30FF
[068h 0104 2] Output node : 0030
[06Ah 0106 6] Reserved :
000000000000
@@ -62,6 +62,6 @@
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 03 00 30 00 00 00 00 00 00 00 00 00 // ......0.........
0030: 03 00 10 00 00 00 10 00 00 00 00 00 00 00 00 00 // ................
- 0040: 01 00 18 00 00 30 00 00 00 00 00 00 00 30 FF 30 // .....0.......0.0
- 0050: 30 00 00 00 00 00 00 00 01 00 18 00 00 10 00 00 // 0...............
- 0060: 00 00 00 00 00 10 FF 10 30 00 00 00 00 00 00 00 // ........0.......
+ 0040: 01 00 18 00 00 10 00 00 00 00 00 00 00 10 FF 10 // ................
+ 0050: 30 00 00 00 00 00 00 00 01 00 18 00 00 30 00 00 // 0............0..
+ 0060: 00 00 00 00 00 30 FF 30 30 00 00 00 00 00 00 00 // .....0.00.......
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-7-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Wed, 25 May 2022 17:32:31 +0000 (18:32 +0100)]
hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus
This ensures that the VIOT ACPI table output is always stable for a given PCI
topology by ensuring that entries are ordered according to min_bus.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-6-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Wed, 25 May 2022 17:32:30 +0000 (18:32 +0100)]
tests/acpi: virt: allow VIOT acpi table changes
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-5-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Wed, 25 May 2022 17:32:29 +0000 (18:32 +0100)]
hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table
Perform the generation of the VIOT ACPI table in 2 separate passes: the first pass
enumerates all of the PCI host bridges and adds the min_bus and max_bus information
to an array.
Once this is done the VIOT table header is generated using the size of the array
to calculate the node count, which means it is no longer necessary to use a
sub-array to hold the PCI host bridge range information along with viommu_off.
Finally the PCI host bridge array is iterated again to add the required entries
to the final VIOT ACPI table.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Wed, 25 May 2022 17:32:28 +0000 (18:32 +0100)]
hw/acpi/viot: move the individual PCI host bridge entry generation to a new function
Instead of generating each table entry inline, move the individual PCI host bridge
table entry generation to a separate build_pci_host_range() function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Wed, 25 May 2022 17:32:27 +0000 (18:32 +0100)]
hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges()
This is in preparation for separating out the VIOT ACPI table build from the
PCI host bridge numeration.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220525173232.31429-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 13:08:04 +0000 (14:08 +0100)]
hw/cxl: Fix missing write mask for HDM decoder target list registers
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608130804.25795-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Claudio Fontana [Tue, 31 May 2022 11:47:07 +0000 (13:47 +0200)]
pci: fix overflow in snprintf string formatting
the code in pcibus_get_fw_dev_path contained the potential for a
stack buffer overflow of 1 byte, potentially writing to the stack an
extra NUL byte.
This overflow could happen if the PCI slot is >= 0x10000000,
and the PCI function is >= 0x10000000, due to the size parameter
of snprintf being incorrectly calculated in the call:
if (PCI_FUNC(d->devfn))
snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
since the off obtained from a previous call to snprintf is added
instead of subtracted from the total available size of the buffer.
Without the accurate size guard from snprintf, we end up writing in the
worst case:
name (32) + "@" (1) + SLOT (8) + "," (1) + FUNC (8) + term NUL (1) = 51 bytes
In order to provide something more robust, replace all of the code in
pcibus_get_fw_dev_path with a single call to g_strdup_printf,
so there is no need to rely on manual calculations.
Found by compiling QEMU with FORTIFY_SOURCE=3 as the error:
*** buffer overflow detected ***: terminated
Thread 1 "qemu-system-x86" received signal SIGABRT, Aborted.
[Switching to Thread 0x7ffff642c380 (LWP 121307)]
0x00007ffff71ff55c in __pthread_kill_implementation () from /lib64/libc.so.6
(gdb) bt
#0 0x00007ffff71ff55c in __pthread_kill_implementation () at /lib64/libc.so.6
#1 0x00007ffff71ac6f6 in raise () at /lib64/libc.so.6
#2 0x00007ffff7195814 in abort () at /lib64/libc.so.6
#3 0x00007ffff71f279e in __libc_message () at /lib64/libc.so.6
#4 0x00007ffff729767a in __fortify_fail () at /lib64/libc.so.6
#5 0x00007ffff7295c36 in () at /lib64/libc.so.6
#6 0x00007ffff72957f5 in __snprintf_chk () at /lib64/libc.so.6
#7 0x0000555555b1c1fd in pcibus_get_fw_dev_path ()
#8 0x0000555555f2bde4 in qdev_get_fw_dev_path_helper.constprop ()
#9 0x0000555555f2bd86 in qdev_get_fw_dev_path_helper.constprop ()
#10 0x00005555559a6e5d in get_boot_device_path ()
#11 0x00005555559a712c in get_boot_devices_list ()
#12 0x0000555555b1a3d0 in fw_cfg_machine_reset ()
#13 0x0000555555bf4c2d in pc_machine_reset ()
#14 0x0000555555c66988 in qemu_system_reset ()
#15 0x0000555555a6dff6 in qdev_machine_creation_done ()
#16 0x0000555555c79186 in qmp_x_exit_preconfig.part ()
#17 0x0000555555c7b459 in qemu_init ()
#18 0x0000555555960a29 in main ()
Found-by: Dario Faggioli <Dario Faggioli <dfaggioli@suse.com>
Found-by: Martin Liška <martin.liska@suse.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <
20220531114707.18830-1-cfontana@suse.de>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:40 +0000 (15:54 +0100)]
hw/machine: Drop cxl_supported flag as no longer useful
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:39 +0000 (15:54 +0100)]
hw/cxl: Move the CXLState from MachineState to machine type specific state.
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Note the pxb register hookup code runs even if cxl=off in order to detect
pxb_cxl host bridges and fail to start if any are present as they won't
have the control registers available.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:38 +0000 (15:54 +0100)]
tests/acpi: Update q35/CEDT.cxl for new memory addresses.
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:37 +0000 (15:54 +0100)]
pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.
Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.
The bus walking logic is common to all machines so add a utility
function + stub to cxl-host*.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:36 +0000 (15:54 +0100)]
tests/acpi: Allow modification of q35 CXL CEDT table.
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:35 +0000 (15:54 +0100)]
hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:34 +0000 (15:54 +0100)]
hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <
20220608145440.26106-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jonathan Cameron [Wed, 8 Jun 2022 14:54:33 +0000 (15:54 +0100)]
hw/cxl: Make the CXL fixed memory window setup a machine parameter.
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is needed to ensure that there is
a CXLFixedMemoryWindowOptionsList even though the actual
element in the json is never used. Similar to existing
SgxEpcProperties.
Update qemu-options.hx to reflect that this is now a -machine
parameter. The bulk of -M / -machine parameters are documented
under machine, so use that in preference to M.
Update cxl-test and bios-tables-test to reflect new parameters.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Message-Id: <
20220608145440.26106-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:40 +0000 (09:53 -0400)]
x86: acpi-build: do not include hw/isa/isa.h directly
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-36-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:39 +0000 (09:53 -0400)]
tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs
expected move of tmp-tis device description directly under
Device(ISA) node.
for tpm-tis 2.0:
@@ -145,6 +145,189 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Name (_ADR, 0x001F0000) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Device (TPM)
+ {
+ Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
+ Name (_STR, "TPM 2.0 Device") // _STR: Description String
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
...
+ }
@@ -3281,189 +3464,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Method (PCNT, 0, NotSerialized)
{
}
-
- Device (TPM)
- {
- Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
- Name (_STR, "TPM 2.0 Device") // _STR: Description String
- Name (_UID, One) // _UID: Unique ID
- Name (_STA, 0x0F) // _STA: Status
...
- }
for tpm-tis 1.2:
@@ -145,6 +145,188 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Name (_ADR, 0x001F0000) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Device (TPM)
+ {
+ Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
...
+ }
@@ -3281,188 +3463,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Method (PCNT, 0, NotSerialized)
{
}
-
- Device (ISA.TPM)
- {
- Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_STA, 0x0F) // _STA: Status
...
- }
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <
20220608135340.
3304695-35-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:38 +0000 (09:53 -0400)]
acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML
.. and clean up not longer needed conditionals in DSTD build code
tpm-tis AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-34-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:37 +0000 (09:53 -0400)]
acpi: pc/q35: remove not needed 'if' condition on pci bus
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-33-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:36 +0000 (09:53 -0400)]
acpi: pc/q35: tpm-tis: fix TPM device scope
tpm-tis 2.0, is not a PCI device but ISA one, move it
under ISA scope to fix incorrect placement.
Fixes:
24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-32-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:35 +0000 (09:53 -0400)]
tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <
20220608135340.
3304695-31-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:34 +0000 (09:53 -0400)]
tests: acpi: update expected DSDT.pvpanic-isa blob
@@ -145,6 +145,37 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Name (_ADR, 0x001F0000) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Device (PEVT)
+ {
+ Name (_HID, "QEMU0001") // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0505, // Range Minimum
+ 0x0505, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ })
+ OperationRegion (PEOR, SystemIO, 0x0505, One)
+ Field (PEOR, ByteAcc, NoLock, Preserve)
+ {
+ PEPT, 8
+ }
+
+ Name (_STA, 0x0F) // _STA: Status
+ Method (RDPT, 0, NotSerialized)
+ {
+ Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */
+ Return (Local0)
+ }
+
+ Method (WRPT, 1, NotSerialized)
+ {
+ PEPT = Arg0
+ }
+ }
+
Device (KBD)
{
Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
@@ -3246,40 +3277,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
}
}
- Scope (\_SB.PCI0.ISA)
- {
- Device (PEVT)
- {
- Name (_HID, "QEMU0001") // _HID: Hardware ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- IO (Decode16,
- 0x0505, // Range Minimum
- 0x0505, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- })
- OperationRegion (PEOR, SystemIO, 0x0505, One)
- Field (PEOR, ByteAcc, NoLock, Preserve)
- {
- PEPT, 8
- }
-
- Name (_STA, 0x0F) // _STA: Status
- Method (RDPT, 0, NotSerialized)
- {
- Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */
- Return (Local0)
- }
-
- Method (WRPT, 1, NotSerialized)
- {
- PEPT = Arg0
- }
- }
- }
-
Scope (\_SB)
{
Scope (PCI0)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-30-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:33 +0000 (09:53 -0400)]
acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML
.. and clean up not longer needed conditionals in DSTD build code
pvpanic-isa AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-29-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:32 +0000 (09:53 -0400)]
tests: acpi: add pvpanic-isa: testcase
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-28-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:31 +0000 (09:53 -0400)]
tests: acpi: white-lists expected DSDT.pvpanic-isa blob
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-27-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:30 +0000 (09:53 -0400)]
tests: acpi: update expected blobs
@@ -145,6 +145,23 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Name (_ADR, 0x001F0000) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Device (SMC)
+ {
+ Name (_HID, EisaId ("APP0001")) // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0300, // Range Minimum
+ 0x0300, // Range Maximum
+ 0x01, // Alignment
+ 0x20, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ })
+ }
+
Device (KBD)
{
Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
@@ -3246,26 +3263,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
}
}
- Scope (\_SB.PCI0.ISA)
- {
- Device (SMC)
- {
- Name (_HID, EisaId ("APP0001")) // _HID: Hardware ID
- Name (_STA, 0x0B) // _STA: Status
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- IO (Decode16,
- 0x0300, // Range Minimum
- 0x0300, // Range Maximum
- 0x01, // Alignment
- 0x20, // Length
- )
- IRQNoFlags ()
- {6}
- })
- }
- }
-
Scope (\_SB)
{
Scope (PCI0)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-26-imammedo@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:29 +0000 (09:53 -0400)]
acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML
.. and clean up not longer needed conditionals in DSTD build
code. applesmc AML will be fetched and included when ISA bridge
will build its own AML code (incl. attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-25-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:28 +0000 (09:53 -0400)]
tests: acpi: add applesmc testcase
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-24-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:27 +0000 (09:53 -0400)]
tests: acpi: add and white-list DSDT.applesmc expected blob
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-23-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Thu, 9 Jun 2022 11:51:13 +0000 (07:51 -0400)]
tests: acpi: update expected blobs
Expected AML change:
ISA devices under separate _SB.PCI0.ISA scope are moved
directly under Device(ISA) node.
Example from PC machine, and q35 have similar changes:
{
Name (_ADR, 0x00010000) // _ADR: Address
OperationRegion (P40C, PCI_Config, 0x60, 0x04)
- }
- }
-
- Scope (_SB.PCI0.ISA)
- {
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
- Name (_STA, 0x0F) // _STA: Status
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ Device (KBD)
{
- IO (Decode16,
- 0x0060, // Range Minimum
- 0x0060, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IO (Decode16,
- 0x0064, // Range Minimum
- 0x0064, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IRQNoFlags ()
- {1}
- })
- }
-
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
- Name (_STA, 0x0F) // _STA: Status
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- IRQNoFlags ()
- {12}
- })
- }
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- IO (Decode16,
- 0x03F2, // Range Minimum
- 0x03F2, // Range Maximum
- 0x00, // Alignment
- 0x04, // Length
- )
- IO (Decode16,
- 0x03F7, // Range Minimum
- 0x03F7, // Range Maximum
- 0x00, // Alignment
- 0x01, // Length
- )
- IRQNoFlags ()
- {6}
- DMA (Compatibility, NotBusMaster, Transfer8, )
- {2}
- })
- Device (FLPA)
+ Device (MOU)
{
- Name (_ADR, Zero) // _ADR: Address
- Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
- Zero,
- 0x05,
- 0x4F,
- 0x30,
- One,
- 0xAF,
- 0x02,
- 0x25,
- 0x02,
- 0x12,
- 0x1B,
- 0xFF,
- 0x6C,
- 0xF6,
- 0x0F,
- 0x08
+ IRQNoFlags ()
+ {12}
})
}
- Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ Device (FDC0)
{
- /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
- /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
- /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
- })
- }
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
- Device (LPT1)
- {
- Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_STA, 0x0F) // _STA: Status
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
{
- IO (Decode16,
- 0x0378, // Range Minimum
- 0x0378, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {7}
- })
- }
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
- Device (COM1)
- {
- Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_STA, 0x0F) // _STA: Status
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ Device (COM1)
{
- IO (Decode16,
- 0x03F8, // Range Minimum
- 0x03F8, // Range Maximum
- 0x00, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {4}
- })
- }
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ Device (RTC)
{
- IO (Decode16,
- 0x0070, // Range Minimum
- 0x0070, // Range Maximum
- 0x01, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {8}
- })
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
}
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220609115113.
3478093-1-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:25 +0000 (09:53 -0400)]
acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device descriptors
replaces adhoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached
to its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_q35_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prologue/epilogue AML for each enumerated PCI device.
Expected AML change is contextual, where ISA devices are moved from
separately declared _SB.PCI0.ISA scope, directly under Device(ISA)
node.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-21-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:24 +0000 (09:53 -0400)]
acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device descriptors
replaces ad-hoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached to
its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_piix4_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prologue/epilogue AML for each enumerated PCI
device.
Expected AML change is contextual, where ISA devices are moved
from separately declared _SB.PCI0.ISA scope , directly under
Device(ISA) node.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-20-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Thu, 9 Jun 2022 11:48:55 +0000 (07:48 -0400)]
tests: acpi: white-list to be re-factored pc/q35 DSDT
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220609114855.
3477822-1-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:22 +0000 (09:53 -0400)]
q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-18-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:21 +0000 (09:53 -0400)]
acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device descriptors
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-17-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:20 +0000 (09:53 -0400)]
acpi: ich9-smb: add support for AcpiDevAmlIf interface
wire AcpiDevAmlIf interface to build ich9-smb and its slave
devices AML. It will be used by followup patches to switch
from creating AML in ad-hoc way to a more systematic one
that will scan present devices and ask them to provide
their AML code like it's done with ISA devices.
This patch is a partial conversion, as it only fetches
AML from slave devices attached to its I2C bus.
The conversion will be completed when PCI bus is
switched to use AcpiDevAmlIf and build_smb0() could be
dropped.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-16-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:19 +0000 (09:53 -0400)]
tests: acpi: update expected DSDT.ipmismbus blob
expected AML change:
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0,
- AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+ AddressingMode7Bit, "^",
0x00, ResourceProducer, , Exclusive,
)
})
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-15-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:18 +0000 (09:53 -0400)]
ipmi: acpi: use relative path to resource source
smbus-ipmi AML description needs to specify a path to its parent
node in _CRS. The rest of IPMI inplementations (ISA based)
do not need path at all. Instead of passing through a full path
use relative path to point to smbus-ipmi's parent node, it will
let follow up patches to create IPMI device AML in a generic
way instead of current ad-hoc way. (i.e. AML will be generated
the same way it's done for other ISA device, and smbus will be
converted to generate AML for its slave devices the same way
as ISA)
expected AML change:
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0,
- AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+ AddressingMode7Bit, "^",
0x00, ResourceProducer, , Exclusive,
)
})
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-14-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:17 +0000 (09:53 -0400)]
tests: acpi: whitelist DSDT.ipmismbus expected blob
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-13-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:16 +0000 (09:53 -0400)]
tests: acpi: update expected blob DSDT.ipmismbus
basic q35 DSDT with an extra device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0,
AddressingMode7Bit, "\\_SB.PCI0.SMB0",
0x00, ResourceProducer, , Exclusive,
)
})
Name (_IFT, 0x04) // _IFT: IPMI Interface Type
Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-12-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:15 +0000 (09:53 -0400)]
tests: acpi: q35: add test for smbus-ipmi device
expected new device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0,
AddressingMode7Bit, "\\_SB.PCI0.SMB0",
0x00, ResourceProducer, , Exclusive,
)
})
Name (_IFT, 0x04) // _IFT: IPMI Interface Type
Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-11-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:14 +0000 (09:53 -0400)]
tests: acpi: add and whitelist DSDT.ipmismbus expected blob
.. which will be used by follow up smbus-ipmi test-case
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220608135340.
3304695-10-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:13 +0000 (09:53 -0400)]
isa-bus: drop no longer used ISADeviceClass::build_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-9-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:12 +0000 (09:53 -0400)]
acpi: pckbd: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-8-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:11 +0000 (09:53 -0400)]
acpi: mc146818rtc: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-7-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:10 +0000 (09:53 -0400)]
acpi: serial-is: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-6-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:09 +0000 (09:53 -0400)]
acpi: parallel port: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-5-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:08 +0000 (09:53 -0400)]
acpi: fdc-isa: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:07 +0000 (09:53 -0400)]
acpi: make isa_build_aml() support AcpiDevAmlIf interface
To allow incremental conversion from ISADeviceClass::build_aml
to AcpiDevAmlIf, add support for the later without removing
the former. Once conversion is complete, another commit will
drop ISADeviceClass::build_aml related code.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Wed, 8 Jun 2022 13:53:06 +0000 (09:53 -0400)]
acpi: add interface to build device specific AML
There is already ISADeviceClass::build_aml() callback which
builds device specific AML blob for some ISA devices.
To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF
Interface that will provide a more generic callback which
will be used not only for ISA but other devices. It will
allow get rid of some data-mining and ad-hoc AML building,
by asking device(s) to generate its own AML blob like it's
done for ISA devices.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20220608135340.
3304695-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Richard Henderson [Wed, 8 Jun 2022 02:22:18 +0000 (19:22 -0700)]
Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stefanberger/qemu-tpm into staging
Merge tpm 2022/06/07 v1
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEEuBi5yt+QicLVzsZrda1lgCoLQhEFAmKf8HgACgkQda1lgCoL
# QhHx8Qf/QB2z+0B1xKKn8NqrWbZ+FaVlnPu/3hX4kraCY5zAYV9e64kdWhuIKRbM
# 74/KARGMpkme6Y8rUSK6mVeiY+ul+egfVMnKyfhsM1jhAQT/DzSlht/XZzbn3Mg+
# FFXQBMqcvcNWH53q9zi9GJYqH4tcxUku3ejgodU4+SO2wB5S59pS/tD+i5H06Vy5
# Iw1kW6I11gYhJGETxVgb6F2Jfyu6uPWFhIg7eN06XwNExFc45E8GjrpIs2rO78GN
# OzMBjwAG+C+/PU+UZDOd5Zhq5qv+8DcvDQuPXyqksxPcFvouvLghQvQL/h7neMlM
# jOwHS153ay0EAT/t2lZafsBwqKQxvQ==
# =b9Qe
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Jun 2022 05:42:32 PM PDT
# gpg: using RSA key
B818B9CADF9089C2D5CEC66B75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211
* tag 'pull-tpm-2022-06-07-1' of https://github.com/stefanberger/qemu-tpm:
tpm_crb: mark command buffer as dirty on request completion
hw/tpm/tpm_tis_common.c: Assert that locty is in range
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Anthony PERARD [Mon, 11 Apr 2022 14:47:49 +0000 (15:47 +0100)]
tpm_crb: mark command buffer as dirty on request completion
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as started could be ignored and not transfered to the
destination.
Mark the memory region of the command buffer as dirty once a request
is completed.
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id:
20220411144749.47185-1-anthony.perard@citrix.com
Richard Henderson [Mon, 6 Jun 2022 23:16:01 +0000 (16:16 -0700)]
Merge tag 'pull-la-
20220606' of https://gitlab.com/rth7680/qemu into staging
Initial LoongArch support.
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKeiRYdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV85Kgf/buBy5+0y51NKOpTI
# zwFzvuQoWyMwb1nz1ag3i0Sk5fk72zmQI13fwfCgyUZckT165qISa2hohnzl4zVZ
# CO0uZl44makET+uqJn5h2VXSM7Wf+jv0UzbCElVQuEFt0t1bIPbco0pTx/TojBb+
# +YKN4jobvJiLVhD1wDVJqp/2r9gcnX11EWZk+ZC+pIiEqYZpWRcQdEGVh4Ymhig8
# 0LK/8HRSyw0AecX/01hcGWvYCC0ldFicwN69AD42BqM+7WD+3jnV8FJL8qqq766G
# xuCNHz0eDcVgfw9bCEyhFmhgiBFvOXNCtyDOV0qVn7eee9nIrFZcsGyBqeI/T1el
# e7uz8Q==
# =l8TD
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Jun 2022 04:09:10 PM PDT
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-la-
20220606' of https://gitlab.com/rth7680/qemu: (43 commits)
target/loongarch: 'make check-tcg' support
tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
target/loongarch: Add gdb support.
hw/loongarch: Add LoongArch virt power manager support.
hw/loongarch: Add LoongArch load elf function.
hw/loongarch: Add LoongArch ls7a rtc device support
hw/loongarch: Add some devices support for 3A5000.
Enable common virtio pci support for LoongArch
hw/loongarch: Add irq hierarchy for the system
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
hw/loongarch: Add support loongson3 virt machine type.
target/loongarch: Add timer related instructions support.
target/loongarch: Add other core instructions support
target/loongarch: Add TLB instruction support
target/loongarch: Add LoongArch IOCSR instruction
target/loongarch: Add LoongArch CSR instruction
target/loongarch: Add constant timer support
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:33 +0000 (20:43 +0800)]
target/loongarch: 'make check-tcg' support
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220606124333.
2060567-44-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:32 +0000 (20:43 +0800)]
tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-43-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:31 +0000 (20:43 +0800)]
target/loongarch: Add gdb support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-42-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:30 +0000 (20:43 +0800)]
hw/loongarch: Add LoongArch virt power manager support.
This is a placeholder for missing ACPI, and will eventually be replaced.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-41-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:29 +0000 (20:43 +0800)]
hw/loongarch: Add LoongArch load elf function.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-40-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:28 +0000 (20:43 +0800)]
hw/loongarch: Add LoongArch ls7a rtc device support
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-39-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:27 +0000 (20:43 +0800)]
hw/loongarch: Add some devices support for 3A5000.
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-38-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:26 +0000 (20:43 +0800)]
Enable common virtio pci support for LoongArch
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-37-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:25 +0000 (20:43 +0800)]
hw/loongarch: Add irq hierarchy for the system
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-36-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:24 +0000 (20:43 +0800)]
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-35-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:23 +0000 (20:43 +0800)]
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-34-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:22 +0000 (20:43 +0800)]
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-33-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:21 +0000 (20:43 +0800)]
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-32-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:20 +0000 (20:43 +0800)]
hw/loongarch: Add support loongson3 virt machine type.
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emulated.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-31-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:19 +0000 (20:43 +0800)]
target/loongarch: Add timer related instructions support.
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-30-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:18 +0000 (20:43 +0800)]
target/loongarch: Add other core instructions support
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-29-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:17 +0000 (20:43 +0800)]
target/loongarch: Add TLB instruction support
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-28-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:16 +0000 (20:43 +0800)]
target/loongarch: Add LoongArch IOCSR instruction
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-27-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:15 +0000 (20:43 +0800)]
target/loongarch: Add LoongArch CSR instruction
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-26-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:14 +0000 (20:43 +0800)]
target/loongarch: Add constant timer support
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-25-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:13 +0000 (20:43 +0800)]
target/loongarch: Add LoongArch interrupt and exception handle
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-24-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:12 +0000 (20:43 +0800)]
target/loongarch: Add MMU support for LoongArch CPU.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-23-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:11 +0000 (20:43 +0800)]
target/loongarch: Implement qmp_query_cpu_definitions()
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-22-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:10 +0000 (20:43 +0800)]
target/loongarch: Add basic vmstate description of CPU.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-21-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:09 +0000 (20:43 +0800)]
target/loongarch: Add CSRs definition
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-20-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Xiaojuan Yang [Mon, 6 Jun 2022 12:43:08 +0000 (20:43 +0800)]
target/loongarch: Add system emulation introduction
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-19-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:07 +0000 (20:43 +0800)]
target/loongarch: Add target build suport
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220606124333.
2060567-18-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:06 +0000 (20:43 +0800)]
target/loongarch: Add disassembler
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-17-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:05 +0000 (20:43 +0800)]
target/loongarch: Add branch instruction translation
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-16-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:04 +0000 (20:43 +0800)]
target/loongarch: Add floating point load/store instruction translation
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-15-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:03 +0000 (20:43 +0800)]
target/loongarch: Add floating point move instruction translation
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-14-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:02 +0000 (20:43 +0800)]
target/loongarch: Add floating point conversion instruction translation
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-13-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:01 +0000 (20:43 +0800)]
target/loongarch: Add floating point comparison instruction translation
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-12-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:43:00 +0000 (20:43 +0800)]
target/loongarch: Add floating point arithmetic instruction translation
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-11-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:59 +0000 (20:42 +0800)]
target/loongarch: Add fixed point extra instruction translation
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-10-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:58 +0000 (20:42 +0800)]
target/loongarch: Add fixed point atomic instruction translation
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-9-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:57 +0000 (20:42 +0800)]
target/loongarch: Add fixed point load/store instruction translation
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-8-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:56 +0000 (20:42 +0800)]
target/loongarch: Add fixed point bit instruction translation
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-7-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:55 +0000 (20:42 +0800)]
target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:54 +0000 (20:42 +0800)]
target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:53 +0000 (20:42 +0800)]
target/loongarch: Add main translation routines
This patch adds main translation routines and
basic functions for translation.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-4-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:52 +0000 (20:42 +0800)]
target/loongarch: Add core definition
This patch adds target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20220606124333.
2060567-3-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Song Gao [Mon, 6 Jun 2022 12:42:51 +0000 (20:42 +0800)]
target/loongarch: Add README
This patch gives an introduction to the LoongArch target.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220606124333.
2060567-2-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 6 Jun 2022 14:57:14 +0000 (07:57 -0700)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* prepare to expand usage of test venv
* fix CPUID when passing through host cache information
* a20 fix
* SGX fix
* generate per-target modinfo
* replay cleanups and simplifications
* "make modules" target
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmKeCV0UHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNVWQgArVaF9Q/RWd1jJ2EUoWhy/GKsrdBs
# CHmSzrYzF/0cqD4OtrjTRyUP72Kywf4/aP4GYtLsjSYRUyriqS4nm5yEkDsME+pH
# 0adATIumtGHBPjVJyPUux3H1cbPUmsxbE03ZIWUK65M/IM2m46hmPDTWVx6ZSXMN
# VnSQdTUeZdxY26D8zfLp+oufqmfgaPT19zURcMZlvWFJ830t+1spfZwH0RGjDlfZ
# ffNVMPcco1qreNFggNIV9sKtoLb8A9PxpFJPV9OtBONA5UGxZ7xhjjZY9jCI4Bxa
# xAd60nXeoAwiOP7LE2bEwXbPku3xgy2e0LNXhqblMGNGOjdlRlwfL/FhFw==
# =C9N3
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Jun 2022 07:04:13 AM PDT
# gpg: using RSA key
F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (29 commits)
meson: qga: do not use deprecated meson.build_root()
configure: remove reference to removed option
regenerate meson-buildoptions.sh
tests: run 'device-crash-test' from tests/venv
tests: add python3-venv to debian10.docker
tests: use tests/venv to run basevm.py-based scripts
tests: install "qemu" namespace package into venv
tests: add quiet-venv-pip macro
tests: silence pip upgrade warnings during venv creation
tests: use python3 as the python executable name
tests: add "TESTS_PYTHON" variable to Makefile
python: update for mypy 0.950
x86: cpu: fixup number of addressable IDs for logical processors sharing cache
x86: cpu: make sure number of addressable IDs for processor cores meets the spec
tests/Makefile.include: Fix 'make check-help' output
tests/avocado: add replay Linux test for Aarch64 machines
tests/avocado: add replay Linux tests for virtio machine
tests/avocado: update replay_linux test
docs: move replay docs to docs/system/replay.rst
docs: convert docs/devel/replay page to rst
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Paolo Bonzini [Mon, 6 Jun 2022 14:03:38 +0000 (16:03 +0200)]
meson: qga: do not use deprecated meson.build_root()
The function will return the build root of the parent project if called from a
subproject; that is irrelevant for QEMU's usage but rarely desirable, and
therefore the function was deprecated and replaced by two functions
project_build_root() and global_build_root(). Replace it with the former.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Mon, 6 Jun 2022 10:44:57 +0000 (12:44 +0200)]
configure: remove reference to removed option
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
OSDN Git Service
