OSDN Git Service
Jason Ekstrand [Tue, 9 Aug 2016 22:06:45 +0000 (15:06 -0700)]
i965/blorp: Make gen6 VS and GS disable helpers static
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 00:48:36 +0000 (17:48 -0700)]
i965: Roll intel_reg.h into brw_defines.h
More than half of the stuff in intel_reg.h had nothing whatsoever to do
with registers and really belongs in brw_defines.h anyway.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 00:30:30 +0000 (17:30 -0700)]
i965: Stop including brw_defines.h in brw_state.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 00:23:10 +0000 (17:23 -0700)]
i965/state: Move is_drawing_lines/points to gen6_clip_state.c
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Aug 2016 10:24:32 +0000 (03:24 -0700)]
genxml/gen9: Make 3DSTATE_SBE::AttributeActiveComponentFormat an array
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Aug 2016 07:27:22 +0000 (00:27 -0700)]
genxml: Add a uint MOCS field to VERTEX_BUFFER_STATE
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Aug 2016 07:12:43 +0000 (00:12 -0700)]
genxml: Make a couple of VERTEX_BUFFER_STATE fields boolean
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 11 Aug 2016 02:49:46 +0000 (19:49 -0700)]
genxml: Make VERTEX_ELEMENT_STATE::Valid a bool
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 10 Aug 2016 23:40:44 +0000 (16:40 -0700)]
genxml/gen6: Make SAMPLER_STATE look a bit more like gen7
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 15:32:09 +0000 (08:32 -0700)]
genxml: Add a uint MOCS field to DEPTH_BUFFER packets
This is easier than dealing with structs all the time
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 15:18:20 +0000 (08:18 -0700)]
genxml/gen6: Make "Depth Clear Value" a uint
The actual data storred is in float, UNORM24, or UNORM16 depending on the
actual depth format.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Aug 2016 00:32:10 +0000 (17:32 -0700)]
genxml/gen6: Add the 3D_Prim_Topo_Type enum
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Aug 2016 05:28:26 +0000 (22:28 -0700)]
genxml/gen6: Fix the length of 3DSTATE_WM
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 5 Aug 2016 23:26:57 +0000 (16:26 -0700)]
genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFER
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 5 Aug 2016 21:17:18 +0000 (14:17 -0700)]
genxml/gen6: Add uint MOCS fields for most things
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 17 Aug 2016 22:03:01 +0000 (15:03 -0700)]
nir: Rely on the fact that bcsel takes a well formed boolean.
According to Connor, it's safe to assume that the first operand of
bcsel, as well as the operand of b2f and b2i, must be well formed
booleans.
https://lists.freedesktop.org/archives/mesa-dev/2016-August/125658.html
With the previous improvements to a@bool handling, this now has no
change in shader-db instruction counts on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Fri, 12 Aug 2016 23:13:16 +0000 (16:13 -0700)]
i965/sched: Change the scheduling heuristics to favor early program termination.
This uses the unblocked time of the exit assigned to each available
node to attempt to unblock exit nodes as early as possible,
potentially reducing the runtime of the shader when an exit branch is
taken. There is a natural trade-off between terminating the program
as early as possible and reducing the worst-case latency of the
program as a whole (since this will typically move exit-unblocking
nodes closer to its dependencies potentially causing additional stalls
of the execution pipeline), but in practice the bandwidth and ALU
cycle savings from terminating the program earlier tend to outweigh
the slight increase in worst-case program execution latency, so it
makes sense to prefer nodes likely to unblock an earlier exit
regardless of the latency benefits of other available nodes.
I haven't observed any benchmark regressions from this change after
testing on VLV, HSW, BDW, BSW and SKL. The FPS of the GfxBench
Manhattan benchmark increases by 10%-20% and the FPS of Unigine Valley
improves by roughly 5% depending on the platform and settings.
The change to the register pressure-sensitive heuristic is rather
conservative and gives precedence to the existing heuristic in order
to avoid increasing register pressure and causing spill count and SIMD
width regressions in shader-db. It may make sense to revisit this
with additional performance data.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Tue, 16 Aug 2016 07:56:04 +0000 (00:56 -0700)]
i965/sched: Assign a preferred exit node to each node of the dependency graph.
This adds a bit of metadata to schedule_node that will be used to
compare available nodes in the scheduling heuristic code based on
which of them unblocks the earliest successor exit node. Note that
assigning exit nodes wouldn't be necessary in a bottom-up scheduler
because we could achieve the same effect by scheduling the exit nodes
themselves appropriately.
No shader-db changes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Tue, 16 Aug 2016 07:01:31 +0000 (00:01 -0700)]
i965/sched: Calculate the critical path of scheduling nodes non-recursively.
The critical path of each node is calculated by induction based on the
critical paths of its children, which can be done in a post-order
depth-first traversal of the dependency graph. The current code
implements graph traversal by iterating over all nodes of the graph
and then recursing into its children -- But it turns out that
recursion is unnecessary because the lexical order of instructions in
the block is already a good enough reverse post-order of the
dependency graph (if it weren't a reverse post-order some instruction
would have been located before one of its dependencies in the original
ordering of the basic block, which is impossible), so we just need to
walk the instruction list in reverse to achieve the same result more
efficiently.
No shader-db changes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Mon, 8 Aug 2016 19:43:18 +0000 (12:43 -0700)]
i965/fs: Switch to per-subspan discard jumps.
ANY4H is more efficient than ANY8H and ANY16H because it makes sure
that whenever a whole subspan hits a discard statement it gets
disabled by the EU until the end of the program, regardless of whether
the discard condition is uniform across all channels of the SIMD8-16
thread. OTOH ANY8H/ANY16H would cause the rest of the program to be
executed for *all* channels if only one of the channels hadn't taken
the discard branch, potentially increasing the bandwidth and ALU usage
of the program unnecessarily.
This change increases the FPS by over 3x of a simple micro-benchmark
that discards a bunch of fragments and then does a single costly
texturing operation. I've just re-verified the FPS change on HSW and
SKL, but I expect all platforms from Gen6 up to get a similar benefit.
Note that we could potentially be more aggressive and use the NORMAL
predicate to discard individual channels, but that would need to
happen post-scheduling because the scheduler currently doesn't care to
reorder HALT instructions with respect to other instructions, and the
NORMAL predicate would cause the results of subsequent derivative
computations to become undefined -- If the scheduler didn't reorder
HALT instructions it would actually be safe to switch to NORMAL
because the behavior of derivative computations after a non-uniform
discard statement is undefined by the GLSL spec, but that would make
the optimization implemented by one of the following commits somewhat
more difficult.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Mon, 8 Aug 2016 19:44:12 +0000 (12:44 -0700)]
i965/fs: Drop bogus writemasking disable bit from HALT instructions.
This may have been the reason people ran into problems with
non-uniform HALT instructions and ended up using the inefficient
ANY16H/ANY8H predicates instead of ANY4H or NORMAL in order to prevent
non-uniform discard. The HALT instruction is able to handle
non-uniform execution masks just fine.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Fri, 8 Jul 2016 05:35:15 +0000 (01:35 -0400)]
mesa: avoid valgrind warning due to opaque only being set sometimes
Valgrind complains with a "Conditional jump or move depends on
uninitialised value(s)" warning due to opaque being conditionally
initialized. However in the punchthrough_alpha == true case, it is
always initialized, so just flip the condition around to silence the
warning.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Ilia Mirkin [Wed, 17 Aug 2016 21:12:10 +0000 (17:12 -0400)]
vbo: remove unnecessary max_basevertex computation
The max basevertex is already computed and added into max_index by the
caller, _tnl_draw_prims.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Wed, 17 Aug 2016 21:12:09 +0000 (17:12 -0400)]
vbo: add basevertex when looking up elements for vbo splitting
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97351
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Thu, 11 Aug 2016 22:57:30 +0000 (00:57 +0200)]
radeonsi: initialize and finalize the LLVM function pass manager
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Emil Velikov [Thu, 28 Jul 2016 13:43:46 +0000 (14:43 +0100)]
isl: automake: use VISIBILITY_CFLAGS to restrict symbol visibility
v2: Add VISIBILITY_CFLAGS to AM_CFLAGS (Ken)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
mil Velikov [Wed, 27 Jul 2016 15:19:41 +0000 (08:19 -0700)]
anv: remove dummy VK_DEBUG_MARKER_EXT entry points
The vkCmdDbgMarker{Begin,End} symbols are exported, yet the json does no
advertise that the driver supports the extension. Furthermore the
functions are empty stubs.
Remove those until we get a proper implementation and json notation.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Wed, 27 Jul 2016 13:02:53 +0000 (14:02 +0100)]
anv: do not export the Vulkan API
With version 1 of the Loader interface there is an internal/private symbol
(vk_icdGetInstanceProcAddr) which is used to retrieve all the API from the
Vulkan entrypoints from the ICD. Implying that exposing the Vulkan API is not
recommended.
Version 2 goes a step further explicitly forbiding the ICD from exposing Vulkan
symbols (and adding a negotiation API)
As a reference:
- Nvidia 367.35
Missing negotiation API - version 1.
Exposes only vk_icdGetInstanceProcAddr.
- AMD 16.30.3.306809
Have negotiation API - version 2,
Exposes vk_icdGetInstanceProcAddr.
Exposes a couple of Vulkan entry points - seems to be in violation with the spec.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Wed, 27 Jul 2016 13:02:52 +0000 (14:02 +0100)]
anv: automake: build with -Bsymbolic
Explicitly suggested in the Loader interface version 2 section, but it's good
idea either way. It essentially, ensures that our symbols are not interposed.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 28 Jul 2016 13:40:08 +0000 (14:40 +0100)]
anv: automake: use VISIBILITY_CFLAGS to restrict symbol visibility
Hide the internal symbols and annotate the vk_icdGetInstanceProcAddr as public
since the loader needs it (since v1 of the loader interface).
v2: Add VISIBILITY_CFLAGS to AM_CFLAGS (Ken)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 28 Jul 2016 13:39:21 +0000 (14:39 +0100)]
anv: remove internal 'validate' layer
Presently the layer has only a single entry point. As mentioned by Jason the
function does not validate anything that isn't checked elsewhere, thus we can
drop the whole thing.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Kenneth Graunke [Wed, 17 Aug 2016 22:03:00 +0000 (15:03 -0700)]
nir/search: Extend 'a@bool' to handle a couple of system values.
load_front_face and load_helper_invocation produce booleans.
On Broadwell:
total instructions in shared programs:
11638956 ->
11638011 (-0.01%)
instructions in affected programs: 115093 -> 114148 (-0.82%)
helped: 628
HURT: 14
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 17 Aug 2016 22:02:59 +0000 (15:02 -0700)]
nir/search: Fold src_is_bool()/alu_instr_is_bool() into src_is_type().
I don't want src_is_bool() and src_is_type(x, nir_type_bool) to behave
differently. Having the logic spread out over three functions makes it
harder to decide where to put new logic, as well.
So, combine them all. It's a bit simpler because there's now only one
recursive function rather than a pair of mutually recursive functions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 17 Aug 2016 22:02:58 +0000 (15:02 -0700)]
nir/search: Introduce a src_is_type() helper for 'a@type' handling.
Currently, 'a@type' can only match if 'a' is produced by an ALU
instruction. This is rather limited - there are other cases we
can easily detect which we should handle.
Extending the code in-place would be fairly messy, so we introduce
a new src_is_type() helper.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 17 Aug 2016 13:35:01 +0000 (06:35 -0700)]
i965: Fix barrier count shift in scalar TCS backend.
The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend
correctly shifts by 9, but the scalar backend only shifted by 8.
It's not like this changed - I think I just made a typo when writing
the original scalar TCS backend code.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Kenneth Graunke [Wed, 17 Aug 2016 13:26:01 +0000 (06:26 -0700)]
i965: Fix execution size of scalar TCS barrier setup code.
Previously, the scalar TCS backend was generating:
mov(8) g17<1>UD 0x00000000UD { align1 WE_all 1Q compacted };
and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x0000000bUD { align1 WE_all 1Q };
or(8) g17.2<1>UD g17.2<8,8,1>UD 0x00008200UD { align1 WE_all 1Q };
send(8) null<1>UW g17<8,8,1>UD
gateway (barrier msg) mlen 1 rlen 0 { align1 WE_all 1Q };
This is rubbish - g17.2<8,8,1>UD spans two registers, and is an illegal
region. Not to mention it clobbers 8 channels of data when we only
wanted to touch m0.2.
Instead, we want:
mov(8) g17<1>UD 0x00000000UD { align1 WE_all 1Q compacted };
and(1) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all };
shl(1) g17.2<1>UD g17.2<0,1,0>UD 0x0000000bUD { align1 WE_all };
or(1) g17.2<1>UD g17.2<0,1,0>UD 0x00008200UD { align1 WE_all };
send(8) null<1>UW g17<8,8,1>UD
gateway (barrier msg) mlen 1 rlen 0 { align1 WE_all 1Q };
Using component() accomplishes this.
Fixes GL44-CTS.tessellation_shader.tessellation_shader_tc_barriers.
barrier_guarded_read_write_calls on Skylake. Probably fixes other
barrier issues on Gen8+.
v2: Use a group(1, 0) builder so inst->exec_size is set correctly
(thanks to Francisco Jerez for catching that it was incorrect).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Wed, 8 Jun 2016 01:18:49 +0000 (18:18 -0700)]
i965: Implement the WaPreventHSTessLevelsInterference workaround.
Fixes several GL44-CTS.tessellation_shader (and GL45 and ES31) subcases:
- vertex_spacing
- tessellation_shader_point_mode.points_verification
- tessellation_shader_quads_tessellation.inner_tessellation_level_rounding
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Kenneth Graunke [Wed, 17 Aug 2016 12:03:29 +0000 (05:03 -0700)]
nir/builder: Add bany_inequal and bany helpers.
The first simply picks the bany_inequal[234] opcodes based on the SSA
def's number of components. The latter implicitly compares with zero
to achieve the same semantics of GLSL's any().
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Kenneth Graunke [Tue, 16 Aug 2016 05:26:42 +0000 (22:26 -0700)]
mesa: Fix uf10_to_f32() scale factor in the E == 0 and M != 0 case.
GL_EXT_packed_float, 2.1.B Unsigned 10-Bit Floating-Point Numbers:
0.0, if E == 0 and M == 0,
2^-14 * (M / 32), if E == 0 and M != 0,
2^(E-15) * (1 + M/32), if 0 < E < 31,
INF, if E == 31 and M == 0, or
NaN, if E == 31 and M != 0,
In the second case (E == 0 and M != 0), we were multiplying the mantissa
by 2^-20, when we should have been multiplying by 2^-19 (which is
2^(-14 + -5), or 2^-14 * 2^-5, or 2^-14 / 32).
The previous section defines the formula for 11-bit numbers, which is:
2^-14 * (M / 64), if E == 0 and M != 0,
In other words, we had accidentally copy and pasted the 11-bit code
to the 10-bit case, and neglected to change the exponent.
Fixes dEQP-GLES3.functional.pbo.renderbuffer.r11f_g11f_b10f_triangles
when run with surface dimensions of 1536x1152 or 1920x1080.
Cc: mesa-stable@lists.freedesktop.org
References: https://code.google.com/p/chrome-os-partner/issues/detail?id=56244
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Tim Rowley [Wed, 17 Aug 2016 19:30:32 +0000 (14:30 -0500)]
swr: [rasterizer core] only use Viewport/Scissors during SwrDraw* operations
Add explicit rects for:
- SwrClearRenderTarget
- SwrDiscardRect
- SwrInvalidateTiles
- SwrStoreTiles
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 17 Aug 2016 19:29:44 +0000 (14:29 -0500)]
swr: [rasterizer common] reorder SWR_FORMAT_INFO
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 16 Aug 2016 18:40:47 +0000 (12:40 -0600)]
swr: [rasterizer core] make dirtytile list point directly to macrotilequeues
Speeds up high geometry HPC workloads.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 16 Aug 2016 18:38:36 +0000 (12:38 -0600)]
swr: [rasterizer core] portability - remove use of INT64
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Mon, 15 Aug 2016 17:58:54 +0000 (11:58 -0600)]
swr: [rasterizer core] viewport transform disabled fix
When viewport transform is disabled (ie. screen space coords are passed
in directly), the W component should be interpreted as RHW.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 12 Aug 2016 22:59:25 +0000 (16:59 -0600)]
swr: [rasterizer core] clamp scissor rects to current tile rect
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 12 Aug 2016 19:39:44 +0000 (13:39 -0600)]
swr: [rasterizer core] align stats structures
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 11 Aug 2016 20:52:18 +0000 (14:52 -0600)]
swr: [rasterizer core] use AVX2 permute to simplify PaTriList
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 11 Aug 2016 16:49:43 +0000 (10:49 -0600)]
swr: [rasterizer core] move some global variables to SWR_CONTEXT
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 10 Aug 2016 19:20:30 +0000 (13:20 -0600)]
swr: [rasterizer core] change scale on VP matrix element gathers
Was 1, which led to pulling denorms for non-zero indices.
Changed to sizeof(float).
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 10 Aug 2016 17:25:31 +0000 (11:25 -0600)]
swr: [rasterizer] implementing native AVX-512 simd16 intrinsics
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 23:53:00 +0000 (16:53 -0700)]
i965/blorp: Use nir_alu_type for the texture data type
This lets us remove the brw_reg.h include
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:33:43 +0000 (15:33 -0700)]
i965: brw_blorp_blit.cpp -> blorp_blit.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:30:57 +0000 (15:30 -0700)]
i965: brw_blorp_clear.cpp -> blorp_clear.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:25:17 +0000 (15:25 -0700)]
i965: Split brw_blorp.c/h into multiple files
This mega-commit pulls most of the i965-specific bits of blorp into the
brw_blorp.c/h files which now contain nothing but i965 wrappers around
"core blorp" calls. The "core blorp" api is moved into blorp.h and the
internal blorp data structures are moved into blorp_priv.h. The new file
blorp.c is created to house "core blorp" internals which are pulled from
the old brw_blorp.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 00:48:05 +0000 (17:48 -0700)]
i965/blorp: Factor the guts of blorp_hiz_exec into a helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:03:49 +0000 (14:03 -0700)]
i965/blorp: Break the guts of do_single_blorp_clear into two helpers
The helpers are completely miptree-unaware and each fairly cleanly do a
single thing. This does come at the downside of not doing proper debug
reporting on whether or not we're doing replicated clears.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:03:42 +0000 (14:03 -0700)]
i965/meta_util: Convert get_fast_clear_rect to take an isl_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:09:14 +0000 (14:09 -0700)]
i965/blorp/clear: Move isl_surf setup higher in the function
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:44:50 +0000 (14:44 -0700)]
i965/blorp: Refactor fast-clear logic a bit
This pulls the mcs allocation into the if statement where we initially
determine that we are doing a fast clear and moves the programming of
wm_inputs and figuring out the fast clear rect into it's own if statement.
The next commit will put code inbetween the two.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:05:48 +0000 (14:05 -0700)]
i965/blorp/clear: Stop stomping the destination format
The blorp_surface_info_init call above should set the format for us and
stomping it later does nothing whatsoever.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 08:13:49 +0000 (01:13 -0700)]
i965/meta_util: Only modify the input parameters in get_fast_clear_rect
We had another inline copy of brw_meta_get_buffer_rect embedded in
get_fast_clear_rect for no good reason. This lets us get rid of the
gl_frameuffer parameter to get_fast_clear_rect.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 08:08:14 +0000 (01:08 -0700)]
i965/blorp: Stop calling brw_meta_get_buffer_rect
We already have an inlined version of the function slightly higher up in
do_single_blorp_clear and all calling it does is stomp the values with the
same thing. We might as well just get rid of it.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 23 Jul 2016 19:46:10 +0000 (12:46 -0700)]
i965/blorp: Pull the guts of resolve_color into a miptree-agnostic helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 23 Jul 2016 19:13:07 +0000 (12:13 -0700)]
i965/meta_util: Convert get_resolve_rect to use ISL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:19:12 +0000 (19:19 -0700)]
i965/blorp: Make the guts of brw_blorp_blit_miptrees miptree-unaware
Now that we have the brw_blorp_surf struct, we can start to make bits of
blorp completely miptree-unaware. To start things off, we split the guts
of brw_blorp_blit_miptrees into a brw_blorp_blit function which knows
nothing about miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:04:03 +0000 (19:04 -0700)]
i965/blorp: Add a new brw_blorp_surf intermediate struct
At the moment, this seems to make all of the interfaces messier rather than
clener. However, it does provide a representation of a surface that
simultaneously contains everything and is completely unaware of miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:01:38 +0000 (19:01 -0700)]
i965/blorp: Use the isl_surf for more params setup
The isl_surf munging doesn't happen until fairly late in the blorp_blit
function. We can use the isl_surf for the vast majority if not all of our
params setup.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:59:16 +0000 (19:59 -0700)]
i965/blorp: Do gen6 stencil offsets up-front
This keeps all of the nastyness of gen6 stencil on the i965 side of the API
line and lets us delete that nasty hand-rolled ISL-based offset path that
we were using for ALL_SLICES_AT_EACH_LOD.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 22 Jul 2016 21:41:43 +0000 (14:41 -0700)]
i965/blorp: Set up HiZ surfaces up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:01:56 +0000 (16:01 -0700)]
i964/blorp: Set up most aux surfaces up-front
This commit also adds support for an offset for aux surfaces. In GL, this
only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux
surfaces are at a non-zero offset and that is likely to happen in GL
eventually.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 22 Jul 2016 21:24:06 +0000 (14:24 -0700)]
i965/blorp: Stop using the miptree in state setup for tex/rt surfaces
This commit movies us from a miptree model to a surf+bo+offset model. In
the GL driver, miptrees are almost always at the start of the bo so the
offset is zero but we don't want to always make that assumption. In the
sort term, gen6 stencil and HiZ will be at an offset but, in the long term,
any Vulkan surface is liable to be at a non-zero offset.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:05:57 +0000 (14:05 -0700)]
i965/blorp/blit: Move format work-arounds before surface_info_init
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 16:30:15 +0000 (09:30 -0700)]
i965/miptree: Add real support for HiZ
The previous HiZ support was bogus because all of get_aux_isl_surf looked
at mt->mcs_mt directly. For HiZ buffers, you need to look at either
mt->hiz_buf or mt->hiz_buf->mt.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 5 Aug 2016 22:06:36 +0000 (15:06 -0700)]
isl/state: Only set clear color if aux is used
Otherwise, the clear color will get ignored. This prevents assertion
errors if clear color is set to something invalid and aux is not used.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:02:29 +0000 (16:02 -0700)]
i965/miptree: Use the isl helpers for creating aux surfaces
In order for the calculations of things such as fast clear rectangles to
work, we need more details of the auxiliary surface to be correct. In
particular, we need to be able to trust the width and height fields.
(These are not necessarily what you want coming out of the miptree.) The
only values state setup really cares about are the row and array pitch and
those we can safely stomp from the miptree.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 07:52:34 +0000 (00:52 -0700)]
isl: Add helpers for creating different types of aux surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 16:33:23 +0000 (09:33 -0700)]
i965/miptree: Use mcs_mt->qpitch for aux surfaces
At one point, we were doing this correctly. It must have gotten lost in
one of the many rebases.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 19 Jul 2016 23:25:50 +0000 (16:25 -0700)]
i965/miptree: Allow get_aux_isl_surf when there is no aux surface
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:02:45 +0000 (16:02 -0700)]
i965/miptree: Support depth in get_isl_clear_color
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:38:54 +0000 (14:38 -0700)]
isl/state: Add an assertion for IVB multisample array textures
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 23:14:24 +0000 (16:14 -0700)]
isl: Add a #define for DEV_IS_BAYTRAIL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:34:02 +0000 (18:34 -0700)]
i965/blorp: Remove unused fields from blorp_surface_info
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces. Let's just have the one field for that.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:33:05 +0000 (18:33 -0700)]
i965/blorp: Simplify depth buffer state setup a bit
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:13:39 +0000 (17:13 -0700)]
i965/blorp: Use the generic surface state path for gen8 textures
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 15:43:27 +0000 (08:43 -0700)]
isl: Add asserts for gen8+ X/YOffset rules
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 18:54:14 +0000 (11:54 -0700)]
i965/blorp: Only do offset hacks for fake W-tiling and IMS
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces. This isn't really necessary since
we can just use the base level/layer provided in the surface state. While
it may have simplified blorp's original design, we haven't been using the
blorp path for surface state on gen8 thanks to render compression and
there's really no good need for it most of the time. This commit restricts
such surface munging to the cases of fake W-tiling and fake interleaved
multisampling.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:46:07 +0000 (14:46 -0700)]
i965/blorp: Add a z_offset field to blorp_surface_info
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:10:49 +0000 (14:10 -0700)]
i965/blorp: Pass the Z component into all texture operations
Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message. We may
as well just pass it through everything.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 02:30:32 +0000 (19:30 -0700)]
i965/blorp: Rework hiz rect alignment calculations
At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero. However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification. Also, we only need to align the surface dimensions in the
case where we are operating on miplevel 0. Previously, it didn't matter
because it aligned on miplevel 0 and, for all other miplevels, the miptree
code guaranteed that the level was already aligned.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:30:35 +0000 (17:30 -0700)]
i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9
The sampling hardware can handle them ok. It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one. The render
hardware isn't so smart.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 22:30:15 +0000 (15:30 -0700)]
i965/miptree: Fill out the isl_surf::usage field
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:25:59 +0000 (14:25 -0700)]
isl: Take the slice0_extent shortcut for interleaved MSAA
The shortcut works just fine for MSAA and the comment even says so.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:21:44 +0000 (14:21 -0700)]
isl: Remove duplicate px->sa conversions
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples. There is no
need to do the conversion and doing so gives us an incorrect value.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 16:05:46 +0000 (09:05 -0700)]
i965/blorp: Use the isl_view from the blorp_surface_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 17 Aug 2016 08:06:36 +0000 (01:06 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::width/height
Instead, we manually mutate the surface size as needed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:48:20 +0000 (20:48 -0700)]
i965/blorp: Move surface offset calculations into a helper
The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:57:41 +0000 (20:57 -0700)]
i965/blorp: Use ISL to compute image offsets
For the moment, we still call the old miptree function; we just assert that
the two are equal.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 22:00:31 +0000 (15:00 -0700)]
isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 04:50:22 +0000 (21:50 -0700)]
isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer. While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:11:46 +0000 (20:11 -0700)]
i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state. For now, we just use it for the format and the
swizzle.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>