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Rafael Espindola [Thu, 16 May 2013 19:44:40 +0000 (19:44 +0000)]
More test coverage for addFrameMove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182041
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Jack Carter [Thu, 16 May 2013 19:40:19 +0000 (19:40 +0000)]
Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040
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Benjamin Kramer [Thu, 16 May 2013 18:47:58 +0000 (18:47 +0000)]
DAGCombine: Also shrink eq compares where the constant is exactly as large as the smaller type.
if ((x & 255) == 255)
before: movzbl %al, %eax
cmpl $255, %eax
after: cmpb $-1, %al
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182038
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Akira Hatanaka [Thu, 16 May 2013 18:42:42 +0000 (18:42 +0000)]
[mips] Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036
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Akira Hatanaka [Thu, 16 May 2013 18:40:12 +0000 (18:40 +0000)]
[mips] Delete unused enum value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182035
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Jakob Stoklund Olesen [Thu, 16 May 2013 18:03:08 +0000 (18:03 +0000)]
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034
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Ulrich Weigand [Thu, 16 May 2013 17:58:02 +0000 (17:58 +0000)]
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032
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Hal Finkel [Thu, 16 May 2013 16:52:41 +0000 (16:52 +0000)]
PPC32 cannot form counter loops around i64 FP conversions
On PPC32, i64 FP conversions are implemented using runtime calls (which clobber
the counter register). These must be excluded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023
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Rafael Espindola [Thu, 16 May 2013 16:48:46 +0000 (16:48 +0000)]
Add a triple to the test to try to fix the windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182022
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Rafael Espindola [Thu, 16 May 2013 16:34:38 +0000 (16:34 +0000)]
More addFrameMove test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182021
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Bill Schmidt [Thu, 16 May 2013 16:15:18 +0000 (16:15 +0000)]
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll
While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler. The new CHECK-DAG support is perfect for
avoiding this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020
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Rafael Espindola [Thu, 16 May 2013 16:09:54 +0000 (16:09 +0000)]
Add more addFrameMove test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182019
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Aaron Ballman [Thu, 16 May 2013 16:03:36 +0000 (16:03 +0000)]
Fixing a 64-bit conversion warning in MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182018
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Rafael Espindola [Thu, 16 May 2013 15:18:50 +0000 (15:18 +0000)]
Add more test coverage for addFrameMove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182017
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Rafael Espindola [Thu, 16 May 2013 15:08:37 +0000 (15:08 +0000)]
Remove dead calls to addFrameMove.
Without a PROLOG_LABEL present, the cfi instructions are never printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016
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Ulrich Weigand [Thu, 16 May 2013 14:53:05 +0000 (14:53 +0000)]
[PowerPC] Report true displacement value from getPreIndexedAddressParts
DAGCombiner::CombineToPreIndexedLoadStore calls a target routine to
decompose a memory address into a base/offset pair. It expects the
offset (if constant) to be the true displacement value in order to
perform optional additional optimizations; in particular, to convert
other uses of the original pointer into uses of the new base pointer
after pre-increment.
The PowerPC implementation of getPreIndexedAddressParts, however,
simply calls SelectAddressRegImm, which returns a TargetConstant.
This value is appropriate for encoding into the instruction, but
it is not always usable as true displacement value:
- Its type is always MVT::i32, even on 64-bit, where addresses
ought to be i64 ... this causes the optimization to simply
always fail on 64-bit due to this line in DAGCombiner:
// FIXME: In some cases, we can be smarter about this.
if (Op1.getValueType() != Offset.getValueType()) {
- Its value is truncated to an unsigned 16-bit value if negative.
This causes the above opimization to generate wrong code.
This patch fixes both problems by simply returning the true
displacement value (in its original type). This doesn't
affect any other user of the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182012
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Rafael Espindola [Thu, 16 May 2013 14:51:26 +0000 (14:51 +0000)]
Add more addFrameMove test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182011
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Rafael Espindola [Thu, 16 May 2013 14:30:09 +0000 (14:30 +0000)]
Extend test to check the .cfi instructions.
I am about to refactor the calls to addFrameMove and some of the ppc
ones were not being tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182009
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Richard Sandiford [Thu, 16 May 2013 13:39:02 +0000 (13:39 +0000)]
[SystemZ] Tweak register array comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182007
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Benjamin Kramer [Thu, 16 May 2013 11:46:50 +0000 (11:46 +0000)]
Relax CHECK-NEXTs a bit to cope with atom's return nop padding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181999
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Evgeniy Stepanov [Thu, 16 May 2013 09:14:05 +0000 (09:14 +0000)]
[msan] Switch TLS globals to initial-exec model.
They are always defined in the main executable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181994
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Patrik Hagglund [Thu, 16 May 2013 08:37:22 +0000 (08:37 +0000)]
Removed unused variable, detected by gcc
-Wunused-but-set-variable. Leftover from r181979.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181993
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Rafael Espindola [Thu, 16 May 2013 04:59:17 +0000 (04:59 +0000)]
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181982
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Rafael Espindola [Thu, 16 May 2013 04:16:25 +0000 (04:16 +0000)]
Don't call addFrameMove on XCore.
getExceptionHandlingType is not ExceptionHandling::DwarfCFI on xcore, so
etFrameInstructions is never called. There is no point creating cfi
instructions if they are never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181979
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Richard Smith [Thu, 16 May 2013 04:12:04 +0000 (04:12 +0000)]
Respect the 'nobuiltin' attribute when determining if a call is to a memory builtin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181978
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Rafael Espindola [Thu, 16 May 2013 03:48:50 +0000 (03:48 +0000)]
Extend test for better coverage.
Without this change nothing was covering this addFrameMove:
// For 64-bit SVR4 when we have spilled CRs, the spill location
// is SP+8, not a frame-relative slot.
if (Subtarget.isSVR4ABI()
&& Subtarget.isPPC64()
&& (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
MachineLocation CSDst(PPC::X1, 8);
MachineLocation CSSrc(PPC::CR2);
MMI.addFrameMove(Label, CSDst, CSSrc);
continue;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181976
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Rafael Espindola [Thu, 16 May 2013 03:34:58 +0000 (03:34 +0000)]
Removed dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181975
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Lang Hames [Thu, 16 May 2013 02:20:41 +0000 (02:20 +0000)]
Fix PBQP graph iterator typedefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181973
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Reed Kotler [Thu, 16 May 2013 02:17:42 +0000 (02:17 +0000)]
Patch number 2 for mips16/32 floating point interoperability stubs.
This creates stubs that help Mips32 functions call Mips16
functions which have floating point parameters that are normally passed
in floating point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181972
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Derek Schuff [Wed, 15 May 2013 23:07:43 +0000 (23:07 +0000)]
Revert "Support unaligned load/store on more ARM targets"
This reverts r181898.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181944
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Eli Bendersky [Wed, 15 May 2013 22:41:28 +0000 (22:41 +0000)]
Remove dead code.
This method is not being used/tested anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181943
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Arnold Schwaighofer [Wed, 15 May 2013 22:38:14 +0000 (22:38 +0000)]
LoopVectorize: Move call of canHoistAllLoads to canVectorizeWithIfConvert
We only want to check this once, not for every conditional block in the loop.
No functionality change (except that we don't perform a check redudantly
anymore).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181942
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Rafael Espindola [Wed, 15 May 2013 22:27:35 +0000 (22:27 +0000)]
Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181941
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David Majnemer [Wed, 15 May 2013 22:23:21 +0000 (22:23 +0000)]
Set an explicit triple for this test.
This allows the test to correctly check symbol names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181939
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Hal Finkel [Wed, 15 May 2013 22:20:24 +0000 (22:20 +0000)]
undef setjmp in PPCCTRLoops
Trying to unbreak the VS build by copying some undef code from
Utils/LowerInvoke.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181938
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David Majnemer [Wed, 15 May 2013 22:03:08 +0000 (22:03 +0000)]
X86: Remove redundant test instructions
Increase the number of instructions LLVM recognizes as setting the ZF
flag. This allows us to remove test instructions that redundantly
recalculate the flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181937
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Bill Wendling [Wed, 15 May 2013 21:38:12 +0000 (21:38 +0000)]
Use proper syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181930
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Hal Finkel [Wed, 15 May 2013 21:37:41 +0000 (21:37 +0000)]
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927
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Hal Finkel [Wed, 15 May 2013 21:37:27 +0000 (21:37 +0000)]
Fix legalization of SETCC with promoted integer intrinsics
If the input operands to SETCC are promoted, we need to make sure that we
either use the promoted form of both operands (or neither); a mixture is not
allowed. This can happen, for example, if a target has a custom promoted
i1-returning intrinsic (where i1 is not a legal type). In this case, we need to
use the promoted form of both operands.
This change only augments the behavior of the existing logic in the case where
the input types (which may or may not have already been legalized) disagree,
and should not affect existing target code because this case would otherwise
cause an assert in the SETCC operand promotion code.
This will be covered by (essentially all of the) tests for the new PPCCTRLoops
infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181926
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Bill Wendling [Wed, 15 May 2013 21:36:46 +0000 (21:36 +0000)]
Add lldb and polly to the projects to tag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181925
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Derek Schuff [Wed, 15 May 2013 21:15:09 +0000 (21:15 +0000)]
Fix miscompile due to StackColoring incorrectly merging stack slots (PR15707)
IR optimisation passes can result in a basic block that contains:
llvm.lifetime.start(%buf)
...
llvm.lifetime.end(%buf)
...
llvm.lifetime.start(%buf)
Before this change, calculateLiveIntervals() was ignoring the second
lifetime.start() and was regarding %buf as being dead from the
lifetime.end() through to the end of the basic block. This can cause
StackColoring to incorrectly merge %buf with another stack slot.
Fix by removing the incorrect Starts[pos].isValid() and
Finishes[pos].isValid() checks.
Just doing:
Starts[pos] = Indexes->getMBBStartIdx(MBB);
Finishes[pos] = Indexes->getMBBEndIdx(MBB);
unconditionally would be enough to fix the bug, but it causes some
test failures due to stack slots not being merged when they were
before. So, in order to keep the existing tests passing, treat LiveIn
and LiveOut separately rather than approximating the live ranges by
merging LiveIn and LiveOut.
This fixes PR15707.
Patch by Mark Seaborn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181922
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Rafael Espindola [Wed, 15 May 2013 18:22:01 +0000 (18:22 +0000)]
Cleanup relocation sorting for ELF.
We want the order to be deterministic on all platforms. NAKAMURA Takumi
fixed that in r181864. This patch is just two small cleanups:
* Move the function to the cpp file. It is only passed to array_pod_sort.
* Remove the ppc implementation which is now redundant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181910
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NAKAMURA Takumi [Wed, 15 May 2013 18:01:35 +0000 (18:01 +0000)]
PPCISelLowering.h: Escape \@ in comments. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181907
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NAKAMURA Takumi [Wed, 15 May 2013 18:01:28 +0000 (18:01 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181906
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Michael Gottesman [Wed, 15 May 2013 17:43:03 +0000 (17:43 +0000)]
[objc-arc] Fixed a spelling error and made the statistic descriptions be consistent about their usage of periods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181901
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Douglas Gregor [Wed, 15 May 2013 17:41:02 +0000 (17:41 +0000)]
Add missing #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181900
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Derek Schuff [Wed, 15 May 2013 16:08:30 +0000 (16:08 +0000)]
Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for
v6+ Darwin as well as for v7+ on other targets.
The distinction is made because v6 doesn't guarantee support (but LLVM assumes
that Apple controls hardware+kernel and therefore have conformant v6 CPUs),
whereas v7 does provide this guarantee (and Linux behaves sanely).
Overall this should slightly improve performance in most cases because of
reduced I$ pressure.
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897
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Ulrich Weigand [Wed, 15 May 2013 15:07:42 +0000 (15:07 +0000)]
Remove MCELFObjectTargetWriter::adjustFixupOffset hack
Now that PowerPC no longer uses adjustFixupOffset, and no other
back-end (ever?) did, we can remove the infrastructure itself
(incidentally addressing a FIXME to that effect).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181895
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Ulrich Weigand [Wed, 15 May 2013 15:07:06 +0000 (15:07 +0000)]
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894
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Richard Sandiford [Wed, 15 May 2013 15:05:29 +0000 (15:05 +0000)]
[SystemZ] Make use of SUBTRACT HALFWORD
Thanks to Ulrich Weigand for noticing that this instruction was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893
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Ulrich Weigand [Wed, 15 May 2013 15:02:12 +0000 (15:02 +0000)]
[PowerPC] Add test case for r181891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181892
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Ulrich Weigand [Wed, 15 May 2013 15:01:46 +0000 (15:01 +0000)]
[PowerPC] Correctly handle fixups of other than 4 byte size
The PPCAsmBackend::applyFixup routine handles the case where a
fixup can be resolved within the same object file. However,
this routine is currently hard-coded to assume the size of
any fixup is always exactly 4 bytes.
This is sort-of correct for fixups on instruction text; even
though it only works because several of what really would be
2-byte fixups are presented as 4-byte fixups instead (requiring
another hack in PPCELFObjectWriter::adjustFixupOffset to clean
it up).
However, this assumption breaks down completely for fixups
on data, which legitimately can be of any size (1, 2, 4, or 8).
This patch makes applyFixup aware of fixups of varying sizes,
introducing a new helper routine getFixupKindNumBytes (along
the lines of what the ARM back end does). Note that in order
to handle fixups of size 8, we also need to fix the return type
of adjustFixupValue to uint64_t to avoid truncation.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181891
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Arnaud A. de Grandmaison [Wed, 15 May 2013 14:05:01 +0000 (14:05 +0000)]
Add Jade to the list of external projects using LLVM in the release notes.
Patch by: Antoine Lorence <Antoine.Lorence@insa-rennes.fr>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181886
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Richard Sandiford [Wed, 15 May 2013 12:53:31 +0000 (12:53 +0000)]
[SystemZ] Add more future work items to the README
Based on an analysis by Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181882
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Richard Sandiford [Wed, 15 May 2013 11:00:31 +0000 (11:00 +0000)]
[SystemZ] Consolidate disassembler tests for valid input into 2 big tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181879
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Richard Sandiford [Wed, 15 May 2013 09:58:19 +0000 (09:58 +0000)]
[SystemZ] Consolidate assembler tests into 4 big tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181878
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Timur Iskhodzhanov [Wed, 15 May 2013 09:00:30 +0000 (09:00 +0000)]
Fix build on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181873
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David Blaikie [Wed, 15 May 2013 07:36:59 +0000 (07:36 +0000)]
Use only explicit bool conversion operators
BitVector/SmallBitVector::reference::operator bool remain implicit since
they model more exactly a bool, rather than something else that can be
boolean tested.
The most common (non-buggy) case are where such objects are used as
return expressions in bool-returning functions or as boolean function
arguments. In those cases I've used (& added if necessary) a named
function to provide the equivalent (or sometimes negative, depending on
convenient wording) test.
One behavior change (YAMLParser) was made, though no test case is
included as I'm not sure how to reach that code path. Essentially any
comparison of llvm::yaml::document_iterators would be invalid if neither
iterator was at the end.
This helped uncover a couple of bugs in Clang - test cases provided for
those in a separate commit along with similar changes to `operator bool`
instances in Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181868
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NAKAMURA Takumi [Wed, 15 May 2013 02:16:23 +0000 (02:16 +0000)]
ELFRelocationEntry::operator<(): Try to stabilize the order. r_offset was insufficient to sort Relocs.
It should fix llvm/test/CodeGen/ARM/ehabi-mc-compact-pr*.ll on some hosts.
RELOCATION RECORDS FOR [.ARM.exidx]:
0 R_ARM_PREL31 .text
0 R_ARM_NONE __aeabi_unwind_cpp_pr0
FIXME: I am not sure of the directions of extra comparators, in Type and Index.
For now, they are different from the direction in r_offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181864
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Arnold Schwaighofer [Wed, 15 May 2013 02:02:45 +0000 (02:02 +0000)]
LoopVectorize: Fix comments
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181862
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Arnold Schwaighofer [Wed, 15 May 2013 01:44:30 +0000 (01:44 +0000)]
LoopVectorize: Hoist conditional loads if possible
InstCombine can be uncooperative to vectorization and sink loads into
conditional blocks. This prevents vectorization.
Undo this optimization if there are unconditional memory accesses to the same
addresses in the loop.
radar://
13815763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181860
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Jakob Stoklund Olesen [Tue, 14 May 2013 23:45:56 +0000 (23:45 +0000)]
Speed up Value::isUsedInBasicBlock() for long use lists.
This is expanding Ben's original heuristic for short basic blocks to
also work for longer basic blocks and huge use lists.
Scan the basic block and the use list in parallel, terminating the
search when the shorter list ends. In almost all cases, either the basic
block or the use list is short, and the function returns quickly.
In one crazy test case with very long use chains, CodeGenPrepare runs
400x faster. When compiling ARMDisassembler.cpp it is 5x faster.
<rdar://problem/
13840497>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181851
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Sylvestre Ledru [Tue, 14 May 2013 23:36:24 +0000 (23:36 +0000)]
Fix two typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181848
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NAKAMURA Takumi [Tue, 14 May 2013 23:05:00 +0000 (23:05 +0000)]
ExceptionDemo: Corresponding to r181820, SectionMemoryManager should belong to RTDyldMemoryManager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181844
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Ahmed Bougacha [Tue, 14 May 2013 22:41:29 +0000 (22:41 +0000)]
Object: Fix Mach-O relocation printing.
There were two problems that made llvm-objdump -r crash:
- for non-scattered relocations, the symbol/section index is actually in the
(aptly named) symbolnum field.
- sections are 1-indexed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181843
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Arnold Schwaighofer [Tue, 14 May 2013 22:33:24 +0000 (22:33 +0000)]
ARM ISel: Don't create illegal types during LowerMUL
The transformation happening here is that we want to turn a
"mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have
to make sure that X still has a valid vector type - possibly recreate an
extension to a smaller type. In case of a extload of a memory type smaller than
64 bit we used create a ext(load()). The problem with doing this - instead of
recreating an extload - is that an illegal type is exposed.
This patch fixes this by creating extloads instead of ext(load()) sequences.
Fixes PR15970.
radar://
13871383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181842
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Manman Ren [Tue, 14 May 2013 21:52:44 +0000 (21:52 +0000)]
GlobalOpt: fix an issue where CXAAtExitFn points to a deleted function.
CXAAtExitFn was set outside a loop and before optimizations where functions
can be deleted. This patch will set CXAAtExitFn inside the loop and after
optimizations.
Seg fault when running LTO because of accesses to a deleted function.
rdar://problem/
13838828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181838
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Eric Christopher [Tue, 14 May 2013 21:52:01 +0000 (21:52 +0000)]
Revert previous patch, it's actually on under Wall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181837
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Eric Christopher [Tue, 14 May 2013 21:49:38 +0000 (21:49 +0000)]
Add -Wreorder to the list of C++ warnings.
This built clean with clang, but if we see false positives on the bots
then we'll revert and turn it into a compiler specific check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181836
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Eric Christopher [Tue, 14 May 2013 21:33:10 +0000 (21:33 +0000)]
Make getCompileUnit non-const and return the current DIE if it
happens to be a compile unit. Noticed on inspection and tested
via calling on a newly created compile unit. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181835
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Michael Liao [Tue, 14 May 2013 20:34:12 +0000 (20:34 +0000)]
Add 'CHECK-DAG' support
Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181827
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Michael Liao [Tue, 14 May 2013 20:29:52 +0000 (20:29 +0000)]
Refactor string checking. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181824
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Bill Schmidt [Tue, 14 May 2013 19:35:45 +0000 (19:35 +0000)]
Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky. Tested via asm-parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821
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Filip Pizlo [Tue, 14 May 2013 19:29:00 +0000 (19:29 +0000)]
SectionMemoryManager shouldn't be a JITMemoryManager. Previously, the
EngineBuilder interface required a JITMemoryManager even if it was being used
to construct an MCJIT. But the MCJIT actually wants a RTDyldMemoryManager.
Consequently, the SectionMemoryManager, which is meant for MCJIT, derived
from the JITMemoryManager and then stubbed out a bunch of JITMemoryManager
methods that weren't relevant to the MCJIT.
This patch fixes the situation: it teaches the EngineBuilder that
RTDyldMemoryManager is a supertype of JITMemoryManager, and that it's
appropriate to pass a RTDyldMemoryManager instead of a JITMemoryManager if
we're using the MCJIT. This allows us to remove the stub methods from
SectionMemoryManager, and make SectionMemoryManager a direct subtype of
RTDyldMemoryManager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181820
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Jyotsna Verma [Tue, 14 May 2013 18:54:06 +0000 (18:54 +0000)]
Hexagon: Pass to replace tranfer/copy instructions into combine instruction
where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817
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Eric Christopher [Tue, 14 May 2013 18:33:40 +0000 (18:33 +0000)]
Reapply "Subtract isn't commutative, fix this for MMX psub." with
a somewhat randomly chosen cpu that will minimize cpu specific
differences on bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181814
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Eric Christopher [Tue, 14 May 2013 18:20:42 +0000 (18:20 +0000)]
Temporarily revert "Subtract isn't commutative, fix this for MMX psub."
It's causing failures on the atom bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181812
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Rafael Espindola [Tue, 14 May 2013 18:06:14 +0000 (18:06 +0000)]
Fix __clear_cache declaration.
This fixes the build with gcc in gnu++98 and gnu++11 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181811
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Eric Christopher [Tue, 14 May 2013 17:52:05 +0000 (17:52 +0000)]
Subtract isn't commutative, fix this for MMX psub.
Patch by Andrea DiBiagio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181809
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Jakob Stoklund Olesen [Tue, 14 May 2013 17:47:27 +0000 (17:47 +0000)]
Recognize sparc64 as an alias for sparcv9 triples.
Patch by Brad Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181808
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Jyotsna Verma [Tue, 14 May 2013 17:16:38 +0000 (17:16 +0000)]
Hexagon: Add patterns to generate 'combine' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805
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Jyotsna Verma [Tue, 14 May 2013 16:36:34 +0000 (16:36 +0000)]
Hexagon: ArePredicatesComplement should not restrict itself to TFRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803
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Kai Nacke [Tue, 14 May 2013 16:30:51 +0000 (16:30 +0000)]
Add bitcast to store of personality function.
The personality function is user defined and may have an arbitrary result type.
The code assumes always i8*. This results in an assertion failure if a different
type is used. A bitcast to i8* is added to prevent this failure.
Reviewed by: Renato Golin, Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181802
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Derek Schuff [Tue, 14 May 2013 16:26:38 +0000 (16:26 +0000)]
Fix ARM FastISel tests, as a first step to enabling ARM FastISel
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on
enabling it for other targets. As a first step I've fixed some of the tests.
Changes to ARM FastISel tests:
- Different triples don't generate the same relocations (especially
movw/movt versus constant pool loads). Use a regex to allow either.
- Mangling is different. Use a regex to allow either.
- The reserved registers are sometimes different, so registers get
allocated in a different order. Capture the names only where this
occurs.
- Add -verify-machineinstrs to some tests where it works. It doesn't
work everywhere it should yet.
- Add -fast-isel-abort to many tests that didn't have it before.
- Split out the VarArg test from fast-isel-call.ll into its own
test. This simplifies test setup because of --check-prefix.
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801
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Bill Schmidt [Tue, 14 May 2013 16:08:32 +0000 (16:08 +0000)]
PPC32: Fix stack collision between FP and CR save areas.
The changes to CR spill handling missed a case for 32-bit PowerPC.
The code in PPCFrameLowering::processFunctionBeforeFrameFinalized()
checks whether CR spill has occurred using a flag in the function
info. This flag is only set by storeRegToStackSlot and
loadRegFromStackSlot. spillCalleeSavedRegisters does not call
storeRegToStackSlot, but instead produces MI directly. Thus we don't
see the CR is spilled when assigning frame offsets, and the CR spill
ends up colliding with some other location (generally the FP slot).
This patch sets the flag in spillCalleeSavedRegisters for PPC32 so
that the CR spill is properly detected and gets its own slot in the
stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800
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Jyotsna Verma [Tue, 14 May 2013 15:50:49 +0000 (15:50 +0000)]
Hexagon: Test case to check if branch probabilities are properly reflected in
the jump instructions in the form of taken/not-taken hint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181799
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Jyotsna Verma [Tue, 14 May 2013 15:33:27 +0000 (15:33 +0000)]
Hexagon: Remove dead-code after unconditional return from addPreSched2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797
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Tom Stellard [Tue, 14 May 2013 14:42:56 +0000 (14:42 +0000)]
R600/SI: Add processor type for Hainan asic
Patch by: Alex Deucher
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792
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Duncan Sands [Tue, 14 May 2013 13:29:16 +0000 (13:29 +0000)]
Get the unittests compiling when building with cmake and the setting
-DLLVM_ENABLE_THREADS=false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788
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Rafael Espindola [Tue, 14 May 2013 13:02:37 +0000 (13:02 +0000)]
Declare __clear_cache.
GCC declares __clear_cache in the gnu modes (-std=gnu++98,
-std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch
declares it and therefore fixes the build when using one of the strict modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181785
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Richard Sandiford [Tue, 14 May 2013 10:17:52 +0000 (10:17 +0000)]
[SystemZ] Add disassembler support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777
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Michel Danzer [Tue, 14 May 2013 09:53:30 +0000 (09:53 +0000)]
R600/SI: Add lit test coverage for the remaining patterns added recently
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181775
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Richard Sandiford [Tue, 14 May 2013 09:49:11 +0000 (09:49 +0000)]
[SystemZ] Add extra testscases for r181773
Forgot to svn add these...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774
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Richard Sandiford [Tue, 14 May 2013 09:47:26 +0000 (09:47 +0000)]
[SystemZ] Rework handling of constant PC-relative operands
The GNU assembler treats things like:
brasl %r14, 100
in the same way as:
brasl %r14, .+100
rather than as a branch to absolute address 100. We implemented this in
LLVM by creating an immediate operand rather than the usual expr operand,
and by handling immediate operands specially in the code emitter.
This was undesirable for (at least) three reasons:
- the specialness of immediate operands was exposed to the backend MC code,
rather than being limited to the assembler parser.
- in disassembly, an immediate operand really is an absolute address.
(Note that this means reassembling printed disassembly can't recreate
the original code.)
- it would interfere with any assembly manipulation that we might
try in future. E.g. operations like branch shortening can change
the relative position of instructions, but any code that updates
sym+offset addresses wouldn't update an immediate "100" operand
in the same way as an explicit ".+100" operand.
This patch changes the implementation so that the assembler creates
a "." label for immediate PC-relative operands, so that the operand
to the MCInst is always the absolute address. The patch also adds
some error checking of the offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773
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Richard Sandiford [Tue, 14 May 2013 09:38:07 +0000 (09:38 +0000)]
[SystemZ] Remove bogus isAsmParserOnly
Marking instructions as isAsmParserOnly stops them from being disassembled.
However, in cases where separate asm and codegen versions exist, we actually
want to disassemble to the asm ones.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772
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Richard Sandiford [Tue, 14 May 2013 09:36:44 +0000 (09:36 +0000)]
[SystemZ] Match operands to fields by name rather than by order
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists. This isn't desirable
for disassembly, where the two are matched only by name. E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.
The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though. The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field. That's the approach taken in this patch.
Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771
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Richard Sandiford [Tue, 14 May 2013 09:28:21 +0000 (09:28 +0000)]
[SystemZ] Match operands to fields by name rather than by order
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists. This isn't desirable
for disassembly, where the two are matched only by name. E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.
The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though. The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field. That's the approach taken in this patch.
Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769
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Michael Gottesman [Tue, 14 May 2013 06:40:10 +0000 (06:40 +0000)]
Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181760
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Reed Kotler [Tue, 14 May 2013 06:00:01 +0000 (06:00 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759
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Reed Kotler [Tue, 14 May 2013 02:13:45 +0000 (02:13 +0000)]
Removed an unnamed namespace and forgot to make two of the functions inside
"static".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754
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