OSDN Git Service
Reid Kleckner [Wed, 29 May 2019 21:26:25 +0000 (21:26 +0000)]
[llvm-pdbutil] Dump inline call site line table annotations
This ports and improves on some existing llvm-readobj -codeview dumping
functionality that llvm-pdbutil lacked.
Helpful for comparing inline line tables between MSVC and clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362037
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Matt Arsenault [Wed, 29 May 2019 20:47:59 +0000 (20:47 +0000)]
LoopVersioningLICM: Respect convergent and noduplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362031
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Tim Northover [Wed, 29 May 2019 20:46:38 +0000 (20:46 +0000)]
Revert "IR: add optional type to 'byval' function parameters"
The IRLinker doesn't delve into the new byval attribute when mapping types, and
this breaks LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362029
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Roman Lebedev [Wed, 29 May 2019 20:11:53 +0000 (20:11 +0000)]
[LoopIdiomRecognize][NFC] Use DEBUG_TYPE, add LLVM_DEBUG() to runOnNoncountableLoop()
Split off from D61144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362022
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Pete Couperus [Wed, 29 May 2019 20:07:35 +0000 (20:07 +0000)]
[ARC] Cleanup ARCAsmPrinter.
Summary:
Remove unused getTargetStreamer.
Remove unused headers.
Reviewers: dantrushin
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362021
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Roman Lebedev [Wed, 29 May 2019 20:03:00 +0000 (20:03 +0000)]
UpdateTestChecks: Lanai triple support
Summary:
The assembly structure most resembles the SPARC pattern:
```
.globl f6 ! -- Begin function f6
.p2align 2
.type f6,@function
f6: ! @f6
.cfi_startproc
! %bb.0:
st %fp, [--%sp]
<...>
ld -8[%fp], %fp
.Lfunc_end0:
.size f6, .Lfunc_end0-f6
.cfi_endproc
! -- End function
```
Test being affected by upcoming patch, so regenerate it.
Reviewers: RKSimon, jpienaar
Reviewed By: RKSimon
Subscribers: jyknight, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362019
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Nico Weber [Wed, 29 May 2019 20:00:36 +0000 (20:00 +0000)]
gn build: Make it possible to build with coverage information
Differential Revision: https://reviews.llvm.org/D62508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362018
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Benjamin Kramer [Wed, 29 May 2019 19:24:19 +0000 (19:24 +0000)]
[DAGCombiner] Replace gathers with a zero mask with the passthru value
These can be created by the legalizer when splitting a larger gather.
See https://llvm.org/PR42055 for a motivating example.
Differential Revision: https://reviews.llvm.org/D62613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362015
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Tim Northover [Wed, 29 May 2019 19:12:48 +0000 (19:12 +0000)]
IR: add optional type to 'byval' function parameters
When we switch to opaque pointer types we will need some way to describe
how many bytes a 'byval' parameter should occupy on the stack. This adds
a (for now) optional extra type parameter.
If present, the type must match the pointee type of the argument.
Note to front-end maintainers: if this causes test failures, it's probably
because the "byval" attribute is printed after attributes without any parameter
after this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362012
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Chris Bieneman [Wed, 29 May 2019 18:37:49 +0000 (18:37 +0000)]
[CMake] [Runtimes] Set *_STANDALONE_BUILD
Summary:
The runtimes use `*_STANDALONE_BUILD=OFF` to signify that clang is an in-tree target. This is not the case with the runtime builds, so we really need this set to `ON`.
In order to resolve the issues phosek was having with checks, we should use checks that don't link. We can use compiler-rt's `try_compile_only` as a basis for that.
This patch is *required* to be able to run the runtime libraries check-* targets.
Reviewers: smeenai, phosek, compnerd
Reviewed By: phosek
Subscribers: mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362007
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Nikita Popov [Wed, 29 May 2019 18:37:13 +0000 (18:37 +0000)]
[InstCombine] Optimize always overflowing signed saturating add/sub
Based on the overflow direction information added in D62463, we can
now fold always overflowing signed saturating add/sub to signed min/max.
Differential Revision: https://reviews.llvm.org/D62544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362006
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Aakanksha Patil [Wed, 29 May 2019 18:20:11 +0000 (18:20 +0000)]
AMDGPU: Return address lowering
The patch computes the return address for the current function.
Differential revision: https://reviews.llvm.org/D59666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362001
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Stella Stamenova [Wed, 29 May 2019 18:07:39 +0000 (18:07 +0000)]
lit: modernize the lit configuration for the lit tests
Summary: This also normalizes the config feature that represents the windows platform to "system-windows" as opposed to having both "windows" and "system-windows"
Reviewers: asmith, probinson
Subscribers: delcypher, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361998
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Eugene Leviant [Wed, 29 May 2019 17:14:48 +0000 (17:14 +0000)]
Yet another attempt to fix buildbot after r361949
Looks like %p format specifier of createStringError behaves
differently on different platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361993
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Craig Topper [Wed, 29 May 2019 17:02:27 +0000 (17:02 +0000)]
[X86] Fix machineverifier error on avx512f-256-set0.mir
Previously the pass ran the entire llc pipeline which caused the IR to be recodegened.
This commit restricts it to just running the postrapseudos pass and checking the results of that instead of the final assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361991
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Matt Arsenault [Wed, 29 May 2019 16:59:48 +0000 (16:59 +0000)]
CallSiteSplitting: Respect convergent and noduplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361990
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Teresa Johnson [Wed, 29 May 2019 16:50:46 +0000 (16:50 +0000)]
[ThinLTO] Use original alias visibility when importing
Summary:
When we import an alias, we do so by making a clone of the aliasee. Just
as this clone uses the original alias name and linkage, it should also
use the same visibility (not the aliasee's visibility). Otherwise,
linker behavior is affected (e.g. if the aliasee was hidden, but the
alias is not, the resulting imported clone should not be hidden,
otherwise the linker will make the final symbol hidden which is
incorrect).
Reviewers: wmi
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361989
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Cameron McInally [Wed, 29 May 2019 16:50:14 +0000 (16:50 +0000)]
[NFC][InstCombine] Add a unary FNeg test to fsub.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361988
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Kevin P. Neal [Wed, 29 May 2019 16:29:31 +0000 (16:29 +0000)]
Partial revert of revert of r361827: Add constrained intrinsic tests for powerpc64le.
The powerpc64-"nonle" tests are removed. They fail because of a bug that
Drew is currently working on that affects multiple targets.
Submitted by: Drew Wock <drew.wock@sas.com>
Reviewed by: Hal Finkel, Kevin P. Neal
Approved by: Hal Finkel
Differential Revision: http://reviews.llvm.org/D62388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361985
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Cameron McInally [Wed, 29 May 2019 15:29:35 +0000 (15:29 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fpcast.ll and fpextend.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361973
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Cameron McInally [Wed, 29 May 2019 15:21:28 +0000 (15:21 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fsub.ll known-never-nan.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361971
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Sam McCall [Wed, 29 May 2019 15:02:16 +0000 (15:02 +0000)]
Qualify use of llvm::empty that's ambiguous with std::empty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361968
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Simon Atanasyan [Wed, 29 May 2019 14:59:07 +0000 (14:59 +0000)]
[mips] Use reg-exp in tests to tolerate register indexes changing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361966
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Simon Atanasyan [Wed, 29 May 2019 14:58:56 +0000 (14:58 +0000)]
[mips] Iterate over MSACtrlRegClass to reserve all MSA control registers. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361965
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Simon Atanasyan [Wed, 29 May 2019 14:58:50 +0000 (14:58 +0000)]
[mips] Use range-based for loops. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361964
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Simon Pilgrim [Wed, 29 May 2019 14:39:37 +0000 (14:39 +0000)]
Revert rL361944 from llvm/trunk :
[ADT] add iterator_range::empty()
........
Breaks windows buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361963
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Nico Weber [Wed, 29 May 2019 14:15:35 +0000 (14:15 +0000)]
gn build: Merge r361953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361961
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Sjoerd Meijer [Wed, 29 May 2019 13:41:57 +0000 (13:41 +0000)]
[ARM] Split predicates out into their own .td file
The new ARMPredicates.td is included from ARM.td, early enough that
the predicate definitions are already in scope when ARMSchedule.td is
included. This will make it possible to refer to them in
UnsupportedFeatures fields of scheduling models.
NFC: the chunk of Tablegen being moved here is copied and pasted
verbatim.
Patch by: Simon Tatham
Differential Revision: https://reviews.llvm.org/D60693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361958
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Matt Arsenault [Wed, 29 May 2019 13:14:39 +0000 (13:14 +0000)]
SpeculateAroundPHIs: Respect convergent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361957
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Matt Arsenault [Wed, 29 May 2019 13:14:35 +0000 (13:14 +0000)]
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
This has been a mandatory part of the build for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361956
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Eugene Leviant [Wed, 29 May 2019 12:26:23 +0000 (12:26 +0000)]
Attempt to fix buildbot after r361949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361954
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Graham Hunter [Wed, 29 May 2019 12:22:54 +0000 (12:22 +0000)]
[SVE][IR] Scalable Vector IR Type
* Adds a 'scalable' flag to VectorType
* Adds an 'ElementCount' class to VectorType to pass (possibly scalable) vector lengths, with overloaded operators.
* Modifies existing helper functions to use ElementCount
* Adds support for serializing/deserializing to/from both textual and bitcode IR formats
* Extends the verifier to reject global variables of scalable types
* Updates documentation
See the latest version of the RFC here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124396.html
Reviewers: rengolin, lattner, echristo, chandlerc, hfinkel, rkruppe, samparker, SjoerdMeijer, greened, sebpop
Reviewed By: hfinkel, sebpop
Differential Revision: https://reviews.llvm.org/D32530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361953
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Andrea Di Biagio [Wed, 29 May 2019 11:38:27 +0000 (11:38 +0000)]
[MCA] Refactor class LSUnit. NFCI
This should be the last bit of refactoring in preparation for a patch that would
finally fix PR37494.
This patch introduces the concept of memory dependency groups (class
MemoryGroup) and "Load/Store Unit token" (LSUToken) to track the status of a
memory operation.
A MemoryGroup is a node of a memory dependency graph. It is used internally to
classify memory operations based on the memory operations they depend on. Let I
and J be two memory operations, we say that I and J equivalent (for the purpose
of mapping instructions to memory dependency groups) if the set of memory
operations they depend depend on is identical.
MemoryGroups are identified by so-called LSUToken (a unique group identifier
assigned by the LSUnit to every group). When an instruction I is dispatched to
the LSUnit, the LSUnit maps I to a group, and then returns a LSUToken.
LSUTokens are used by class Scheduler to track memory dependencies.
This patch simplifies the LSUnit interface and moves most of the implementation
details to its base class (LSUnitBase). There is no user visible change to the
output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361950
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Eugene Leviant [Wed, 29 May 2019 11:37:16 +0000 (11:37 +0000)]
[llvm-objcopy] Implement IHEX writer
Differential revision: https://reviews.llvm.org/D60270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361949
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George Rimar [Wed, 29 May 2019 11:01:07 +0000 (11:01 +0000)]
[llvm-readobj] - Repair the test case.
I forgot to change the test tag in r361932.
Now it is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361945
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Sam McCall [Wed, 29 May 2019 10:39:01 +0000 (10:39 +0000)]
[ADT] add iterator_range::empty()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361944
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George Rimar [Wed, 29 May 2019 10:31:46 +0000 (10:31 +0000)]
[llvm-readelf] - Allow dumping of the .dynamic section even if there is no PT_DYNAMIC header.
It is now possible after D61937 was landed and was discussed
in it's review comments. It is not consistent with GNU, which
does not output .dynamic section content in this case for
no visible reason.
Differential revision: https://reviews.llvm.org/D62179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361943
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Cullen Rhodes [Wed, 29 May 2019 09:03:27 +0000 (09:03 +0000)]
[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
Summary:
Patch adds support for the following instructions:
* EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR
Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361936
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Cullen Rhodes [Wed, 29 May 2019 08:53:06 +0000 (08:53 +0000)]
[AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add
Summary:
Patch adds support for the indexed and unpredicated vectors forms of the
FMLALB, FMLALT, FMLSLB and FMLSLT instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361935
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Cullen Rhodes [Wed, 29 May 2019 08:40:33 +0000 (08:40 +0000)]
[AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise Group
Summary:
Patch adds support for the following instructions:
SVE2 floating-point pairwise operations:
* FADDP, FMAXNMP, FMINNMP, FMAXP, FMINP
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361933
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George Rimar [Wed, 29 May 2019 08:28:47 +0000 (08:28 +0000)]
[llvm-readobj/llvm-readelf] - Simplify the elf-versioninfo.test test case.
This removes 2 precompiled objects from the test case and replaces
them with a single YAML. That allowed to simplify and clean up the test,
remove excessive checks.
Differential revision: https://reviews.llvm.org/D62529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361932
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Fangrui Song [Wed, 29 May 2019 06:18:34 +0000 (06:18 +0000)]
[llvm-readobj] -u: don't crash when dumping SHT_ARM_EXIDX if .symtab doesn't exist
Reviewed By: kongyi
Differential Revision: https://reviews.llvm.org/D62567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361929
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Richard Trieu [Wed, 29 May 2019 04:09:32 +0000 (04:09 +0000)]
Inline a variable into debug section to fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361927
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Richard Trieu [Wed, 29 May 2019 03:43:01 +0000 (03:43 +0000)]
Inline value into debug statement to avoid unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361924
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Peter Collingbourne [Wed, 29 May 2019 03:29:01 +0000 (03:29 +0000)]
Add IR support, ELF section and user documentation for partitioning feature.
The partitioning feature was proposed here:
http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html
This is mostly just documentation. The feature itself will be contributed
in subsequent patches.
Differential Revision: https://reviews.llvm.org/D60242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361923
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Peter Collingbourne [Wed, 29 May 2019 03:28:51 +0000 (03:28 +0000)]
IR: Give the TypeAllocator a more generic name and start using it for section names as well. NFCI.
This prepares us to start using it for partition names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361922
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Jinsong Ji [Wed, 29 May 2019 03:02:59 +0000 (03:02 +0000)]
Support resource tracking with InstrSchedModel
The current design use DFA to do resource tracking in SMS,
and DFA only support InstrItins, and also has scaling limitation.
This patch extend SMS to allow Subtarget to use ProcResource in
InstrSchedModel instead.
Differential Revision: https://reviews.llvm.org/D62163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361919
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Pengfei Wang [Wed, 29 May 2019 02:49:59 +0000 (02:49 +0000)]
Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"
This reverts commit
c1b3716614bc0a107e6f41a7d3d503baefad8a5b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361918
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Pengfei Wang [Wed, 29 May 2019 02:20:37 +0000 (02:20 +0000)]
[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to
avoid static check fail
RegClassOrBank is an object of RegClassOrRegBank, which is defined as
using llvm::RegClassOrRegBank = typedef PointerUnion<const
TargetRegisterClass *, const RegisterBank *>
so control flow can not get here. Use ""llvm_unreachable" here to avoid
"null pointer" confusion.
Patch by Shengchen Kan (skan)
Differential Revision: https://reviews.llvm.org/D62006
Signed-off-by: pengfei <pengfei.wang@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361912
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Fangrui Song [Wed, 29 May 2019 02:02:59 +0000 (02:02 +0000)]
[X86] Fix x86-64 call *foo@tlsdesc(%rax) and support R_386_TLSGOTDESC R_386_TLS_DESC_CALL
D18885 emitted 5 bytes for call *foo@tlsdesc(%rax). It should use the
2-byte form instead and let R_X86_64_TLSDESC_CALL apply to the beginning
of the call instruction.
The 2-byte form was deliberately chosen to make ->LE and ->IE relaxation work:
0: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # 7 <.text+0x7>
3: R_X86_64_GOTPC32_TLSDESC a-0x4
7: ff 10 callq *(%rax)
7: R_X86_64_TLSDESC_CALL a
=>
0: 48 c7 c0 fc ff ff ff mov $0xfffffffffffffffc,%rax
7: 66 90 xchg %ax,%ax
Also change the symbol type to STT_TLS when VK_TLSCALL or VK_TLSDESC is
seen.
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D62512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361910
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Sanjay Patel [Wed, 29 May 2019 01:37:44 +0000 (01:37 +0000)]
[AArch64] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361908
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 29 May 2019 01:35:10 +0000 (01:35 +0000)]
[AArch64] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361906
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 29 May 2019 01:06:00 +0000 (01:06 +0000)]
[WebAssembly] Add signatures for RINT builtins
Reviewers: azakai, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361904
91177308-0d34-0410-b5e6-
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Quentin Colombet [Tue, 28 May 2019 23:43:12 +0000 (23:43 +0000)]
[RegUsageInfoCollector] Don't mark as saved registers that don't have subregister lanes
To determine the list of clobbered registers, the RegUsageInfoCollector pass
uses the list of callee saved registers provided by the target and then augments
it with the list of registers which have all their subregisters saved. It then
basically does the difference between all the registers and the saved registers
to come up with what is clobbered (plus it checks that the register is defined
within that functions).
The patch fixes a bug where when register does not have any subregister lane,
hence when checking if any of its subregister are not saved, we would find none
and think the register is saved as well.
That's obviously wrong.
The code was actually kind of checking for something like that with the
CoveredBySubRegs bit. What this bit says is that a register is completely
covered by its subregisters.
We required that this bit was set, to check that a register was saved by its
subregister lanes, since without this bit, we potentially would miss to check
some part of the register.
However, this bit is used de facto on registers that don't have any
subregisters (e.g., on ARM) and the code was not prepared for that.
This patch fixes this by checking that a register has subregisters before
declaring it saved when none of its lanes are modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361901
91177308-0d34-0410-b5e6-
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Lang Hames [Tue, 28 May 2019 23:35:44 +0000 (23:35 +0000)]
[ORC] Track JIT symbol states more explicitly.
Prior to this patch, JITDylibs inferred symbol states (whether a symbol was
newly added, materializing, resolved, or ready to run) via a combination of (1)
bits in the JITSymbolFlags member, and (2) the state of some internal JITDylib
data structures. This patch explicitly tracks symbol states by adding a new
SymbolState member to the symbol table entries, and removing the 'Lazy' and
'Materializing' bits from JITSymbolFlags. This is a first step towards adding
additional states representing initialization phases (e.g. eh-frame registration,
registration with the language runtime, and static initialization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361899
91177308-0d34-0410-b5e6-
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Alexander Shaposhnikov [Tue, 28 May 2019 23:22:12 +0000 (23:22 +0000)]
[tools] Introduce llvm-lipo
This diff starts the implementation of llvm-lipo
which is supposed to be a drop-in replacement for the well-known tool lipo.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D61927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361896
91177308-0d34-0410-b5e6-
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Jessica Paquette [Tue, 28 May 2019 22:52:49 +0000 (22:52 +0000)]
[AArch64][GlobalISel] Select FCMPSri/FCMPDri when comparing against 0.0
Add support for selecting FCMPSri and FCMPDri when comparing against 0.0, and
factor out opcode selection for G_FCMP into its own function.
Add a test to show that we don't do this with other immediates.
Differential Revision: https://reviews.llvm.org/D62539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361888
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Tue, 28 May 2019 22:09:12 +0000 (22:09 +0000)]
[WebAssembly] Support for atomic fences
Summary:
This adds support for translation of LLVM IR fence instruction. We
convert a singlethread fence to a pseudo compiler barrier which becomes
0 instructions in final binary, and a thread fence to an idempotent
atomicrmw instruction to a memory address.
Reviewers: dschuff, jfb, sunfish, tlively
Subscribers: sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D50277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361884
91177308-0d34-0410-b5e6-
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Rong Xu [Tue, 28 May 2019 21:45:56 +0000 (21:45 +0000)]
[PGO] Handle cases of failing to split critical edges
Fix PR41279 where critical edges to EHPad are not split.
The fix is to not instrument those critical edges. We used to be able to know
the size of counters right after MST is computed. With this, we have to
pre-collect the instrument BBs to know the size, and then instrument them.
Differential Revision: https://reviews.llvm.org/D62439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361882
91177308-0d34-0410-b5e6-
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Nikita Popov [Tue, 28 May 2019 21:28:24 +0000 (21:28 +0000)]
Revert "[CorrelatedValuePropagation] Fix prof branch_weights metadata handling for SwitchInst"
This reverts commit
53f2f3286572cb879b3861d7c15480e4d830dd3b.
As reported on D62126, this causes assertion failures if the switch
has incorrect branch_weights metadata, which may happen as a result
of other transforms not handling it correctly yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361881
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Tue, 28 May 2019 21:18:34 +0000 (21:18 +0000)]
AMDGPU: Temporary drop s_mul_hi_i/u32 patterns
It introduces performance regressions in several applications.
This has already been submitted downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361879
91177308-0d34-0410-b5e6-
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Adhemerval Zanella [Tue, 28 May 2019 21:04:29 +0000 (21:04 +0000)]
[AArch64] Handle ISD::LRINT and ISD::LLRINT
This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.
Reviewed By: SjoerdMeijer, mstorsjo
Differential Revision: https://reviews.llvm.org/D62018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361877
91177308-0d34-0410-b5e6-
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Adhemerval Zanella [Tue, 28 May 2019 20:47:44 +0000 (20:47 +0000)]
[CodeGen] Add lrint/llrint builtins
This patch add the ISD::LRINT and ISD::LLRINT along with new
intrinsics. The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an interger.
The idea is to optimize lrint/llrint generation for AArch64
in a subsequent patch. Current semantic is just route it to libm
symbol.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D62017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361875
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 20:40:10 +0000 (20:40 +0000)]
[DAGCombine] (x - C) - y -> (x - y) - C fold. Try 2
Summary:
Again only vectors affected. Frustrating. Let me take a look into that..
https://rise4fun.com/Alive/AAq
This is a recommit, originally committed in rL361856, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: javed.absar, JDevlieghere, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361874
91177308-0d34-0410-b5e6-
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Roman Lebedev [Tue, 28 May 2019 20:40:03 +0000 (20:40 +0000)]
[DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 2
Summary:
This prevents regressions in next patch,
and somewhat recovers from the regression to AMDGPU test in D62223.
It is indeed not great that we leave vector decrement,
don't transform it into vector add all-ones..
https://rise4fun.com/Alive/ZRl
This is a recommit, originally committed in rL361855, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel, arsenm
Reviewed By: RKSimon, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361873
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 20:39:55 +0000 (20:39 +0000)]
[DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold. Try 2
Summary:
Direct sibling of D62223 patch.
While i don't have a direct motivational pattern for this,
it would seem to make sense to handle both patterns (or none),
for symmetry?
The aarch64 changes look neutral;
sparc and systemz look like improvement (one less instruction each);
x86 changes - 32bit case improves, 64bit case shows that LEA no longer
gets constructed, which may be because that whole test is `-mattr=+slow-lea,+slow-3ops-lea`
https://rise4fun.com/Alive/ffh
This is a recommit, originally committed in rL361853, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, jyknight, javed.absar, kristof.beyls, fedor.sergeev, jrtc27, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361872
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 20:39:39 +0000 (20:39 +0000)]
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 2
Summary:
The main motivation is shown by all these `neg` instructions that are now created.
In particular, the `@reg32_lshr_by_negated_unfolded_sub_b` test.
AArch64 test changes all look good (`neg` created), or neutral.
X86 changes look neutral (vectors), or good (`neg` / `xor eax, eax` created).
I'm not sure about `X86/ragreedy-hoist-spill.ll`, it looks like the spill
is now hoisted into preheader (which should still be good?),
2 4-byte reloads become 1 8-byte reload, and are elsewhere,
but i'm not sure how that affects that loop.
I'm unable to interpret AMDGPU change, looks neutral-ish?
This is hopefully a step towards solving [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]].
https://rise4fun.com/Alive/pkdq (we are missing more patterns, i'll submit them later)
This is a recommit, originally committed in rL361852, but reverted
to investigate test-suite compile-time hangs.
Reviewers: craig.topper, RKSimon, spatel, arsenm
Reviewed By: RKSimon
Subscribers: bjope, qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361871
91177308-0d34-0410-b5e6-
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David Blaikie [Tue, 28 May 2019 20:22:16 +0000 (20:22 +0000)]
Fix GDB pretty printer for Optional after r354246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361870
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Tue, 28 May 2019 20:01:25 +0000 (20:01 +0000)]
Change ELF tools to allow multiple sections per file.
This is how multi-partition combined output files are going to look. If we
see multiple sections, the tools will just read the first one.
Differential Revision: https://reviews.llvm.org/D62349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361869
91177308-0d34-0410-b5e6-
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Michael Liao [Tue, 28 May 2019 19:37:09 +0000 (19:37 +0000)]
[AMDGPU] Correct the handling of inlineasm output registers.
Summary:
- There's a regression due to the cross-block RC assignment. Use the
proper way to derive the output register RC in inline asm.
Reviewers: rampitec, alex-t
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, eraman, hiraditya, llvm-commits, yaxunl
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361868
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 19:04:21 +0000 (19:04 +0000)]
Revert DAGCombine "hoist binop with const" folds
Appear to introduce test-suite compile-time hang.
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/22825
This reverts r361852,r361853,r361854,r361855,r361856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361865
91177308-0d34-0410-b5e6-
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Nikita Popov [Tue, 28 May 2019 18:59:28 +0000 (18:59 +0000)]
[InstCombine] Add tests for signed saturating always overflow; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361864
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikita Popov [Tue, 28 May 2019 18:59:21 +0000 (18:59 +0000)]
[InstCombine] Clean up saturing math overflow optimizations; NFC
Reduce duplication and make it easier to handle signed
always-overflows conditions in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361863
91177308-0d34-0410-b5e6-
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Roman Lebedev [Tue, 28 May 2019 18:31:36 +0000 (18:31 +0000)]
[NFC][MIPS] Autogenerater madd-msub.ll test
Being affected by upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361860
91177308-0d34-0410-b5e6-
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Nikita Popov [Tue, 28 May 2019 18:08:31 +0000 (18:08 +0000)]
[ValueTracking][ConstantRange] Distinguish low/high always overflow
In order to fold an always overflowing signed saturating add/sub,
we need to know in which direction the always overflow occurs.
This patch splits up AlwaysOverflows into AlwaysOverflowsLow and
AlwaysOverflowsHigh to pass through this information (but it is
not used yet).
Differential Revision: https://reviews.llvm.org/D62463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361858
91177308-0d34-0410-b5e6-
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Nikita Popov [Tue, 28 May 2019 18:08:06 +0000 (18:08 +0000)]
[IR] Add SaturatingInst and BinaryOpIntrinsic classes
Based on the suggestion in D62447, this adds a SaturatingInst class
that represents the saturating add/sub family of intrinsics. It
exposes the same interface as WithOverflowInst, for this reason I
have also added a common base class BinaryOpIntrinsic that holds the
actual implementation code and will be useful in some places handling
both overflowing and saturating math.
Differential Revision: https://reviews.llvm.org/D62466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361857
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 17:54:21 +0000 (17:54 +0000)]
[DAGCombine] (x - C) - y -> (x - y) - C fold
Summary:
Again only vectors affected. Frustrating. Let me take a look into that..
https://rise4fun.com/Alive/AAq
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: javed.absar, JDevlieghere, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361856
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 17:54:13 +0000 (17:54 +0000)]
[DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold
Summary:
This prevents regressions in next patch,
and somewhat recovers from the regression to AMDGPU test in D62223.
It is indeed not great that we leave vector decrement,
don't transform it into vector add all-ones..
https://rise4fun.com/Alive/ZRl
Reviewers: RKSimon, craig.topper, spatel, arsenm
Reviewed By: RKSimon, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361855
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 17:54:04 +0000 (17:54 +0000)]
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold
Summary:
Only vector tests are being affected here,
since subtraction by scalar constant is rewritten
as addition by negated constant.
No surprising test changes.
https://rise4fun.com/Alive/pbT
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361854
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 17:53:54 +0000 (17:53 +0000)]
[DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold
Summary:
Direct sibling of D62223 patch.
While i don't have a direct motivational pattern for this,
it would seem to make sense to handle both patterns (or none),
for symmetry?
The aarch64 changes look neutral;
sparc and systemz look like improvement (one less instruction each);
x86 changes - 32bit case improves, 64bit case shows that LEA no longer
gets constructed, which may be because that whole test is `-mattr=+slow-lea,+slow-3ops-lea`
https://rise4fun.com/Alive/ffh
Reviewers: RKSimon, craig.topper, spatel, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, jyknight, javed.absar, kristof.beyls, fedor.sergeev, jrtc27, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361853
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 28 May 2019 17:53:43 +0000 (17:53 +0000)]
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold
Summary:
The main motivation is shown by all these `neg` instructions that are now created.
In particular, the `@reg32_lshr_by_negated_unfolded_sub_b` test.
AArch64 test changes all look good (`neg` created), or neutral.
X86 changes look neutral (vectors), or good (`neg` / `xor eax, eax` created).
I'm not sure about `X86/ragreedy-hoist-spill.ll`, it looks like the spill
is now hoisted into preheader (which should still be good?),
2 4-byte reloads become 1 8-byte reload, and are elsewhere,
but i'm not sure how that affects that loop.
I'm unable to interpret AMDGPU change, looks neutral-ish?
This is hopefully a step towards solving [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]].
https://rise4fun.com/Alive/pkdq (we are missing more patterns, i'll submit them later)
Reviewers: craig.topper, RKSimon, spatel, arsenm
Reviewed By: RKSimon
Subscribers: bjope, qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361852
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 28 May 2019 17:37:58 +0000 (17:37 +0000)]
Revert "[x86] split 256-bit store of concatenated vectors"
This reverts commit
d5a8637072f4c556b88156bd2f6237a2ead47d31.
Most likely suspect for this bot failure:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-avx2-linux/builds/9684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361850
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 28 May 2019 16:46:02 +0000 (16:46 +0000)]
AMDGPU: Don't enable all lanes with non-CSR VGPR spills
If the only VGPRs used for SGPR spilling were not CSRs, this was
enabling all laness and immediately restoring exec. This is the usual
situation in leaf functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361848
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Tue, 28 May 2019 16:29:39 +0000 (16:29 +0000)]
[AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.
Summary:
- Don't treat the use of a scalar register as `vreg_1` an VGPR usage.
Otherwise, that promotes that scalar register into vector one, which
breaks the assumption that scalar register holds the lane mask.
- The issue is triggered in a complicated case, where if the uses of
that (lane mask) scalar register is legalized firstly before its
definition, e.g., due to the mismatch block placement and its
topological order or loop. In that cases, the legalization of PHI
introduces the use of that scalar register as `vreg_1`.
Reviewers: rampitec, nhaehnle, arsenm, alex-t
Subscribers: kzhuravl, jvesely, wdng, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361847
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Tatham [Tue, 28 May 2019 16:13:20 +0000 (16:13 +0000)]
[ARM] Replace fp-only-sp and d16 with fp64 and d32.
Those two subtarget features were awkward because their semantics are
reversed: each one indicates the _lack_ of support for something in
the architecture, rather than the presence. As a consequence, you
don't get the behavior you want if you combine two sets of feature
bits.
Each SubtargetFeature for an FP architecture version now comes in four
versions, one for each combination of those options. So you can still
say (for example) '+vfp2' in a feature string and it will mean what
it's always meant, but there's a new string '+vfp2d16sp' meaning the
version without those extra options.
A lot of this change is just mechanically replacing positive checks
for the old features with negative checks for the new ones. But one
more interesting change is that I've rearranged getFPUFeatures() so
that the main FPU feature is appended to the output list *before*
rather than after the features derived from the Restriction field, so
that -fp64 and -d32 can override defaults added by the main feature.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361845
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Fangrui Song [Tue, 28 May 2019 16:11:56 +0000 (16:11 +0000)]
[AArch64] Delete unused VariantKind in AArch64MCExpr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361844
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David Greene [Tue, 28 May 2019 15:37:01 +0000 (15:37 +0000)]
[X86-64] Fix 256-bit SET0 lowering for non-VLX targets
If we don't have VLX then 256-bit SET0 should be lowered
to VPXOR with ZMM registers. This restores functionality
accidentally removed by r309926.
Differential Revision: https://reviews.llvm.org/D62415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361843
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Nico Weber [Tue, 28 May 2019 15:30:04 +0000 (15:30 +0000)]
llvm-undname: Support demangling char8_t
Ports clang's mangling support added in r354633 to llvm-undname.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361839
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Alexandre Ganea [Tue, 28 May 2019 15:04:39 +0000 (15:04 +0000)]
Revert r361826, as it still breaks LLDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361837
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Nico Weber [Tue, 28 May 2019 14:54:49 +0000 (14:54 +0000)]
llvm-undname: Add support for local static thread guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361835
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Jason Liu [Tue, 28 May 2019 14:37:59 +0000 (14:37 +0000)]
[XCOFF] Implement parsing symbol table for xcoffobjfile and output as yaml format
Summary:
This patch implement parsing symbol table for xcoffobjfile and
output as yaml format. Parsing auxiliary entries of a symbol
will be in a separate patch.
The XCOFF object file (aix_xcoff.o) used in the test comes from
-bash-4.2$ cat test.c
extern int i;
extern int TestforXcoff;
int main()
{
i++;
TestforXcoff--;
}
Patch by DiggerLin
Reviewers: sfertile, hubert.reinterpretcast, MaskRay, daltenty
Differential Revision: https://reviews.llvm.org/D61532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361832
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Kevin P. Neal [Tue, 28 May 2019 14:37:45 +0000 (14:37 +0000)]
Revert 361827. It broke the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361831
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Ilya Biryukov [Tue, 28 May 2019 14:23:00 +0000 (14:23 +0000)]
gn build: make clangd depend on clang resource headers
Summary:
clangd needs them to function properly, even though they are not
strictly required for the build.
Reviewers: thakis
Reviewed By: thakis
Subscribers: MaskRay, jkorous, arphaman, llvm-commits, kadircet
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361828
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Kevin P. Neal [Tue, 28 May 2019 14:17:48 +0000 (14:17 +0000)]
Add constrained intrinsic tests for powerpc64 and powerpc64le.
Submitted by: Drew Wock
Reviewed by: Hal Finkel
Approved by: Hal Finkel
Differential Revision: https://reviews.llvm.org/D62388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361827
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Alexandre Ganea [Tue, 28 May 2019 14:14:48 +0000 (14:14 +0000)]
[CMake] Default options for faster executables on MSVC
Differential Revision: https://reviews.llvm.org/D55056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361826
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Sanjay Patel [Tue, 28 May 2019 13:54:17 +0000 (13:54 +0000)]
[x86] split 256-bit store of concatenated vectors
This shows up as a side issue to the main problem for the AVX target example from PR37428:
https://bugs.llvm.org/show_bug.cgi?id=37428 - https://godbolt.org/z/7tpRa3
But as we can see in the pile of existing test diffs, it's actually a widespread problem
that affects any AVX or later target. Apart from a couple of oddballs, I think these are
all improvements for the reasons stated in the code comment: we do not want to enable YMM
unnecessarily (avoid vzeroupper and frequency throttling) and some cores split 256-bit
stores anyway.
We could say that MergeConsecutiveStores() is going overboard on some of these examples,
but that won't solve the problem completely. But that is the reason I'm proposing this as
a lowering rather than a combine: we will infinite loop fighting the merge code if we try
this earlier.
Differential Revision: https://reviews.llvm.org/D62498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361822
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Simon Pilgrim [Tue, 28 May 2019 13:46:26 +0000 (13:46 +0000)]
[DAG] LegalizeVectorTypes - reduce scope of local variables. NFCI.
Move the element index/count variables into the block where they are actually used - appeases cppcheck and helps avoid shadow variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361821
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David Stenberg [Tue, 28 May 2019 13:23:25 +0000 (13:23 +0000)]
Stop undef fragments from closing non-overlapping fragments
Summary:
When DwarfDebug::buildLocationList() encountered an undef debug value,
it would truncate all open values, regardless if they were overlapping or
not. This patch fixes so that it only does that for overlapping fragments.
This change unearthed a bug that I had introduced in D57511,
which I have fixed in this patch. The code in DebugHandlerBase that
changes labels for parameter debug values could break DwarfDebug's
assumption that the labels for the entries in the debug value history
are monotonically increasing. Before this patch, that bug could result
in location list entries whose ending address was lower than the
beginning address, and with the changes for undef debug values that this
patch introduces it could trigger an assertion, due to attempting to
emit location list entries with empty ranges. A reproducer for the bug
is added in param-reg-const-mix.mir.
Reviewers: aprantl, jmorse, probinson
Reviewed By: aprantl
Subscribers: javed.absar, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D62379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361820
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Matt Arsenault [Tue, 28 May 2019 13:08:31 +0000 (13:08 +0000)]
MIR: Fix printer crashing on dead CSR frame indexes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361819
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Sjoerd Meijer [Tue, 28 May 2019 13:04:47 +0000 (13:04 +0000)]
Follow up of r361810: test case fix attempt for Windows builder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361817
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