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Sander de Smalen [Wed, 24 Jan 2018 10:30:23 +0000 (10:30 +0000)]
Fixes Sphinx issue ('undefined label') introduced in r323313.
(and also slightly reformatted the related lines to look better in
the rendered HTML)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323317
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Igor Laevsky [Wed, 24 Jan 2018 09:57:17 +0000 (09:57 +0000)]
[llvm-opt-fuzzer] Add couple of popular passes
Differential Revision: https://reviews.llvm.org/D42410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323314
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Sander de Smalen [Wed, 24 Jan 2018 09:56:07 +0000 (09:56 +0000)]
[Metadata] Extend 'count' field of DISubrange to take a metadata node
Summary:
This patch extends the DISubrange 'count' field to take either a
(signed) constant integer value or a reference to a DILocalVariable
or DIGlobalVariable.
This is patch [1/3] in a series to extend LLVM's DISubrange Metadata
node to support debugging of C99 variable length arrays and vectors with
runtime length like the Scalable Vector Extension for AArch64. It is
also a first step towards representing more complex cases like arrays
in Fortran.
Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie
Reviewed By: aprantl
Subscribers: rnk, probinson, fhahn, aemerson, rengolin, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323313
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Sven van Haastregt [Wed, 24 Jan 2018 09:53:47 +0000 (09:53 +0000)]
[DAGCombiner] Bail out if vector size is not a multiple
For the included test case, the DAG transformation
concat_vectors(scalar, undef) -> scalar_to_vector(sclr)
would attempt to create a v2i32 vector for a v9i8
concat_vector. Bail out to avoid creating a bitcast with
mismatching sizes later on.
Differential Revision: https://reviews.llvm.org/D42379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323312
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David Chisnall [Wed, 24 Jan 2018 09:53:01 +0000 (09:53 +0000)]
[Doc] Guideline on adding exception handling support for a target
Summary:
This is the first attempt to write down a guideline on adding exception handling support for a target. The content basically bases on the discussion on [1]. If you guys know who is exception handling expert, please add him as the reviewer. Thanks.
[1] http://lists.llvm.org/pipermail/llvm-dev/2018-January/120405.html
Reviewers: t.p.northover, theraven, nemanjai
Reviewed By: theraven
Subscribers: sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D42178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323311
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Max Kazantsev [Wed, 24 Jan 2018 07:51:41 +0000 (07:51 +0000)]
[NFC] Remove overconfident assert from IRCE
This patch removes assert that SCEV is able to prove that a value is
non-negative. In fact, SCEV can sometimes be unable to do this because
its cache does not update properly. This assert will be returned once this
problem is resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323309
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Martin Storsjo [Wed, 24 Jan 2018 06:40:11 +0000 (06:40 +0000)]
[ARM] Call __chkstk for dynamic stack allocation in all windows environments
This matches what MSVC does for alloca() function calls on ARM.
Even if MSVC doesn't support VLAs at the language level, it does
support the alloca function.
On the clang level, both the _alloca() (when emulating MSVC, which is
what the alloca() function expands to) and __builtin_alloca() builtin
functions, and VLAs, map to the same LLVM IR "alloca" function - so
within LLVM they're not distinguishable from each other.
Differential Revision: https://reviews.llvm.org/D42292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323308
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Martin Storsjo [Wed, 24 Jan 2018 06:40:04 +0000 (06:40 +0000)]
[GlobalMerge] Don't merge dllexport globals
Merging such globals loses the dllexport attribute. Add a test
to check that normal globals still are merged.
Differential Revision: https://reviews.llvm.org/D42127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323307
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Craig Topper [Wed, 24 Jan 2018 05:32:51 +0000 (05:32 +0000)]
[X86] Move 'Y' to correct place in FMA4 regular expression in Znver1 scheduler model.
I think these instructions used to be named differently and the regular expression reflected that. I guess we must have correct itinerary information that made this not matter for the scheduler test?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323305
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Craig Topper [Wed, 24 Jan 2018 05:14:39 +0000 (05:14 +0000)]
[X86] Rename 256-bit VFRCZ instructions to have the Y before the rr/rm to match other instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323304
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Craig Topper [Wed, 24 Jan 2018 05:14:33 +0000 (05:14 +0000)]
[X86] Remove redundant regular expression from the Znver1 scheduler model. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323303
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Hiroshi Inoue [Wed, 24 Jan 2018 05:04:35 +0000 (05:04 +0000)]
[NFC] fix trivial typos in comments
"the the" -> "the"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323302
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Craig Topper [Wed, 24 Jan 2018 04:51:17 +0000 (04:51 +0000)]
[X86] Use ISD::SIGN_EXTEND instead of X86ISD::VSEXT for mask to xmm/ymm/zmm conversion
There are a couple tricky things with this patch.
I had to add an override of isVectorLoadExtDesirable to stop DAG combine from combining sign_extend with loads after legalization since we legalize sextload using a load+sign_extend. Overriding this hook actually prevents a lot sextloads from being created in the first place.
I also had to add isel patterns because DAG combine blindly combines sign_extend+truncate to a smaller sign_extend which defeats what legalization was trying to do.
Differential Revision: https://reviews.llvm.org/D42407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323301
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Jakub Kuderski [Wed, 24 Jan 2018 02:40:35 +0000 (02:40 +0000)]
[Dominators] Introduce DomTree verification levels
Summary:
Currently, there are 2 ways to verify a DomTree:
* `DT.verify()` -- runs full tree verification and checks all the properties and gives a reason why the tree is incorrect. This is run by when EXPENSIVE_CHECKS are enabled or when `-verify-dom-info` flag is set.
* `DT.verifyDominatorTree()` -- constructs a fresh tree and compares it against the old one. This does not check any other tree properties (DFS number, levels), nor ensures that the construction algorithm is correct. Used by some passes inside assertions.
This patch introduces DomTree verification levels, that try to close the gape between the two ways of checking trees by introducing 3 verification levels:
- Full -- checks all properties, but can be slow (O(N^3)). Used when manually requested (e.g. `assert(DT.verify())`) or when `-verify-dom-info` is set.
- Basic -- checks all properties except the sibling property, and compares the current tree with a freshly constructed one instead. This should catch almost all errors, but does not guarantee that the construction algorithm is correct. Used when EXPENSIVE checks are enabled.
- Fast -- checks only basic properties (reachablility, dfs numbers, levels, roots), and compares with a fresh tree. This is meant to replace the legacy `DT.verifyDominatorTree()` and in my tests doesn't cause any noticeable performance impact even in the most pessimistic examples.
When used to verify dom tree wrapper pass analysis on sqlite3, the 3 new levels make `opt -O3` take the following amount of time on my machine:
- no verification: 8.3s
- `DT.verify(VerificationLevel::Fast)`: 10.1s
- `DT.verify(VerificationLevel::Basic)`: 44.8s
- `DT.verify(VerificationLevel::Full)`: 1m 46.2s
(and the previous `DT.verifyDominatorTree()` is within the noise of the Fast level)
This patch makes `DT.verifyDominatorTree()` pick between the 3 verification levels depending on EXPENSIVE_CHECKS and `-verify-dom-info`.
Reviewers: dberlin, brzycki, davide, grosser, dmgreen
Reviewed By: dberlin, brzycki
Subscribers: MatzeB, llvm-commits
Differential Revision: https://reviews.llvm.org/D42337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323298
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Rafael Espindola [Wed, 24 Jan 2018 02:11:18 +0000 (02:11 +0000)]
Don't assume a null GV is local for ELF and MachO.
This is already a simplification, and should help with avoiding a plt
reference when calling an intrinsic with -fno-plt.
With this change we return false for null GVs, so the caller only
needs to check the new metadata to decide if it should use foo@plt or
*foo@got.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323297
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Eric Christopher [Wed, 24 Jan 2018 01:51:57 +0000 (01:51 +0000)]
Remove set but unused variable IsUndef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323295
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Zvi Rackover [Wed, 24 Jan 2018 01:36:40 +0000 (01:36 +0000)]
X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
Summary:
AVX512BW adds support for variable shift amount for 16-bit element
vectors.
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: rengolin, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D42437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323292
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Aditya Nandakumar [Wed, 24 Jan 2018 01:35:26 +0000 (01:35 +0000)]
[GISel]: Remove redundant copies at the end of ISel
https://reviews.llvm.org/D42402
A lot of these copies are useless (copies b/w VRegs having the same
regclass) and should be cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323291
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Sam Clegg [Wed, 24 Jan 2018 01:27:17 +0000 (01:27 +0000)]
[WebAssembly] Add minor helper functions to WasmObjectFile
Also, fix crash when exporting an imported function.
Differential Revision: https://reviews.llvm.org/D42454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323290
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Matthias Braun [Wed, 24 Jan 2018 00:39:53 +0000 (00:39 +0000)]
AArch64: Cyclone: Remove SlowMisaligned128Store tuning flag
Remove FeatureSlowMisaligned128Store from cyclone flags.
This flag causes splitting of 16 byte wide stores into 2 stored of 8
bytes. This was useful on older apple CPUs which were slow for 16byte
stores that were not aligned on 16byte. As the compiler often cannot
predict the actual alignment, the splitting was choosen.
This has been a topic for a lot of debate as the splitting also
decreases performance for some benchmarks. Measuring the effects on
newer apple chips (rdar://
35525421) shows that it harms more cases than
it helps. So it is time to retire this workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323289
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Reid Kleckner [Tue, 23 Jan 2018 23:17:06 +0000 (23:17 +0000)]
[llvm-readobj] Fix double 0x prefix in RVA table printing after r321527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323280
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Benjamin Kramer [Tue, 23 Jan 2018 23:05:04 +0000 (23:05 +0000)]
[TableGen] Optimize the regex search.
llvm::Regex is still the slowest regex engine on earth, running it over
all instructions on X86 takes a while. Extract a prefix and use a binary
search to reduce the search space before we resort to regex matching.
There are a couple of caveats here:
- The generic opcodes are outside of the sorted enum. They're handled in an extra loop.
- If there's a top-level bar we can't use the prefix trick.
- We bail on top-level ?. This could be handled, but it's rare.
This brings the time to generate X86GenInstrInfo.inc from 21s to 4.7s on
my machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323277
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Benjamin Kramer [Tue, 23 Jan 2018 23:03:50 +0000 (23:03 +0000)]
[TblGen] Inline an (almost) trivial accessor. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323276
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Sam Clegg [Tue, 23 Jan 2018 23:03:47 +0000 (23:03 +0000)]
[WebAssembly] MC: Use inline triple in test bitcode files
This matches the CodeGen tests and makes it a little easy
to run these from the command line manually.
Differential Revision: https://reviews.llvm.org/D42440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323275
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Volkan Keles [Tue, 23 Jan 2018 22:55:28 +0000 (22:55 +0000)]
Add missing include to fix the failure caused by r323266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323274
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Sam Clegg [Tue, 23 Jan 2018 22:32:34 +0000 (22:32 +0000)]
[WebAssembly] Add to test expectations for test/MC/WebAssembly/weak-alias.ll. NFC.
Split out from D42095
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323272
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Volkan Keles [Tue, 23 Jan 2018 22:24:34 +0000 (22:24 +0000)]
BlockExtractor: Remove unused variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323271
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Tim Shen [Tue, 23 Jan 2018 22:06:57 +0000 (22:06 +0000)]
[PPC] Avoid incorrect fp-i128-fp lowering.
Summary:
Fix an issue that's similar to what D41411 fixed:
float(__int128(float_var)) shouldn't be optimized to xscvdpsxds +
xscvsxdsp, as they mean (float)(int64_t)float_var.
Reviewers: jtony, hfinkel, echristo
Subscribers: sanjoy, nemanjai, hiraditya, llvm-commits, kbarton
Differential Revision: https://reviews.llvm.org/D42400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323270
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Sanjay Patel [Tue, 23 Jan 2018 22:04:17 +0000 (22:04 +0000)]
[SLPVectorizer] add test for PR13837; NFC
This was probably fixed long ago, but I don't see a test
that lines up with the example and target in the bug report:
https://bugs.llvm.org/show_bug.cgi?id=13837
...so adding it here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323269
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Simon Pilgrim [Tue, 23 Jan 2018 22:03:57 +0000 (22:03 +0000)]
Add bdver shuffle sink tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323268
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Volkan Keles [Tue, 23 Jan 2018 21:51:34 +0000 (21:51 +0000)]
[llvm-extract] Support extracting basic blocks
Summary:
Currently, there is no way to extract a basic block from a function easily. This patch
extends llvm-extract to extract the specified basic block(s).
Reviewers: loladiro, rafael, bogner
Reviewed By: bogner
Subscribers: hintonda, mgorny, qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D41638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323266
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Simon Pilgrim [Tue, 23 Jan 2018 21:50:46 +0000 (21:50 +0000)]
Regenerate select test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323265
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Simon Pilgrim [Tue, 23 Jan 2018 21:50:11 +0000 (21:50 +0000)]
Regenerate shuffle sink test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323264
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Craig Topper [Tue, 23 Jan 2018 21:37:56 +0000 (21:37 +0000)]
[X86] Merge some regular expressions in Zen scheduler model and remove 2 unused classes.
I don't know if the unused classes were intended to be used and that the VEX version is really different than the legacy SSE version. Agner's tables don't show any differences. I'm just cleaning up assuming the current behavior is correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323263
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Craig Topper [Tue, 23 Jan 2018 21:37:54 +0000 (21:37 +0000)]
[X86] Remove 'Int_' from instregexs in Zen scheduler model.
No instructions have Int_ at the beginning. It's always at the end now. So it should be picked up as a prefix match
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323262
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Craig Topper [Tue, 23 Jan 2018 21:37:51 +0000 (21:37 +0000)]
[X86] Move 'Int_' to the end of the name of the VCOMISS/VUCOMISS and instructions to get them picked up by the scheduler model regexs.
All other intrinsic instructions put the _Int on the end. This make these instructions consistent and gets the prefix instregexs in the scheduler models to pick them up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323261
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Simon Pilgrim [Tue, 23 Jan 2018 21:33:24 +0000 (21:33 +0000)]
[X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to v2i64/v2f64
Minor refactor to make it possible for LowerBUILD_VECTORAsVariablePermute to be used with a wider variety of shuffles op and types.
I'd have liked to add v4i32/v4f32 support as well but we don't see v4i32 index extractions at the moment (which is why I created D42308)
After this I intend to begin adding scaling support for PSHUFB (v8i16, v4i32, v2i64)) and VPERMPS (v4f64, v4i64).
Differential Revision: https://reviews.llvm.org/D42431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323260
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Evgeniy Stepanov [Tue, 23 Jan 2018 21:27:07 +0000 (21:27 +0000)]
[safestack] Inline safestack pointer access when possible.
Summary:
This adds an -mllvm flag that forces the use of a runtime function call to
get the unsafe stack pointer, the same that is currently used on non-x86, non-aarch64 android.
The call may be inlined.
Reviewers: pcc
Subscribers: aemerson, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D37405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323259
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Simon Pilgrim [Tue, 23 Jan 2018 21:22:16 +0000 (21:22 +0000)]
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323258
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Vedant Kumar [Tue, 23 Jan 2018 20:43:50 +0000 (20:43 +0000)]
[Debugify] Add a mode to opt to enable faster testing
Opt's "-enable-debugify" mode adds an instance of Debugify at the
beginning of the pass pipeline, and an instance of CheckDebugify at the
end.
You can enable this mode with lit using: -Dopt="opt -enable-debugify".
Note that running test suites in this mode will result in many failures
due to strict FileCheck commands, etc.
It can be more useful to look for assertion failures which arise only
when Debugify is enabled, e.g to prove that we have (or do not have)
test coverage for some code path with debug info present.
Differential Revision: https://reviews.llvm.org/D41793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323256
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Vedant Kumar [Tue, 23 Jan 2018 20:22:37 +0000 (20:22 +0000)]
docs: Remove reference to a deprecated flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323254
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Alexey Bataev [Tue, 23 Jan 2018 20:11:27 +0000 (20:11 +0000)]
Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle."
This reverts commit r323246 because of the broken buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323252
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Krzysztof Parzyszek [Tue, 23 Jan 2018 19:56:16 +0000 (19:56 +0000)]
[Hexagon] Add patterns for sext_inreg of HVX vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323250
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Volkan Keles [Tue, 23 Jan 2018 19:47:10 +0000 (19:47 +0000)]
Add a utility to reduce GlobalISel tests
Summary: This patch adds a script to reduce GlobalISel failures using bugpoint.
Reviewers: bogner
Reviewed By: bogner
Subscribers: MatzeB, qcolombet, rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323248
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Alexey Bataev [Tue, 23 Jan 2018 19:30:26 +0000 (19:30 +0000)]
[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.
Reviewers: spatel, RKSimon, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323246
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Zvi Rackover [Tue, 23 Jan 2018 19:20:39 +0000 (19:20 +0000)]
X86 Tests: Add AVX512BW config to CodeGenPrepare test. NFC
Case points out that we don't consider shifts supported by AVX512BW
in isVectorShiftByScalarCheap()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323242
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Krzysztof Parzyszek [Tue, 23 Jan 2018 19:08:40 +0000 (19:08 +0000)]
[Hexagon] Implement hasLoadFromStackSlot and hasStoreToStackSlot
If the instruction is a bundle, check the instructions inside of it.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323240
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Nico Weber [Tue, 23 Jan 2018 19:03:13 +0000 (19:03 +0000)]
Introduce errorToBool() helper and use it.
errorToBool() converts an Error to a bool and puts the Error in a checked
state. No behavior change.
https://reviews.llvm.org/D42422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323238
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Sam Clegg [Tue, 23 Jan 2018 18:30:04 +0000 (18:30 +0000)]
[WebAssembly] Remove "name" section of object wasm object files
LLD is unaffected, no changes needed there. LLD continues to
write out a name section, using the symbol names.
Fixes: https://github.com/WebAssembly/tool-conventions/issues/37
Patch by Nicholas Wilson!
Differential Revision: https://reviews.llvm.org/D42425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323234
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Krzysztof Parzyszek [Tue, 23 Jan 2018 18:16:52 +0000 (18:16 +0000)]
[Hexagon] Fix unused variable warning in release build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323233
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Krzysztof Parzyszek [Tue, 23 Jan 2018 17:53:59 +0000 (17:53 +0000)]
[Hexagon] Implement basic vector operations on vectors vNi1
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323229
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Simon Pilgrim [Tue, 23 Jan 2018 17:02:15 +0000 (17:02 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - extract subvector from oversized index vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323223
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Dan Gohman [Tue, 23 Jan 2018 17:02:02 +0000 (17:02 +0000)]
[WebAssembly] Add mem.* intrinsics.
The grow_memory and current_memory instructions are expected to be
officially renamed to mem.grow and mem.size. Introduce new intrinsics
with the new names. These new names aren't yet official, so for now,
use them at your own risk.
Also, take this opportunity to add arguments for the currently unused
immediate field in those instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323222
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Dan Gohman [Tue, 23 Jan 2018 16:55:44 +0000 (16:55 +0000)]
[WebAssembly] Switch to *-wasm as the default target triple.
This makes wasm32-unknown-unknown-wasm the default, which supports
the .o file writer and the new linking ABI. To enable s2wasm-compatible
output, use the wasm32-unknown-unknown-elf triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323220
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Yaxun Liu [Tue, 23 Jan 2018 16:11:15 +0000 (16:11 +0000)]
Verifier: fix bug treating debug info issue as non-debug info issue
Normally when llvm-as sees only debug info errors in LLVM assembly, it simply
drops the debug info and outputs a valid LLVM bitcode and returns 0.
There is a bug in LLVM verifier which incorrectly treats a debug info error
as non-debug info error, which causes llvm-as returns 1 even though llvm-as
can drop the invalid debug info and outputs a valid LLVM bitcode.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D42391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323216
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Alexander Ivchenko [Tue, 23 Jan 2018 16:08:15 +0000 (16:08 +0000)]
[x86] Reautogenerate a bunch of tests for D42287. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323215
91177308-0d34-0410-b5e6-
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Yaxun Liu [Tue, 23 Jan 2018 16:04:53 +0000 (16:04 +0000)]
CodeGen: Fix assertion in ScheduleDAGMILive::scheduleMI due to llvm.dbg.value
Fix a bug in ScheduleDAGMILive::scheduleMI which causes BotRPTracker not tracking CurrentBottom in some rare cases involving llvm.dbg.value.
This issues causes amdgcn target to assert when compiling some user codes with -g.
Differential Revision: https://reviews.llvm.org/D42394
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323214
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Craig Topper [Tue, 23 Jan 2018 15:56:36 +0000 (15:56 +0000)]
[X86] Rewrite vXi1 element insertion by using a vXi1 scalar_to_vector and inserting into a vXi1 vector.
The existing code was already doing something very similar to subvector insertion so this allows us to remove the nearly duplicate code.
This patch is a little larger than it should be due to differences between the DQI handling between the two today.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323212
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Simon Pilgrim [Tue, 23 Jan 2018 15:51:03 +0000 (15:51 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - ensure that the source vector is not larger than the destination
We might be able to support this in the future with VPERMV3, OR(PSHUFB, PSHUFB) etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323210
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Alexander Ivchenko [Tue, 23 Jan 2018 15:48:50 +0000 (15:48 +0000)]
[x86] Mostly reautogenerate a bunch of tests that affect D37775. NFC
Tests required minor manual tweaks:
CodeGen/MIR/X86/generic-instr-type.mir
CodeGen/X86/GlobalISel/select-copy.mir
CodeGen/X86/GlobalISel/select-ext.mir
CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
CodeGen/X86/GlobalISel/select-phi.mir
CodeGen/X86/GlobalISel/select-trunc.mir
CodeGen/X86/GlobalISel/select-frameIndex.mir
And following tests are split into 32/64 versions:
CodeGen/X86/GlobalISel/legalize-GV.mir
CodeGen/X86/GlobalISel/select-frameIndex.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323209
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Simon Pilgrim [Tue, 23 Jan 2018 15:30:07 +0000 (15:30 +0000)]
Use EVT::changeVectorElementTypeToInteger() to convert index type to integer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323207
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Simon Pilgrim [Tue, 23 Jan 2018 15:13:37 +0000 (15:13 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - ensure that the index vector has the correct number of elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323206
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Tim Northover [Tue, 23 Jan 2018 15:11:27 +0000 (15:11 +0000)]
AArch64: get type from correct result when forming BFX
Some nodes produce multiple values so when obtaining the type of an ISD::OR we
need to make sure we ask for the correct one. Hopefully that's all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323205
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Tim Northover [Tue, 23 Jan 2018 14:37:03 +0000 (14:37 +0000)]
AArch64: get type from correct result when forming BFI/BFM
Some nodes produce multiple values so when obtaining the type of an ISD::OR we
need to make sure we ask for the correct one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323202
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Craig Topper [Tue, 23 Jan 2018 14:25:39 +0000 (14:25 +0000)]
[X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the default of promoting to v32i8.
Summary:
For the most part its better to keep v32i1 as a mask type of a narrower width than trying to promote it to a ymm register.
I had to add some overrides to the methods that get the types for the calling convention so that we still use v32i8 for argument/return purposes.
There are still some regressions in here. I definitely saw some around shuffles. I think we probably should move vXi1 shuffle from lowering to a DAG combine where I think the extend and truncate we have to emit would be better combined.
I think we also need a DAG combine to remove trunc from (extract_vector_elt (trunc))
Overall this removes something like 13000 CHECK lines from lit tests.
Reviewers: zvi, RKSimon, delena, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323201
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Craig Topper [Tue, 23 Jan 2018 14:09:22 +0000 (14:09 +0000)]
[X86] Add missing MOVSX/MOVZX instructions to load folding tables.
I'm not sure there's any way to generate these folding cases especially the movzx ones since even the register form is never emitted by codegen.
I'm just adding them to remove the difference with the autogenerated version of the folding table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323200
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Tim Northover [Tue, 23 Jan 2018 13:51:57 +0000 (13:51 +0000)]
llvm-objdump: prevent out of bounds accesses during unwind dumping.
We were a bit too trusting about the offsets encoded in MachO compact unwind
sections, so this passes every access through a bounds check just in case. It
prevents a few segfaults on malformed object files, if one should ever come
along.
Mostly to silence fuzzers in the vague hope they might be able to produce
something useful without the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323198
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Serguei Katkov [Tue, 23 Jan 2018 12:07:49 +0000 (12:07 +0000)]
[CGP] Fix the GV handling in complex addressing mode
If in complex addressing mode the difference is in GV then
base reg should not be installed because we plan to use
base reg as a merge point of different GVs.
This is a fix for PR35980.
Reviewers: reames, john.brawn, santosh
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323192
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Simon Pilgrim [Tue, 23 Jan 2018 11:39:06 +0000 (11:39 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - fix PSHUFB source/index operand ordering
As detailed in rL317463, PSHUFB (like most variable shuffle instructions) uses Op[0] for the source vector and Op[1] for the shuffle index vector, VPERMV works in reverse which is probably where the confusion comes from.
Differential Revision: https://reviews.llvm.org/D42380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323190
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MinSeong Kim [Tue, 23 Jan 2018 11:11:36 +0000 (11:11 +0000)]
[Analysis] Disable exp/exp2/pow finite lib calls on Android with -ffast-math.
Summary:
Since r322087, glibc's finite lib calls are generated when possible.
However, glibc is not supported on Android. Therefore this change
enables llvm to finely distinguish between linux and Android for
unsupported library calls. The change also include some regression
tests.
Reviewers: srhines, pirama
Reviewed By: srhines
Subscribers: kongyi, chh, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D42288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323187
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Stefan Maksimovic [Tue, 23 Jan 2018 10:09:39 +0000 (10:09 +0000)]
[mips] Properly select abs and sqrt instructions
- Alter abs for micromips to have both AFGR64 and FGR64
variants, same as sqrt
- Remove sqrt and abs from MicroMips32r6InstrInfo.td,
use micromips FGR64 variants
- Restrict non-micromips abs/sqrt with NotInMicroMips
predicate
Differential revision: https://reviews.llvm.org/D41439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323184
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Ashutosh Nema [Tue, 23 Jan 2018 09:47:28 +0000 (09:47 +0000)]
This change add's optimization remark in LoopVersioning LICM pass.
Summary:
This patch is adding remark messages to the LoopVersioning LICM pass,
which will be useful for optimization remark emitter (ORE) infrastructure.
Patch by: Deepak Porwal
Reviewers: anemet, ashutosh.nema, eastig
Subscribers: eastig, vivekvpandya, fhahn, llvm-commits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323183
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Anton Bikineev [Tue, 23 Jan 2018 09:27:47 +0000 (09:27 +0000)]
[InstSimplify] (X << Y) % X -> 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323182
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Justin Bogner [Tue, 23 Jan 2018 06:39:04 +0000 (06:39 +0000)]
update_mir_test_checks: Improve the check for LLVM IR in MIR files
The LLVM IR section of a MIR document can start with "--- |" rather
than just "---", because "|" is a sigil for a freeform document in
YAML. We need to handle this so that we don't try to add check lines
to the LLVM IR functions in a MIR file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323178
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Hiroshi Inoue [Tue, 23 Jan 2018 05:49:30 +0000 (05:49 +0000)]
[NFC] fix trivial typos in comments
"the the" -> "the"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323176
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Craig Topper [Tue, 23 Jan 2018 05:45:52 +0000 (05:45 +0000)]
[X86] Don't reorder (srl (and X, C1), C2) if (and X, C1) can be matched as a movzx
Summary:
If we can match as a zero extend there's no need to flip the order to get an encoding benefit. As movzx is 3 bytes with independent source/dest registers. The shortest 'and' we could make is also 3 bytes unless we get lucky in the register allocator and its on AL/AX/EAX which have a 2 byte encoding.
This patch was more impressive before r322957 went in. It removed some of the same Ands that got deleted by that patch.
Reviewers: spatel, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323175
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Craig Topper [Tue, 23 Jan 2018 05:37:00 +0000 (05:37 +0000)]
[X86] Remove 'NOREX' comment from the printing of _NOREX instructions.
Some of the NOREX instructions are used in 32-bit mode making this printing confusing. It also doesn't provide a lot of value since you can see the h-register being used by the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323174
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Craig Topper [Tue, 23 Jan 2018 05:36:53 +0000 (05:36 +0000)]
[X86] Various vXi1 insertion improvements.
Add missing patterns for inserting v1i1 into a zero vector. Use insert_subvector to zero upper bits before inserting an element into a vXi1 vector. Replace kshift based isel pattern with insert_subvector based pattern now that code that caused the pattern has been fixed to emit insert_subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323173
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David Blaikie [Tue, 23 Jan 2018 01:25:20 +0000 (01:25 +0000)]
NewPM: Add an extension point for the start of the pipeline.
This applies to most pipelines except the LTO and ThinLTO backend
actions - it is for use at the beginning of the overall pipeline.
This extension point will be used to add the GCOV pass when enabled in
Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323166
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Sam Clegg [Tue, 23 Jan 2018 01:23:17 +0000 (01:23 +0000)]
[WebAssembly] Store function index rather than table index in TABLE_INDEX relocations
Relocations of type R_WEBASSEMBLY_TABLE_INDEX represent places
where the table index for a given function is needed. While the
value stored in this location is a table index, the index in
the relocation entry itself is a function index (the index of
the function which is to be called indirectly).
This is how is was spec'd originally but the LLVM implementation
didn't do this. This makes things a little simpler in the linker
since the table in the input file can essentially be ignored that
the output table can be created purely based on these relocations.
Patch by Nicholas Wilson!
Differential Revision: https://reviews.llvm.org/D42080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323165
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Rui Ueyama [Mon, 22 Jan 2018 23:27:50 +0000 (23:27 +0000)]
Revert r322595: Specify inline for isWhitespace in CommandLine.cpp
The original change was made based on a misunderstanding that
-DCMAKE_BUILD_TYPE=RelWithDebugInfo would produce the same executable
as -DCMAKE_BUILD_TYPE=Release modulo debug info. Turned out that's not
true -- it at least disables some optimizations such as function inlining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323161
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Chandler Carruth [Mon, 22 Jan 2018 22:05:25 +0000 (22:05 +0000)]
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/
7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323155
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Mark Searles [Mon, 22 Jan 2018 21:46:43 +0000 (21:46 +0000)]
[AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64
- Change inserted add ( V_ADD_{I|U}32_e32 ) to _e64 version ( V_ADD_{I|U}32_e64 ) so that the add uses a vreg for the carry; this prevents inserted v_add from killing VCC; the _e64 version doesn't accept a literal in its encoding, so we need to introduce a mov instr as well to get the imm into a register.
- Change pass name to "SI Load Store Optimizer"; this removes the '/', which complicates scripts.
Differential Revision: https://reviews.llvm.org/D42124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323153
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Jake Ehrlich [Mon, 22 Jan 2018 19:27:30 +0000 (19:27 +0000)]
[llvm-objcopy] Use physical instead of virtual address when aligning and placing sections in binary
For sections with different virtual and physical addresses, alignment and
placement in the output binary should be based on the physical address.
Ran into this problem with a bare metal ARM project where llvm-objcopy added a
lot of zero-padding before the .data section that had differing addresses. GNU
objcopy did not add the padding, and after this fix, neither does llvm-objcopy.
Update a test case so a section has different physical and virtual addresses.
Fixes B35708
Authored By: Owen Shaw (owenpshaw)
Differential Revision: https://reviews.llvm.org/D41619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323144
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Dmitry Vyukov [Mon, 22 Jan 2018 19:07:11 +0000 (19:07 +0000)]
asan: allow inline instrumentation for the kernel
Currently ASan instrumentation pass forces callback
instrumentation when applied to the kernel.
This patch changes the current behavior to allow
using inline instrumentation in this case.
Authored by andreyknvl. Reviewed in:
https://reviews.llvm.org/D42384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323140
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Evandro Menezes [Mon, 22 Jan 2018 19:03:26 +0000 (19:03 +0000)]
[AArch64] Create a separate feature set for Exynos M3
Distinguish the features from Exynos M2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323139
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Joel Galenson [Mon, 22 Jan 2018 17:53:47 +0000 (17:53 +0000)]
[ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInstr (NFCI).
As noted in another review, this loop is confusing. This commit cleans it up
somewhat.
Differential Revision: https://reviews.llvm.org/D42312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323136
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Reid Kleckner [Mon, 22 Jan 2018 17:50:20 +0000 (17:50 +0000)]
[CodeGen] Shrink MachineOperand by 8 bytes on Windows
Use 'unsigned' for these bitfields so they actually pack together.
Previously it used three words for these bits instead of one.
Add some static_asserts to prevent this from being undone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323135
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Ilya Biryukov [Mon, 22 Jan 2018 17:19:41 +0000 (17:19 +0000)]
[Dockerfiles] Use a newer version of ninja when building inside debian8.
Summary:
The debian8 repos have an old version of ninja that seems to sometimes crash
when building llvm.
Reviewers: ioeric, mehdi_amini
Reviewed By: ioeric
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323134
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Petar Jovanovic [Mon, 22 Jan 2018 16:43:30 +0000 (16:43 +0000)]
[mips] add warnings for using dsp and msa flags with inappropriate revisions
Dsp and dspr2 require MIPS revision 2, while msa requires revision 5. Adding
warnings for cases when these flags are used with earlier revision.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D40490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323131
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Ulrich Weigand [Mon, 22 Jan 2018 15:41:49 +0000 (15:41 +0000)]
[SystemZ] Fix bootstrap failure due to invalid DAG loop
The change in r322988 caused a failure in the bootstrap build bot.
The problem was that directly gluing a BR_CCMASK node to a
compare-and-swap could lead to issues if other nodes were
chained in between. There is then no way to create a topological
sort that respects both the chain sequence and the glue property.
Fixed for now by rejecting the optimization in this case. As a
future enhancement, we may be able to handle additional cases
by swapping chain links around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323129
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Marina Yatsina [Mon, 22 Jan 2018 15:31:05 +0000 (15:31 +0000)]
Fix bug in commit 323096 exposed by test in test-suite-verify-machineinstrs-x86_64h-O3
Change-Id: I0a4b10d0d6c8de606d989c567ec07944ae283a87
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323126
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Sander de Smalen [Mon, 22 Jan 2018 15:29:19 +0000 (15:29 +0000)]
[AArch64][SVE] Asm: PTRUE and PTRUES instructions
Summary: These instructions initialize a predicate vector from a pattern/immediate.
Reviewers: fhahn, rengolin, evandro, mcrosier, t.p.northover, samparker, olista01
Reviewed By: samparker
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323124
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Carey Williams [Mon, 22 Jan 2018 14:16:11 +0000 (14:16 +0000)]
[AArch64] optimise v4f16 fcmps to utilise vector instructions
Improves the code generation for v4f16 FCMP instructions when FullFP16 is not supported.
Generating FCTVL(s) rather than a longer series of FCVTs.
Differential Revision: https://reviews.llvm.org/D41772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323118
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Eugene Leviant [Mon, 22 Jan 2018 13:35:40 +0000 (13:35 +0000)]
[ThinLTO] Re-commit of dot dumper after test fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323116
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Marina Yatsina [Mon, 22 Jan 2018 13:24:10 +0000 (13:24 +0000)]
Fixing warnings caused by commit 323095
Change-Id: I4e1f81db2f5382a820f4016c23b243e4d5aebf51
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323114
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Pavel Labath [Mon, 22 Jan 2018 13:17:23 +0000 (13:17 +0000)]
Rename DwarfAcceleratorTable to AppleAcceleratorTable. NFC
This frees up the first name to be used as an base class for the
apple table and the dwarf5 .debug_names accel table. The rename was
split off from D42297 (adding of debug_names support), which is still
under review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323113
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Simon Pilgrim [Mon, 22 Jan 2018 12:27:22 +0000 (12:27 +0000)]
[X86][AVX] Add test case for PR34370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323106
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Simon Pilgrim [Mon, 22 Jan 2018 12:05:17 +0000 (12:05 +0000)]
[X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied)
Primarily, this allows us to use the aggressive extraction mechanisms in combineExtractWithShuffle earlier and make use of UNDEF elements that may be lost during lowering.
Reapplied after rL322279 was reverted at rL322335 due to PR35918, underlying issue was fixed at rL322644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323104
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Sander de Smalen [Mon, 22 Jan 2018 10:46:00 +0000 (10:46 +0000)]
[AArch64][SVE] Asm: Predicate patterns
Summary:
This patch adds support for parsing/printing of named or unnamed
patterns that are used in SVE's PTRUE instruction, amongst others.
The pattern can be specified as a named pattern to initialize the predicate
vector or it can be specified as an immediate in the range 0-31.
Reviewers: fhahn, rengolin, evandro, mcrosier, t.p.northover
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323098
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