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Rafael Espindola [Mon, 29 Jun 2015 14:12:14 +0000 (14:12 +0000)]
Add a testcase for an invalid file.
We were already checking this, but had no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240945
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Rafael Espindola [Mon, 29 Jun 2015 14:02:24 +0000 (14:02 +0000)]
Convert an assert that can fail into error checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240944
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Rafael Espindola [Mon, 29 Jun 2015 12:38:31 +0000 (12:38 +0000)]
Remove Elf_Sym_Iter.
It was a fairly broken concept for an ELF only class.
An ELF file can have two symbol tables, but they have exactly the same
format. There is no concept of a dynamic or a static symbol. Storing this
on the iterator also makes us do more work per symbol than necessary. To fetch
a name we would:
* Find if we had a static or a dynamic symbol.
* Look at the corresponding symbol table and find the string table section.
* Look at the string table section to fetch its contents.
* Compute the name as a substring of the string table.
All but the last step can be done per symbol table instead of per symbol. This
is a step in that direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240939
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Elena Demikhovsky [Mon, 29 Jun 2015 12:14:24 +0000 (12:14 +0000)]
AVX-512: all forms of SCATTER instruction on SKX,
encoding, intrinsics and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240936
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Javed Absar [Mon, 29 Jun 2015 09:53:33 +0000 (09:53 +0000)]
[ARM]: Extend -mfpu options for half-precision and vfpv3xd
removing default label in switch as it results.
This is part of earlier commit http://reviews.llvm.org/D1064
Subscribers: llvm-commits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240932
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Javed Absar [Mon, 29 Jun 2015 09:32:29 +0000 (09:32 +0000)]
[ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.
Reviewers: rengolin, ranjeet.singh
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930
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Igor Breger [Mon, 29 Jun 2015 09:10:00 +0000 (09:10 +0000)]
AVX-512: Implemented missing encoding and intrinsics for FMA instructions
Added tests for DAG lowering ,encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D10796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240926
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NAKAMURA Takumi [Mon, 29 Jun 2015 04:50:09 +0000 (04:50 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240924
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Matt Arsenault [Sun, 28 Jun 2015 18:16:14 +0000 (18:16 +0000)]
AMDGPU/SI: Fix extra space when printing v_div_fmas_*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240911
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Jingyue Wu [Sun, 28 Jun 2015 17:45:05 +0000 (17:45 +0000)]
[SLSR] S's basis must have the same type as S
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240910
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Asaf Badouh [Sun, 28 Jun 2015 14:30:39 +0000 (14:30 +0000)]
[x86][AVX512]
Add vscalef support
include encoding and intrinsics
review:
http://reviews.llvm.org/D10730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240906
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Elena Demikhovsky [Sun, 28 Jun 2015 10:53:29 +0000 (10:53 +0000)]
AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240905
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Adrian Prantl [Sat, 27 Jun 2015 21:55:00 +0000 (21:55 +0000)]
Revert "Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed"
This reverts commit 240890. Breaking the gdb buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240893
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Benjamin Kramer [Sat, 27 Jun 2015 21:11:43 +0000 (21:11 +0000)]
Don't use %llc_dwarf for target-specific tests.
Should fix running them on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240892
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Benjamin Kramer [Sat, 27 Jun 2015 20:33:26 +0000 (20:33 +0000)]
[SDAG] Now that we have a way to communicate the exact bit on sdiv use it to simplify sdiv by a constant.
We had a hack in SDAGBuilder in place to work around this but now we
can avoid that. Call BuildExactSDIV from BuildSDIV so DAGCombiner can
perform this trick automatically.
The added check in DAGCombiner is necessary to prevent exact sdiv by pow2
from regressing as the target-specific pow2 lowering is not aware of
exact bits yet.
This is mostly covered by existing tests. One side effect is that we
get the better lowering for exact vector sdivs now too :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240891
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Adrian Prantl [Sat, 27 Jun 2015 20:12:43 +0000 (20:12 +0000)]
Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed
the DW_AT_bit_offset computation, the byte offset is in fact also
endian-dependent as it needs to point to the storage unit containing the
most-significant bit of the the bitfield.
I'm so looking forward to emitting the endian-agnostic DWARF 3 version
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240890
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Daniel Sanders [Sat, 27 Jun 2015 17:56:44 +0000 (17:56 +0000)]
[mips] Fold duplicate big-endian disassembler tests together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240887
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Daniel Sanders [Sat, 27 Jun 2015 16:13:59 +0000 (16:13 +0000)]
[mips] Sort big-endian disassembler tests by opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240885
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Daniel Sanders [Sat, 27 Jun 2015 15:42:25 +0000 (15:42 +0000)]
[mips] Make little-endian disassembler test filenames consistent.
Most are named *-el.txt. Renamed the three that were *-le.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240884
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Daniel Sanders [Sat, 27 Jun 2015 15:39:19 +0000 (15:39 +0000)]
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.
Patch by Simon Dardis. A couple small corrections by myself.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883
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Peter Zotov [Sat, 27 Jun 2015 14:32:30 +0000 (14:32 +0000)]
[OCaml] Bump ctypes dependency to 0.4.
ctypes 0.3 and earlier contains an interface-definig bug:
its ptr_of_raw_address accepts Int64 and not Nativeint. ctypes 0.4
was not released during the 3.6 cycle, and because of that, LLVM 3.6
was released with ctypes 0.3 as a dependency, which now breaks
the build on modern ctypes.
Unbreak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240882
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David Majnemer [Sat, 27 Jun 2015 08:38:17 +0000 (08:38 +0000)]
[LoopVectorize] Pointer indicies may be wider than the pointer
If we are dealing with a pointer induction variable, isInductionPHI
gives back a step value of Stride / size of pointer. However, we might
be indexing with a legal type wider than the pointer width.
Handle this by inserting casts where appropriate instead of crashing.
This fixes PR23954.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240877
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David Majnemer [Sat, 27 Jun 2015 07:52:53 +0000 (07:52 +0000)]
[PruneEH] A naked, noinline function can return via InlineAsm
The PruneEH pass tries to annotate functions as 'noreturn' if it doesn't
see a ReturnInst. However, a naked function containing inline assembly
can contain control flow leaving the function.
This fixes PR23971.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240876
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Lang Hames [Sat, 27 Jun 2015 03:49:25 +0000 (03:49 +0000)]
[Stackmap] Pre-assemble the stackmap parser test case. (Fix builders).
This case had been failing on testers that didn't have x86 support. Rather
than XFAIL it on testers without x86 support, I've just assembled it and used
the raw object as the test input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240875
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NAKAMURA Takumi [Sat, 27 Jun 2015 03:46:58 +0000 (03:46 +0000)]
llvm/test/CodeGen/X86/xor.ll: Appease Win32 targets since r240796.
%struct.ref_s = type { %union.v, i16, i16 }
%union.v = type { i64 }
It seems %struct.ref_s is incompatible in tail padding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240874
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Petr Hosek [Sat, 27 Jun 2015 01:54:17 +0000 (01:54 +0000)]
[MC] Ensure that pending labels are flushed when -mc-relax-all flag is used
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.
The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.
Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063
Test Plan: Regression test attached
Reviewers: mseaborn
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240870
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Petr Hosek [Sat, 27 Jun 2015 01:49:53 +0000 (01:49 +0000)]
[MC] Align fragments when -mc-relax-all flag is used
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.
The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.
Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063
Test Plan: Regression test attached
Reviewers: mseaborn
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240869
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Duncan P. N. Exon Smith [Sat, 27 Jun 2015 01:19:17 +0000 (01:19 +0000)]
AsmPrinter: Document why DIEValueList uses a linked-list, NFC
There are two main reasons why a linked-list makes sense for
`DIEValueList`.
1. We want `DIE` to be on a `BumpPtrAllocator` to improve teardown
efficiency. Making `DIEValueList` array-based would make that much
more complicated.
2. The singly-linked list is fairly memory efficient. The histogram
[1] shows that most DIEs have relatively few values, so we often pay
less than the 2/3-pointer static overhead of a vector. Furthermore,
we don't know ahead of time exactly how many values a `DIE` needs,
so a vector-like scheme will on average over-allocate by ~50%. As
it happens, that's the same memory overhead as the linked list node.
[1]: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-May/085910.html
The comment I added to the code is a little more succinct, but I think
it's enough to give the idea.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240868
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Duncan P. N. Exon Smith [Sat, 27 Jun 2015 00:38:26 +0000 (00:38 +0000)]
IR: Expose ModuleSlotTracker in Value::print()
Allow callers of `Value::print()` and `Metadata::print()` to pass in a
`ModuleSlotTracker`. This allows them to pay only once for calculating
module-level slots (such as Metadata).
This is related to PR23865, where there was a huge cost for
`MachineFunction::print()`. Although I don't have a *particular* user
in mind for this new code, I have hit big slowdowns before when running
`opt -debug`, and I think this will be useful. Going forward, if
someone hits a big slowdown with `print()` statements, they can create a
`ModuleSlotTracker` and send it through. Similarly, adding support to
`Value::dump()` and `Metadata::dump()` should be trivial.
I added unit tests to be sure the `print()` functions actually behave
the same way with and without the slot tracker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240867
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Peter Collingbourne [Sat, 27 Jun 2015 00:17:51 +0000 (00:17 +0000)]
LowerBitSets: Ignore bitset entries that do not directly refer to a global.
It is possible for a global to be substituted with another global of a
different type or a different kind (i.e. an alias) at IR link time. One
example of this scenario is when a Microsoft ABI vtable is substituted with
an alias referring to a larger vtable containing an RTTI reference.
This will cause the global to be RAUW'd with a possibly bitcasted reference
to the other global. This will of course also affect any references to the
global in bitset metadata.
The right way to handle such metadata is simply to ignore it. This is sound
because the linked module should contain another copy of the bitset entries as
applied to the new global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240866
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Duncan P. N. Exon Smith [Sat, 27 Jun 2015 00:15:32 +0000 (00:15 +0000)]
Plug a leak introduced by r240848
Apparently this obvious leak was never exercised before, but r240848
exposed it. Plug it.
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/5075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240865
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Adrian Prantl [Sat, 27 Jun 2015 00:01:33 +0000 (00:01 +0000)]
Add original source code to test case as suggested in review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240863
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Lang Hames [Fri, 26 Jun 2015 23:56:53 +0000 (23:56 +0000)]
[StackMaps] Add a lightweight parser for stackmap version 1 sections.
The parser provides a convenient interface for reading llvm stackmap v1 sections
in object files.
This patch also includes a new option for llvm-readobj, '-stackmap', which uses
the parser to pretty-print stackmap sections for debugging/testing purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240860
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Adrian Prantl [Fri, 26 Jun 2015 23:31:27 +0000 (23:31 +0000)]
Debug Info: Fix a bug in the DW_AT_bit_offset calculation that would
result in negative offsets and attempt a better job at documenting
the algorithm.
rdar://
21082998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240853
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Duncan P. N. Exon Smith [Fri, 26 Jun 2015 23:18:44 +0000 (23:18 +0000)]
CodeGen: Create a proper ModuleSlotTracker for MachineInstr
Another follow-up related to r240848: try a little harder to share slot
tracking calculations within a single `MachineInstr` dump. This is
unrelated to `MachineFunction::print()`, since that should be passing
through the function's `ModuleSlotTracker` by now, but could affect the
speed of dumping from a debugger if there is more than one IR-level
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240852
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Alex Lorenz [Fri, 26 Jun 2015 22:56:48 +0000 (22:56 +0000)]
MIR Serialization: Serialize global address machine operands.
This commit serializes the global address machine operands.
This commit doesn't serialize the operand's offset and target
flags, it serializes only the global value reference.
Reviewers: Duncan P. N. Exon Smith
Differential Revision: http://reviews.llvm.org/D10671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240851
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Philip Reames [Fri, 26 Jun 2015 22:47:37 +0000 (22:47 +0000)]
[RewriteStatepointsForGC] Generalized vector phi/select handling for base pointers
This change extends the detection of base pointers for vector constructs to handle arbitrary phi and select nodes. The existing non-vector code already handles those, so this is basically just extending the vector special case to be less special cased. It still isn't generalized vector handling since we can't handle arbitrary vector instructions (e.g. shufflevectors), but it's a lot closer.
The general structure of the change is as follows:
* Extend the base defining value relation over a subset of vector instructions and vector typed phi & select instructions.
* Move scalarization from before base pointer rewriting to after base pointer rewriting. The extension of the BDV relation is sufficient to find vector base phis for vector inputs.
* Preserve the existing special case logic for when the base of a vector element is locally obvious. This general idea could be extended to the scalar case as well.
Differential Revision: http://reviews.llvm.org/D10461#inline-84275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240850
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Jingyue Wu [Fri, 26 Jun 2015 22:35:43 +0000 (22:35 +0000)]
[NVPTX] noop when kernel pointers are already global
Summary:
Some front ends make kernel pointers global already. In that case,
handlePointerParams does nothing.
Test Plan: more tests in lower-kernel-ptr-arg.ll
Reviewers: grosser
Subscribers: jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D10779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240849
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Duncan P. N. Exon Smith [Fri, 26 Jun 2015 22:28:47 +0000 (22:28 +0000)]
CodeGen: Push the ModuleSlotTracker through Metadata
For another 1% speedup on the testcase in PR23865, push the
`ModuleSlotTracker` through to metadata-related printing in
`MachineBasicBlock::print()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240848
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Philip Reames [Fri, 26 Jun 2015 22:21:52 +0000 (22:21 +0000)]
Minor style cleanup after 240843 [NFC]
Use a for-each loop in one case and rename the function to reflect it's new usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240847
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Duncan P. N. Exon Smith [Fri, 26 Jun 2015 22:06:47 +0000 (22:06 +0000)]
CodeGen: Push the ModuleSlotTracker through MachineOperands
Push `ModuleSlotTracker` through `MachineOperand`s, dropping the time
for `llc -print-machineinstrs` on the testcase in PR23865 from ~13
seconds to ~9 seconds. Now `SlotTracker::processFunctionMetadata()`
accounts for only 8% of the runtime, which seems reasonable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240845
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Philip Reames [Fri, 26 Jun 2015 22:04:34 +0000 (22:04 +0000)]
[Verifier] Follow on to 240836
Address one missed review comment and do the rename I left out of that patch to make it reviewable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240843
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Duncan P. N. Exon Smith [Fri, 26 Jun 2015 22:04:20 +0000 (22:04 +0000)]
CodeGen: Use a single SlotTracker in MachineFunction::print()
Expose enough of the IR-level `SlotTracker` so that
`MachineFunction::print()` can use a single one for printing
`BasicBlock`s. Next step would be to lift this through a few more APIs
so that we can make other print methods faster.
Fixes PR23865, changing the runtime of `llc -print-machineinstrs` from
many minutes (killed after 3 minutes, but it wasn't very close) to
13 seconds for a 502185 line dump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240842
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Tom Stellard [Fri, 26 Jun 2015 21:58:42 +0000 (21:58 +0000)]
AMDPGU/SI: Use correct resource descriptors for VI on HSA
Summary: We need to set MTYPE = 2 for VI shaders when targeting the HSA runtime.
Reviewers: arsenm
Differential Revision: http://reviews.llvm.org/D10777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240841
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Tom Stellard [Fri, 26 Jun 2015 21:58:31 +0000 (21:58 +0000)]
AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839
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Tom Stellard [Fri, 26 Jun 2015 21:58:26 +0000 (21:58 +0000)]
AMDGPU/SI: Remove unused variable
This should fix some bots that were broken by r240831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240838
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Philip Reames [Fri, 26 Jun 2015 21:39:44 +0000 (21:39 +0000)]
[Verifier] Verify invokes of intrinsics
We support invoking a subset of llvm's intrinsics, but the verifier didn't account for this. We had previously added a special case to verify invokes of statepoints. By generalizing the code in terms of CallSite, we can verify invokes of other intrinsics as well. Interestingly, this found one test case which was invalid.
Note: I'm deliberately leaving the naming change from CI to CS to a follow up change. That will happen shortly, I just wanted to reduce the diff to make it clear what was happening with this one.
Differential Revision: http://reviews.llvm.org/D10118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240836
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Adrian Prantl [Fri, 26 Jun 2015 21:27:30 +0000 (21:27 +0000)]
Debug Info: Clarify the documentation for bitfields emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240835
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Adrian Prantl [Fri, 26 Jun 2015 21:27:16 +0000 (21:27 +0000)]
Debug info: Add more test coverage for bitfields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240834
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Tom Stellard [Fri, 26 Jun 2015 21:15:11 +0000 (21:15 +0000)]
AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
Reviewers: arsenm, rafael
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240832
91177308-0d34-0410-b5e6-
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Tom Stellard [Fri, 26 Jun 2015 21:15:07 +0000 (21:15 +0000)]
AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831
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Tom Stellard [Fri, 26 Jun 2015 21:15:03 +0000 (21:15 +0000)]
AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240830
91177308-0d34-0410-b5e6-
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Tom Stellard [Fri, 26 Jun 2015 21:14:58 +0000 (21:14 +0000)]
AMDGPU/SI: Emit amd_kernel_code_t in EmitFunctionBodyStart()
Summary:
This way the function symbol points to the start of amd_kernel_code_t
rather than the start of the function.
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240829
91177308-0d34-0410-b5e6-
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Philip Reames [Fri, 26 Jun 2015 20:51:17 +0000 (20:51 +0000)]
Teach InlineCost to account for a null check which can be folded away
If we have a caller that knows a particular argument can never be null, we can exploit this fact while simplifying values in the inline cost analysis. This has the effect of reducing the cost for inlining when a null check is present in the callee, but the value is known non null in the caller. In particular, any dependent control flow can be discounted from the cost estimate.
Note that we use the parameter attributes at the call site to memoize the analysis within the caller's code. The setting of this attribute is done in InstCombine, the inline cost analysis just consumes it. This is intentional and important because we want the inline cost analysis results to be easily cachable themselves. We're not currently doing so, but initial results on LTO indicate this will quickly become important.
Differential Revision: http://reviews.llvm.org/D9129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240828
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Mehdi Amini [Fri, 26 Jun 2015 20:44:16 +0000 (20:44 +0000)]
DataLayout now returns a const ref to its member string representation
There was no particular reason to return by value in the first place.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240826
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Marek Olsak [Fri, 26 Jun 2015 20:29:10 +0000 (20:29 +0000)]
AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
If pseudoToMCOpcode failed, we would return the original opcode, so operands
would be swapped, but the instruction would remain the same.
It resulted in LSHLREV a, b ---> LSHLREV b, a.
This fixes Glamor text rendering and
piglit/arb_sample_shading-builtin-gl-sample-mask on VI.
This is a candidate for stable branches.
v2: the test was simplified by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240824
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Benjamin Kramer [Fri, 26 Jun 2015 20:16:44 +0000 (20:16 +0000)]
Add Value.def to the list of textual includes, excluding it from the modules build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240823
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Pete Cooper [Fri, 26 Jun 2015 19:37:02 +0000 (19:37 +0000)]
Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240822
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Nemanja Ivanovic [Fri, 26 Jun 2015 19:26:53 +0000 (19:26 +0000)]
Add missing builtins to the PPC back end for ABI compliance (vol. 1)
This patch corresponds to review:
http://reviews.llvm.org/D10638
This is the back end portion of patch
http://reviews.llvm.org/D10637
It just adds the code gen and intrinsic functions necessary to support that patch to the back end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240820
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Pete Cooper [Fri, 26 Jun 2015 19:23:20 +0000 (19:23 +0000)]
Wrap assert loops in #ifndef NDEBUG
The body of the loops here only contained asserts. This triggered an unused variable
warning on release builds and -Werror on the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240819
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Pete Cooper [Fri, 26 Jun 2015 19:18:49 +0000 (19:18 +0000)]
Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240817
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Pete Cooper [Fri, 26 Jun 2015 19:08:33 +0000 (19:08 +0000)]
Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240815
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Fri, 26 Jun 2015 19:04:11 +0000 (19:04 +0000)]
Make header parse standalone. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240814
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Matt Arsenault [Fri, 26 Jun 2015 19:00:11 +0000 (19:00 +0000)]
Show invariant loads in MMO dumping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240813
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David Majnemer [Fri, 26 Jun 2015 18:55:48 +0000 (18:55 +0000)]
Revert "Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant""
This reverts commit r240793 while fixing how we handle array constant
pool entries.
This fixes PR23966.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240811
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Rafael Espindola [Fri, 26 Jun 2015 18:42:17 +0000 (18:42 +0000)]
Fix error handling in getString and simplify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240810
91177308-0d34-0410-b5e6-
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Pete Cooper [Fri, 26 Jun 2015 18:41:54 +0000 (18:41 +0000)]
Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240809
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Rafael Espindola [Fri, 26 Jun 2015 18:32:53 +0000 (18:32 +0000)]
Delete dead code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240807
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Pete Cooper [Fri, 26 Jun 2015 18:17:36 +0000 (18:17 +0000)]
Add op_values() to iterate over the SDValue operands of an SDNode.
SDNode already had ops() which would iterate over the operands and return
SDUse*. This version instead gets the SDValue's out of the SDUse's so that
we can use foreach in more places.
Reviewed by David Blaikie.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240805
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David Blaikie [Fri, 26 Jun 2015 18:02:52 +0000 (18:02 +0000)]
Move VectorUtils from Transforms to Analysis to correct layering violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240804
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Javed Absar [Fri, 26 Jun 2015 17:42:37 +0000 (17:42 +0000)]
[ARM] Cortex-R5 is not VFPOnlySP
This patch fixes the error in ARM.td which stated that Cortex-R5
floating point unit can do only single precision, when it can do double as well.
Reviewers: rengolin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240799
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Adam Nemet [Fri, 26 Jun 2015 17:25:43 +0000 (17:25 +0000)]
[LAA] Try to prove non-wrapping of pointers if SCEV cannot
Summary:
Scalar evolution does not propagate the non-wrapping flags to values
that are derived from a non-wrapping induction variable because
the non-wrapping property could be flow-sensitive.
This change is a first attempt to establish the non-wrapping property in
some simple cases. The main idea is to look through the operations
defining the pointer. As long as we arrive to a non-wrapping AddRec via
a small chain of non-wrapping instruction, the pointer should not wrap
either.
I believe that this essentially is what Andy described in
http://article.gmane.org/gmane.comp.compilers.llvm.cvs/220731 as the way
forward.
Reviewers: aschwaighofer, nadav, sanjoy, atrick
Reviewed By: atrick
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240798
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Alex Lorenz [Fri, 26 Jun 2015 17:07:27 +0000 (17:07 +0000)]
Fix unused variable from r240792.
The variable 'I' wasn't used when assertions were disabled.
This commit ensures that 'I' is used outside of an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240797
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Benjamin Kramer [Fri, 26 Jun 2015 16:59:31 +0000 (16:59 +0000)]
[DAGCombine] Fix demanded bits computation for exact shifts.
Fixes a miscompilation of MultiSource/Benchmarks/MallocBench/gs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240796
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Douglas Katzman [Fri, 26 Jun 2015 16:58:59 +0000 (16:58 +0000)]
[X86]: Correctly sign-extend 16-bit immediate in CALL instruction.
Patch by Matthew Barney. Thanks!
Differential Revision: http://reviews.llvm.org/D9514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240795
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David Blaikie [Fri, 26 Jun 2015 16:57:30 +0000 (16:57 +0000)]
Fix ODR violation waiting to happen by making static function definitions in VectorUtils.h non-static and defined out of line
Patch by Ashutosh Nema
Differential Revision: http://reviews.llvm.org/D10682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240794
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Hans Wennborg [Fri, 26 Jun 2015 16:48:02 +0000 (16:48 +0000)]
Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant"
It seems to have caused PR23966: "UNREACHABLE executed at ..\lib\Target\X86\X86TargetObjectFile.cpp:148"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240793
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Alex Lorenz [Fri, 26 Jun 2015 16:46:11 +0000 (16:46 +0000)]
MIR Serialization: Serialize machine basic block operands.
This commit serializes machine basic block operands. The
machine basic block operands use the following syntax:
%bb.<id>[.<name>]
This commit also modifies the YAML representation for the
machine basic blocks - a new, required field 'id' is added
to the MBB YAML mapping.
The id is used to resolve the MBB references to the
actual MBBs. And while the name of the MBB can be
included in a MBB reference, this name isn't used to
resolve MBB references - as it's possible that multiple
MBBs will reference the same BB and thus they will have the
same name. If the name is specified, the parser will verify
that it is equal to the name of the MBB with the specified id.
Reviewers: Duncan P. N. Exon Smith
Differential Revision: http://reviews.llvm.org/D10608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240792
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Rafael Espindola [Fri, 26 Jun 2015 15:27:04 +0000 (15:27 +0000)]
ELF: Simplify the rel/rela implementation.
Now the rela class inherits from rel and just adds the addend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240790
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Benjamin Kramer [Fri, 26 Jun 2015 14:51:49 +0000 (14:51 +0000)]
[DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.
Allows more aggressive folding of ashr/shl pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240788
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Benjamin Kramer [Fri, 26 Jun 2015 14:51:36 +0000 (14:51 +0000)]
[DAGCombine] fold (X >>?,exact C1) << C2 --> X << (C2-C1)
Instcombine also does this but many opportunities only become visible
after GEPs are lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240787
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Aaron Ballman [Fri, 26 Jun 2015 14:51:22 +0000 (14:51 +0000)]
Silencing spurious MSVC C4189 warnings regarding local variables that are initialized but not used; NFC. This bug has been reported to Microsoft (https://connect.microsoft.com/VisualStudio/feedback/details/
1475983).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240786
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Rafael Espindola [Fri, 26 Jun 2015 14:51:16 +0000 (14:51 +0000)]
Rename getObjectFile to getObject for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240785
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Rafael Espindola [Fri, 26 Jun 2015 14:11:54 +0000 (14:11 +0000)]
Simplify isSymbolList64Bit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240784
91177308-0d34-0410-b5e6-
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Rafael Espindola [Fri, 26 Jun 2015 13:24:23 +0000 (13:24 +0000)]
Simplify isObject. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240783
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Toma Tabacu [Fri, 26 Jun 2015 13:20:17 +0000 (13:20 +0000)]
[mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782
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Rafael Espindola [Fri, 26 Jun 2015 13:11:15 +0000 (13:11 +0000)]
Implement elf_section_iterator and getELFType().
And with those, simplify getSymbolNMTypeChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240780
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Rafael Espindola [Fri, 26 Jun 2015 12:44:10 +0000 (12:44 +0000)]
Expose getFlags via ELFSectionRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240779
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Rafael Espindola [Fri, 26 Jun 2015 12:33:37 +0000 (12:33 +0000)]
Add a ELFSectionRef class and use it to expose getSectionType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240778
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Rafael Espindola [Fri, 26 Jun 2015 12:18:49 +0000 (12:18 +0000)]
Simplify getSymbolType.
This is still a really odd function. Most calls are in object format specific
contexts and should probably be replaced with a more direct query, but at least
now this is not too obnoxious to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240777
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Javed Absar [Fri, 26 Jun 2015 12:14:56 +0000 (12:14 +0000)]
[ARM] Cortex-R4F is not VFPOnlySP
Cortex-R4F TRM states that fpu supports both single and double precision.
This patch corrects the information in ARM.td file and corresponding test.
Reviewers: rengolin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240776
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Rafael Espindola [Fri, 26 Jun 2015 11:39:57 +0000 (11:39 +0000)]
Make getOther ELF only.
No other format has this field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240774
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Rafael Espindola [Fri, 26 Jun 2015 11:31:13 +0000 (11:31 +0000)]
Optimize the creation of mapping symbols.
No need to create two symbols just to assign one to the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240773
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Sergey Dmitrouk [Fri, 26 Jun 2015 10:13:56 +0000 (10:13 +0000)]
Do not ignore projects/LLVMBuild.txt in git repo
Without explicit exception for the path, it matches projects/* rule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240771
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David Majnemer [Fri, 26 Jun 2015 07:03:12 +0000 (07:03 +0000)]
[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant
No functionality changed, just keeping things clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240762
91177308-0d34-0410-b5e6-
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Hao Liu [Fri, 26 Jun 2015 04:38:21 +0000 (04:38 +0000)]
[InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240760
91177308-0d34-0410-b5e6-
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Hao Liu [Fri, 26 Jun 2015 02:45:36 +0000 (02:45 +0000)]
[ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.
This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
Differential Revision: http://reviews.llvm.org/D10533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240755
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Hao Liu [Fri, 26 Jun 2015 02:32:07 +0000 (02:32 +0000)]
[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
Differential Revision: http://reviews.llvm.org/D10533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240754
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Hao Liu [Fri, 26 Jun 2015 02:10:27 +0000 (02:10 +0000)]
[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
%v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.
E.g. An interleaved store (Factor = 3):
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.
Differential Revision: http://reviews.llvm.org/D10533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240751
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Duncan P. N. Exon Smith [Fri, 26 Jun 2015 00:53:44 +0000 (00:53 +0000)]
AsmPrinter: More explicitly scope iterator for MSVC
r240748 seems to be on the right path. Be more explicit.
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/1961/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240750
91177308-0d34-0410-b5e6-
96231b3b80d8