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Sander de Smalen [Mon, 2 Jul 2018 07:34:52 +0000 (07:34 +0000)]
Reapply r334980 and r334983.
These patches were previously reverted as they led to
buildbot time-outs caused by large switch statement in
printAliasInstr when using UBSan and O3. The issue has
been addressed with a workaround (r335525).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336079
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Max Kazantsev [Mon, 2 Jul 2018 06:55:00 +0000 (06:55 +0000)]
[NFC] Test that shows unprofitability of instcombine with bit ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336078
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Craig Topper [Mon, 2 Jul 2018 06:42:42 +0000 (06:42 +0000)]
[X86] Put some cases in switch statements back on one line to be more compact and make it easier to see the similarities. NFC
It looks like someone ran clang-format over this entire file which reformatted these switches into a multiline form. But I think the single line form is more useful here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336077
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Clement Courbet [Mon, 2 Jul 2018 06:39:55 +0000 (06:39 +0000)]
[llvm-exegesis][NFC] Cleanup useless braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336076
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Craig Topper [Mon, 2 Jul 2018 06:23:39 +0000 (06:23 +0000)]
[X86] Remove FMA3Info DenseMap. Break into sorted tables that we can binary search.
I separated out the rounding and broadcast groups into their own tables because it made the ordering in the main table easier.
Further splitting of the tables might make it possible to directly index using bits from the TSFlags, but its probably not worth it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336075
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QingShan Zhang [Mon, 2 Jul 2018 05:46:09 +0000 (05:46 +0000)]
[PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's multiple for i64 pre-inc load/store
For the below case, pre-inc prep think it's a good candidate to use pre-inc for the bucket, but 64bit integer load/store update (pre-inc) instruction on Power requires the displacement field should be DS-form (4's multiple). Since it can't satisfy the constraint, we have to do some fix ups later. As below, the original load/stores could be well-form, it makes things worse.
unsigned long long result = 0;
unsigned long long foo(char *p, unsigned long long n) {
for (unsigned long long i = 0; i < n; i++) {
unsigned long long x1 = *(unsigned long long *)(p - 50000 + i);
unsigned long long x2 = *(unsigned long long *)(p - 61024 + i);
unsigned long long x3 = *(unsigned long long *)(p - 62048 + i);
unsigned long long x4 = *(unsigned long long *)(p - 64096 + i);
result *= x1 * x2 * x3 * x4;
}
return result;
}
Patch by jedilyn(Kewen Lin).
Differential Revision: https://reviews.llvm.org/D48813
--This line, and those below, will be ignored--
M lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
A test/CodeGen/PowerPC/preincprep-i64-check.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336074
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Piotr Padlewski [Mon, 2 Jul 2018 04:49:30 +0000 (04:49 +0000)]
Implement strip.invariant.group
Summary:
This patch introduce new intrinsic -
strip.invariant.group that was described in the
RFC: Devirtualization v2
Reviewers: rsmith, hfinkel, nlopes, sanjoy, amharc, kuhar
Subscribers: arsenm, nhaehnle, JDevlieghere, hiraditya, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D47103
Co-authored-by: Krzysztof Pszeniczny <krzysztof.pszeniczny@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336073
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Eric Christopher [Mon, 2 Jul 2018 00:16:39 +0000 (00:16 +0000)]
Add an entry for rodata constant merge sections to the default
section flags in the ELF assembler. This matches the defaults
given in the rest of MC.
Fixes PR37997 where we couldn't assemble our own assembly output
without warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336072
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Craig Topper [Sun, 1 Jul 2018 23:49:06 +0000 (23:49 +0000)]
[X86] Fix a few test names in avx512-intrinsics-fast-isel.ll to match their clang intrinsic names.
I thought I fixed these yesterday, but I guess I missed a few.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336071
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Craig Topper [Sun, 1 Jul 2018 23:27:41 +0000 (23:27 +0000)]
[X86] Remove the places that return nullptr from X86InstrInfo::commuteInstructionImpl.
findCommutedOpIndices does the pre-checking for whether commuting is possible. There should be no reason left to fail in commuteInstructionImpl. There was a missing pre-check that I've added there and changed the check to an assert in commuteInstructionImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336070
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Simon Pilgrim [Sun, 1 Jul 2018 20:22:46 +0000 (20:22 +0000)]
[SLPVectorizer] Call InstructionsState.isOpcodeOrAlt with Instruction instead of an opcode. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336069
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Simon Pilgrim [Sun, 1 Jul 2018 20:07:30 +0000 (20:07 +0000)]
[SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsState.isOpcodeOrAlt helper. NFCI.
This is a basic step towards matching more general instructions types than just opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336068
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Craig Topper [Sun, 1 Jul 2018 17:50:29 +0000 (17:50 +0000)]
[X86][Disassembler] Remove TYPE_BNDR from translateImmediate.
I've check the disassembler tables and this shouldn't be reachable. Which is good since if it was reachable there should have been a 'return' after the addOperand line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336066
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Sanjay Patel [Sun, 1 Jul 2018 17:14:37 +0000 (17:14 +0000)]
[InstCombine] add abs tests with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336065
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Sanjay Patel [Sun, 1 Jul 2018 13:42:57 +0000 (13:42 +0000)]
[PatternMatch] allow undef elements in vectors with m_Neg
This is similar to the m_Not change from D44076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336064
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Simon Pilgrim [Sun, 1 Jul 2018 13:41:58 +0000 (13:41 +0000)]
[SLPVectorizer] Use InstructionsState Op/Alt opcodes directly. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336063
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David Green [Sun, 1 Jul 2018 12:47:30 +0000 (12:47 +0000)]
[UnrollAndJam] New Unroll and Jam pass
This is a simple implementation of the unroll-and-jam classical loop
optimisation.
The basic idea is that we take an outer loop of the form:
for i..
ForeBlocks(i)
for j..
SubLoopBlocks(i, j)
AftBlocks(i)
Instead of doing normal inner or outer unrolling, we unroll as follows:
for i... i+=2
ForeBlocks(i)
ForeBlocks(i+1)
for j..
SubLoopBlocks(i, j)
SubLoopBlocks(i+1, j)
AftBlocks(i)
AftBlocks(i+1)
Remainder Loop
So we have unrolled the outer loop, then jammed the two inner loops into
one. This can lead to a simpler inner loop if memory accesses can be shared
between the now jammed loops.
To do this we have to prove that this is all safe, both for the memory
accesses (using dependence analysis) and that ForeBlocks(i+1) can move before
AftBlocks(i) and SubLoopBlocks(i, j).
Differential Revision: https://reviews.llvm.org/D41953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336062
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Paul Semel [Sun, 1 Jul 2018 11:54:09 +0000 (11:54 +0000)]
Revert "[llvm-readobj] Fix printing format"
There is a problem with the formatting on windows build.
I need to investigate on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336061
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Simon Pilgrim [Sun, 1 Jul 2018 11:29:46 +0000 (11:29 +0000)]
[SLPVectorizer][X86] Add some alternate tests for cast operators
Alternate opcode handling only supports binary operators, these tests demonstrate missed opportunities to vectorize some sitofp/uitofp and fptosi/fptoui style casts as well as some (successful) float bits manipulations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336060
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Eugene Leviant [Sun, 1 Jul 2018 11:02:07 +0000 (11:02 +0000)]
[Evaluator] Improve evaluation of call instruction
Recommit of r335324 after buildbot failure fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336059
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Paul Semel [Sun, 1 Jul 2018 09:51:59 +0000 (09:51 +0000)]
[llvm-readobj] Fix printing format
We were printing every character, even those that weren't printable. It
doesn't really make sense for this option.
The string content was sticked to its address, added two spaces in
between.
Differential Revision: https://reviews.llvm.org/D48271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336058
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Craig Topper [Sun, 1 Jul 2018 05:54:22 +0000 (05:54 +0000)]
[X86] Remove unnecessary include. NFC
Leftover from when the pass contained a DenseMap before it switched to binary search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336057
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Craig Topper [Sun, 1 Jul 2018 05:47:49 +0000 (05:47 +0000)]
[X86] Move the memory unfolding table creation into its own class and make it a ManagedStatic.
Also move the static folding tables, their search functions and the new class into new cpp/h files.
The unfolding table is effectively static data. It's just a different ordering and a subset of the static folding tables.
By putting it in a separate ManagedStatic we ensure we only have one copy instead of one per X86InstrInfo object. This way also makes it only get initialized when really needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336056
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Craig Topper [Sat, 30 Jun 2018 22:38:42 +0000 (22:38 +0000)]
[X86] Move the X86InstrFMA3Info class into the cpp file. Expose only a getFMA3Group free function. NFCI
The class only exists to hold a DenseMap and is only created as a ManagedStatic. It used to expose a single static method that outside code was expected to use.
This patch moves that static function out of the class and moves it implementation into the cpp file. It can now access the ManagedStatic directly by name without the need for the other static method that accessed the ManagedStatic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336055
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Craig Topper [Sat, 30 Jun 2018 22:38:41 +0000 (22:38 +0000)]
[X86] Remove the AsmName from the HAX,HDX,HCX,HBX,HSI,HDI,HBP,HSP,HIP artificial registers so they can't be parsed by the assembly parser.
There are no instructions that use them so they weren't causing any bad matches. But they weren't being diagnosed as "invalid register name" if they were used and would instead trigger some form of invalid operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336054
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Craig Topper [Sat, 30 Jun 2018 18:30:31 +0000 (18:30 +0000)]
[X86] Use MVT::i8 for scalar shift amounts since that is what they ultimately need to legalize to.
I believe all of these are constants so legalizing them should be pretty trivial, but this saves a step.
In one case it looks like we may have been creating a shift amount larger than the shift input itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336052
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Craig Topper [Sat, 30 Jun 2018 17:49:42 +0000 (17:49 +0000)]
[X86] When combining load to BZHI, make sure we create the shift instruction with an i8 type.
This combine runs pretty late and causes us to introduce a shift after the op legalization phase has run. We need to be sure we create the shift with the proper type for the shift amount. If we don't do this, we will still re-legalize the operation properly, but we won't get a chance to fully optimize the truncate that gets inserted.
So this patch adds the necessary truncate when the shift is created. I've also narrowed the subtract that gets created to always be an i32 type. The truncate would have trigered SimplifyDemandedBits to optimize it anyway. But using a more appropriate VT here is free and saves an optimization step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336051
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Sanjay Patel [Sat, 30 Jun 2018 14:11:46 +0000 (14:11 +0000)]
[InstCombine] add tests for negate vector with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336050
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Simon Pilgrim [Sat, 30 Jun 2018 12:24:23 +0000 (12:24 +0000)]
Fix Wdocumentation compiler warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336049
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Simon Pilgrim [Sat, 30 Jun 2018 12:22:55 +0000 (12:22 +0000)]
[DAGCombiner] Handle correctly non-splat power of 2 -1 divisor (PR37119)
The combine added in commit 329525 overlooked the case where one, but not all, of the divisor elements is -1, -1 is the only power of two value for which the sdiv expansion recipe breaks.
Thanks to @zvi for the original patch.
Differential Revision: https://reviews.llvm.org/D45806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336048
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Craig Topper [Sat, 30 Jun 2018 07:25:29 +0000 (07:25 +0000)]
[X86] Update some avx512 fast-isel tests to match their real clang IRgen.
Especially of note was the test_mm_mask_set1_epi64 and other set1 tests that were truncating the element to be broadcasted to i8 and broadcasting that instead of a whole 64 bit value.
Some of the others were just correcting mask sizes on parameters due to bugs in the clang test case they were generated from that have now been fixed.
Some were converting i8 to <4 x i1>/<2 x i1> by truncating to i4/i2 and then bitcasting. But the clang codegen is bitcast to <8 x i1>, then extract to <4 x i1>/<2 x i1>. This is likely to incur less trouble from the integer type legalizer in the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336045
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Craig Topper [Sat, 30 Jun 2018 06:45:10 +0000 (06:45 +0000)]
[X86] Change some chec-prefixes from X32 to X86 to match the FileCheck command line.
I think this test changed and these test cases were created around the same time and missed the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336044
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Craig Topper [Sat, 30 Jun 2018 06:45:09 +0000 (06:45 +0000)]
[X86] Remove test cases from avx512vl-intrinsics-fast-isel.ll for intrinsics that don't really exist in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336043
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Tom Stellard [Sat, 30 Jun 2018 04:09:44 +0000 (04:09 +0000)]
AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal.
Summary:
We could split sizes that are not power of two into smaller sized
G_IMPLICIT_DEF instructions, but this ends up generating
G_MERGE_VALUES instructions which we then have to handle in the instruction
selector. Since G_IMPLICIT_DEF is really a no-op it's easier just to
keep everything that can fit into a register legal.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336041
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Jessica Paquette [Sat, 30 Jun 2018 03:56:03 +0000 (03:56 +0000)]
[MachineOutliner] Add support for target-default outlining.
This adds functionality to the outliner that allows targets to
specify certain functions that should be outlined from by default.
If a target supports default outlining, then it specifies that in
its TargetOptions. In the case that it does, and the user hasn't
specified that they *never* want to outline, the outliner will
be added to the pass pipeline and will run on those default functions.
This is a preliminary patch for turning the outliner on by default
under -Oz for AArch64.
https://reviews.llvm.org/D48776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336040
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Craig Topper [Sat, 30 Jun 2018 01:32:04 +0000 (01:32 +0000)]
[X86] Remove masking from avx512 rotate intrinsics. Use select in IR instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336035
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Chandler Carruth [Fri, 29 Jun 2018 23:36:03 +0000 (23:36 +0000)]
[instsimplify] Move the instsimplify pass to use more obvious file names
and diretory.
Also cleans up all the associated naming to be consistent and removes
the public access to the pass ID which was unused in LLVM.
Also runs clang-format over parts that changed, which generally cleans
up a bunch of formatting.
This is in preparation for doing some internal cleanups to the pass.
Differential Revision: https://reviews.llvm.org/D47352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336028
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Zachary Turner [Fri, 29 Jun 2018 22:19:02 +0000 (22:19 +0000)]
[CodeView] Correctly compute the name of S_PROCREF symbols.
We have a function which switches on the type of a symbol record
to return a hardcoded offset into the record that contains the
symbol name. Not all symbols have names to begin with, and for
those records we return -1 for the offset.
Names are used for various things. Importantly for this particular
bug, a hash of the record name is used as a key for certain hash
tables which are serialied into the PDB file. One of these hash
tables is for the global symbol stream, which is basically a
collection of S_PROCREF symbols which contain the name of the
symbol, a module, and an address offset.
However, for S_PROCREF symbols, the function to return the offset
of the name was returning -1: basically it wasn't implemented.
As a result of this, all global symbols were hashing to the same
value, essentially it was as if every single global symbol's name
was the empty string.
This manifests in the VS debugger when you try to call a function
(global or member, doesn't matter) through the immediate window
and the debugger simply reports an error because it can't find the
function. This makes perfect sense, because it is hashing the name
for real, looking in the global symbol hash table, and there is only
1 entry there which corresponds to a symbol whose name is the empty
string.
Fixing this fixes the MSVC debugger in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336024
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Heejin Ahn [Fri, 29 Jun 2018 21:27:20 +0000 (21:27 +0000)]
[WebAssembly] Update comments for non-splat pow2 vector test case
Summary:
After rL335727, (sdiv X, 1) is treated as a special case, so we can
safely transform 'sdiv's in non-splat pow vectors into 'shr's even when
some of its entries are '1'. The test expectations have been already
fixed in rL335771, but the comments were out of date.
Also changed the filename from `vector_sdiv.ll` to `vector-sdiv.ll` to
be consistent with other test file names.
Reviewers: RKSimon
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336018
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Heejin Ahn [Fri, 29 Jun 2018 21:19:22 +0000 (21:19 +0000)]
[WebAssembly] Comment out a switch block in ISelDAGToDAG
Summary: Fixes PR37977.
Reviewers: RKSimon
Subscribers: dschuff, sbc100, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336017
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Alina Sbirlea [Fri, 29 Jun 2018 20:46:16 +0000 (20:46 +0000)]
[MemorySSA] Add APIs to MemoryPhis to delete incoming blocks/values, and an updater API to remove blocks.
Summary:
MemoryPhis now have APIs analogous to BB Phis to remove an incoming value/block.
The MemorySSAUpdater uses the above APIs when updating MemorySSA given a set of dead blocks about to be deleted.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D48396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336015
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Alex Shlyapnikov [Fri, 29 Jun 2018 20:20:17 +0000 (20:20 +0000)]
[HWASan] Do not retag allocas before return from the function.
Summary:
Retagging allocas before returning from the function might help
detecting use after return bugs, but it does not work at all in real
life, when instrumented and non-instrumented code is intermixed.
Consider the following code:
F_non_instrumented() {
T x;
F1_instrumented(&x);
...
}
{
F_instrumented();
F_non_instrumented();
}
- F_instrumented call leaves the stack below the current sp tagged
randomly for UAR detection
- F_non_instrumented allocates its own vars on that tagged stack,
not generating any tags, that is the address of x has tag 0, but the
shadow memory still contains tags left behind by F_instrumented on the
previous step
- F1_instrumented verifies &x before using it and traps on tag mismatch,
0 vs whatever tag was set by F_instrumented
Reviewers: eugenis
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D48664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336011
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Vedant Kumar [Fri, 29 Jun 2018 20:13:13 +0000 (20:13 +0000)]
[LLVMContext] Detecting leaked instructions with metadata
When instructions with metadata are accidentally leaked, the result is a
difficult-to-find memory corruption in ~LLVMContextImpl that leads to
random crashes.
Patch by Arvīds Kokins!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336010
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Paul Robinson [Fri, 29 Jun 2018 19:17:44 +0000 (19:17 +0000)]
Pass DWARFUnit to verifier by reference not by value. I am moderately
sure this should not cause a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336007
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Sean Fertile [Fri, 29 Jun 2018 17:48:58 +0000 (17:48 +0000)]
Revert "Extend CFGPrinter and CallPrinter with Heat Colors"
This reverts r335996 which broke graph printing in Polly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336000
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Matt Arsenault [Fri, 29 Jun 2018 17:31:42 +0000 (17:31 +0000)]
AMDGPU: Don't use struct type for argument layout
This was introducing unnecessary padding after the explicit
arguments, depending on the alignment of the total struct type.
Also has the side effect of avoiding creating an extra GEP for
the offset from the base kernel argument to the explicit kernel
argument offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335999
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Craig Topper [Fri, 29 Jun 2018 17:24:07 +0000 (17:24 +0000)]
[X86] Limit the number of target specific nodes emitted in LowerShiftParts
The important part is the creation of the SHLD/SHRD nodes. The compare and the conditional move can use target independent nodes that can be legalized on their own. This gives some opportunities to trigger the optimizations present in the lowering for those things. And its just better to limit the number of places we emit target specific nodes.
The changed test cases still aren't optimal.
Differential Revision: https://reviews.llvm.org/D48619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335998
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Sean Fertile [Fri, 29 Jun 2018 17:13:58 +0000 (17:13 +0000)]
Extend CFGPrinter and CallPrinter with Heat Colors
Extends the CFGPrinter and CallPrinter with heat colors based on heuristics or
profiling information. The colors are enabled by default and can be toggled
on/off for CFGPrinter by using the option -cfg-heat-colors for both
-dot-cfg[-only] and -view-cfg[-only]. Similarly, the colors can be toggled
on/off for CallPrinter by using the option -callgraph-heat-colors for both
-dot-callgraph and -view-callgraph.
Patch by Rodrigo Caetano Rocha!
Differential Revision: https://reviews.llvm.org/D40425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335996
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Jonas Devlieghere [Fri, 29 Jun 2018 17:11:34 +0000 (17:11 +0000)]
[dsymutil] Rename conflicting declaration
Using MemoryBuffer as member name clashed with the llvm::MemoryBuffer
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335995
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Craig Topper [Fri, 29 Jun 2018 17:11:26 +0000 (17:11 +0000)]
[X86] Use a std::vector for the memory unfolding table.
Previously we used a DenseMap which is costly to set up due to multiple full table rehashes as the size increases and causes the table to be reallocated.
This patch changes the table to a vector of structs. We now walk the reg->mem tables and push new entries in the mem->reg table for each row not marked TB_NO_REVERSE. Once all the table entries have been created, we sort the vector. Then we can use a binary search for lookups.
Differential Revision: https://reviews.llvm.org/D48585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335994
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Jonas Devlieghere [Fri, 29 Jun 2018 16:51:52 +0000 (16:51 +0000)]
[dsymutil] Make the CachedBinaryHolder the default
Replaces all uses of the old binary holder with its cached variant.
Differential revision: https://reviews.llvm.org/D48770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335991
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Jonas Devlieghere [Fri, 29 Jun 2018 16:50:41 +0000 (16:50 +0000)]
[dsymutil] Introduce a new CachedBinaryHolder
The original binary holder has an optimization where it caches a static
library (archive) between consecutive calls to GetObjects. However, the
actual memory buffer wasn't cached between calls.
This made sense when dsymutil was processing objects one after each
other, but when processing them in parallel, several binaries have to be
in memory at the same time. For this reason, every link context
contained a binary holder.
Having one binary holder per context is problematic, because the same
static archive was cached for every object file. Luckily, when the file
is mmap'ed, this was only costing us virtual memory.
This patch introduces a new BinaryHolder variant that is fully cached,
for all the object files it load, as well as the static archives. This
way, we don't have to give up on this optimization of bypassing the
file system.
Differential revision: https://reviews.llvm.org/D48501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335990
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Petar Jovanovic [Fri, 29 Jun 2018 16:37:16 +0000 (16:37 +0000)]
[mips] Support shrink-wrapping
Except for -O0, it's enabled by default.
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D47947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335989
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Stanislav Mekhanoshin [Fri, 29 Jun 2018 16:26:53 +0000 (16:26 +0000)]
[AMDGPU] Enable LICM in the BE pipeline
This allows to hoist code portion to compute reciprocal of loop
invariant denominator in integer division after codegen prepare
expansion.
Differential Revision: https://reviews.llvm.org/D48604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335988
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Jessica Paquette [Fri, 29 Jun 2018 16:12:45 +0000 (16:12 +0000)]
[MachineOutliner] Add always and never options to -enable-machine-outliner
This is a recommit of r335887, which was erroneously committed earlier.
To enable the MachineOutliner by default on AArch64, we need to be able to
disable the MachineOutliner and also provide an option to "always" enable the
outliner.
This adds that capability. It allows the user to still use the old
-enable-machine-outliner option, which defaults to "always". This is building
up to allowing the user to specify "always" versus the target default
outlining behaviour.
https://reviews.llvm.org/D48682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335986
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Sanjay Patel [Fri, 29 Jun 2018 15:28:11 +0000 (15:28 +0000)]
[InstCombine] add more tests for shuffle-binop folds; NFC
The mul+shl tests add coverage for the fold enabled with D48678.
The and+or tests are not handled yet; that's D48662.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335984
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Andrea Di Biagio [Fri, 29 Jun 2018 14:24:46 +0000 (14:24 +0000)]
[llvm-mca] Remove field HasReadAdvanceEntries from class ReadDescriptor.
This simplifies the logic that updates RAW dependencies in the DispatchStage.
There is no advantage in storing that flag in the ReadDescriptor; we should
simply rely on the call to `STI.getReadAdvanceCycles()` to obtain the
ReadAdvance cycles. If there are no read-advance entries, then method
`getReadAdvanceCycles()` quickly returns 0.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335977
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Alexey Bataev [Fri, 29 Jun 2018 14:23:28 +0000 (14:23 +0000)]
[DEBUG_INFO, NVPTX] Do not emit .debug_loc section.
Summary:
.debug_loc section is not supported for NVPTX target. If there is an
object whose location can change during its lifetime, we do not generate
debug location info for this variable.
Reviewers: echristo
Subscribers: jholewinski, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D48730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335976
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Krzysztof Parzyszek [Fri, 29 Jun 2018 13:55:28 +0000 (13:55 +0000)]
[Hexagon] Remove unused instruction itineraties, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335975
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Sanjay Patel [Fri, 29 Jun 2018 13:44:06 +0000 (13:44 +0000)]
[InstCombine] enhance shuffle-of-binops to allow different variable ops (PR37806)
This was discussed in D48401 as another improvement for:
https://bugs.llvm.org/show_bug.cgi?id=37806
If we have 2 different variable values, then we shuffle (select) those lanes,
shuffle (select) the constants, and then perform the binop. This eliminates a binop.
The new shuffle uses the same shuffle mask as the existing shuffle, so there's no
danger of creating a difficult shuffle.
All of the earlier constraints still apply, but we also check for extra uses to
avoid creating more instructions than we'll remove.
Additionally, we're disallowing the fold for div/rem because that could expose a
UB hole.
Differential Revision: https://reviews.llvm.org/D48678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335974
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Roman Shirokiy [Fri, 29 Jun 2018 11:46:30 +0000 (11:46 +0000)]
Fix overconfident assert in ScalarEvolution::isImpliedViaMerge
We can have AddRec with loops having many predecessors.
This changes an assert to an early return.
Differential Revision: https://reviews.llvm.org/D48766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335965
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Sjoerd Meijer [Fri, 29 Jun 2018 11:03:15 +0000 (11:03 +0000)]
[AArch64] Armv8.4-A: Virtualization system registers
This adds the Secure EL2 extension.
Differential Revision: https://reviews.llvm.org/D48711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335962
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Filipe Cabecinhas [Fri, 29 Jun 2018 10:34:37 +0000 (10:34 +0000)]
[cmake] Change WIN32 test to CMAKE_HOST_WIN32
The test is about what can be run on the host, not the cmake target.
When cross-compiling (compiler-rt at least) on Windows, we end up with
lit being unable to run llvm-lit because it can't find the llvm-lit
module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335961
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Simon Pilgrim [Fri, 29 Jun 2018 09:36:39 +0000 (09:36 +0000)]
[X86][SSE] Support v16i8/v32i8 vector rotations
This uses the same technique as for shifts - split the rotation into 4/2/1-bit partial rotations and select those partials based on the amount bit, making use of PBLENDVB if available. This halves the use of PBLENDVB compared to expanding to shifts, which can be a slow op.
Unfortunately I haven't found a decent way to share much of this code with the shift equivalent.
Differential Revision: https://reviews.llvm.org/D48655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335957
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Sjoerd Meijer [Fri, 29 Jun 2018 08:43:19 +0000 (08:43 +0000)]
[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335953
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Roman Lebedev [Fri, 29 Jun 2018 07:44:20 +0000 (07:44 +0000)]
SCEVExpander::expandAddRecExprLiterally(): check before casting as Instruction
Summary:
An alternative to D48597.
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=37936 | PR37936 ]].
The problem is as follows:
1. `indvars` marks `%dec` as `NUW`.
2. `loop-instsimplify` runs `instsimplify`, which constant-folds `%dec` to -1 (D47908)
3. `loop-reduce` tries to do some further modification, but crashes
with an type assertion in cast, because `%dec` is no longer an `Instruction`,
If the runline is split into two, i.e. you first run `-indvars -loop-instsimplify`,
store that into a file, and then run `-loop-reduce`, there is no crash.
So it looks like the problem is due to `-loop-instsimplify` not discarding SCEV.
But in this case we can just not crash if it's not an `Instruction`.
This is just a local fix, unlike D48597, so there may very well be other problems.
Reviewers: mkazantsev, uabelho, sanjoy, silviu.baranga, wmi
Reviewed By: mkazantsev
Subscribers: evstupac, javed.absar, spatel, llvm-commits
Differential Revision: https://reviews.llvm.org/D48599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335950
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Kristof Beyls [Fri, 29 Jun 2018 07:16:27 +0000 (07:16 +0000)]
Make email options of find_interesting_reviews more flexible.
This enables a few requested improvements on the original review of this
script at https://reviews.llvm.org/D46192.
This introduces 2 new command line options:
* --email-report: This option enables specifying who to email the generated
report to. This also enables not sending any email and only printing out
the report on stdout by not specifying this option on the command line.
* --sender: this allows specifying the email address that will be used in
the "From" email header.
I believe that with these options the script starts having the basic
features needed to run it well on a regular basis for a group of
developers.
Differential Revision: https://reviews.llvm.org/D47930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335948
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Craig Topper [Fri, 29 Jun 2018 05:43:26 +0000 (05:43 +0000)]
[X86] Remove masking from the avx512 packed sqrt intrinsics. Use select in IR instead.
While there improve the coverage of the intrinsic testing and add fast-isel tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335944
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Tom Stellard [Thu, 28 Jun 2018 23:47:12 +0000 (23:47 +0000)]
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335942
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Sterling Augustine [Thu, 28 Jun 2018 23:22:14 +0000 (23:22 +0000)]
Require x86 for this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335939
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Eli Friedman [Thu, 28 Jun 2018 21:49:41 +0000 (21:49 +0000)]
[ARM] Assert that ARMDAGToDAGISel creates valid UBFX/SBFX nodes.
We don't ever check these again (unless you're using
-fno-integrated-as), so make sure the extracted bits are well-defined.
I don't think it's possible to trigger any of the assertions on trunk,
but it's difficult to prove. (The first one depends on DAGCombine to
minimize the number of set bits in AND masks; I think the others are
mathematically impossible to hit.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335931
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Jessica Paquette [Thu, 28 Jun 2018 21:49:24 +0000 (21:49 +0000)]
[MachineOutliner] Never add the outliner in -O0
This is a recommit of r335879.
We shouldn't add the outliner when compiling at -O0 even if
-enable-machine-outliner is passed in. This makes sure that we
don't add it in this case.
This also removes -O0 from the outliner DWARF test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335930
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Sanjay Patel [Thu, 28 Jun 2018 21:14:02 +0000 (21:14 +0000)]
[InstCombine] adjust shuffle tests; NFC
Use xor for the extra uses test because div/rem have other problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335924
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Jake Ehrlich [Thu, 28 Jun 2018 21:07:34 +0000 (21:07 +0000)]
[llvm-readobj] Add experimental support for SHT_RELR sections
This change adds experimental support for SHT_RELR sections, proposed
here: https://groups.google.com/forum/#!topic/generic-abi/bX460iggiKg
Definitions for the new ELF section type and dynamic array tags, as well
as the encoding used in the new section are all under discussion and are
subject to change. Use with caution!
Author: rahulchaudhry
Differential Revision: https://reviews.llvm.org/D47919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335922
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Benjamin Kramer [Thu, 28 Jun 2018 21:03:24 +0000 (21:03 +0000)]
[SupportTests] Silence -Wsign-compare warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335921
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Sanjay Patel [Thu, 28 Jun 2018 20:52:43 +0000 (20:52 +0000)]
[InstCombine] fix opcode check in shuffle fold
There's no way to expose this difference currently,
but we should use the updated variable because the
original opcodes can go stale if we transform into
something new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335920
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Martin Storsjo [Thu, 28 Jun 2018 20:28:29 +0000 (20:28 +0000)]
[COFF] Fix constant sharing regression for MinGW
This fixes a regression since SVN r334523, where the object files
built targeting MinGW were rejected by GNU binutils tools. Prior to
that commit, we only put constants in comdat for MSVC configurations.
Differential Revision: https://reviews.llvm.org/D48567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335918
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Zachary Turner [Thu, 28 Jun 2018 20:09:37 +0000 (20:09 +0000)]
Fix padding with custom character in formatv.
The format string for formatv allows to specify a custom padding
character instead of the default space. This custom character was
parsed correctly, but not passed on to the formatter.
Patch by Marcel Köppe
Differential Revision: https://reviews.llvm.org/D48140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335915
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Teresa Johnson [Thu, 28 Jun 2018 20:07:47 +0000 (20:07 +0000)]
[ThinLTO] Port InlinerFunctionImportStats handling to new PM
Summary:
The InlinerFunctionImportStats will collect and dump stats regarding how
many function inlined into the module were imported by ThinLTO.
Reviewers: wmi, dexonsmith
Subscribers: mehdi_amini, inglorion, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D48729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335914
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Benjamin Kramer [Thu, 28 Jun 2018 20:05:35 +0000 (20:05 +0000)]
[NVPTX] Delete dead code
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335913
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Eli Friedman [Thu, 28 Jun 2018 19:53:12 +0000 (19:53 +0000)]
[ARM] Add missing Thumb2 assembler diagnostics.
Mostly just adding checks for Thumb2 instructions which correspond to
ARM instructions which already had diagnostics. While I'm here, also fix
ARM-mode strd to check the input registers correctly.
Differential Revision: https://reviews.llvm.org/D48610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335909
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Sterling Augustine [Thu, 28 Jun 2018 19:47:23 +0000 (19:47 +0000)]
Some targets don't have lld built, so just use a binary copy
of the input file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335908
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Anastasis Grammenos [Thu, 28 Jun 2018 18:58:30 +0000 (18:58 +0000)]
[SROA] Preserve DebugLoc when rewriting alloca partitions
When rewriting an alloca partition copy the DL from the
old alloca over the the new one.
Differential Revision: https://reviews.llvm.org/D48640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335904
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Sterling Augustine [Thu, 28 Jun 2018 18:57:13 +0000 (18:57 +0000)]
Handle absolute symbols as branch targets in disassembly.
https://reviews.llvm.org/D48554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335903
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Zachary Turner [Thu, 28 Jun 2018 18:49:09 +0000 (18:49 +0000)]
Add a flag to FileOutputBuffer that allows modification.
FileOutputBuffer creates a temp file and on commit atomically
renames the temp file to the destination file. Sometimes we
want to modify an existing file in place, but still have the
atomicity guarantee. To do this we can initialize the contents
of the temp file from the destination file (if it exists), that
way the resulting FileOutputBuffer can have only selective
bytes modified. Committing will then atomically replace the
destination file as desired.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335902
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Simon Pilgrim [Thu, 28 Jun 2018 18:37:16 +0000 (18:37 +0000)]
Remove unnecessary semicolon. NFCI.
Fixes -Wpedantic warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335901
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Justin Bogner [Thu, 28 Jun 2018 18:36:52 +0000 (18:36 +0000)]
[CMake] Respect CMAKE_STRIP and CMAKE_DSYMUTIL on apple platforms
This allows overriding the strip and dsymutil tools, and updates
iOS.cmake to do so. I've also added libtool to iOS.cmake, but it was
already respecting CMAKE_LIBTOOL if set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335900
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Vedant Kumar [Thu, 28 Jun 2018 18:21:11 +0000 (18:21 +0000)]
[Debugify] Do not report line 0 locations as errors
The checking logic should not treat artificial locations as being
somehow problematic. Producing these locations can be the desired
behavior of some passes.
See llvm.org/PR37961.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335897
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Craig Topper [Thu, 28 Jun 2018 17:58:01 +0000 (17:58 +0000)]
[X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.
This is a follow up to r335753. At the time I forgot about isProfitableToFold which makes this pretty easy.
Differential Revision: https://reviews.llvm.org/D48706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335895
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Jonas Devlieghere [Thu, 28 Jun 2018 17:56:43 +0000 (17:56 +0000)]
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
Reverting because this is causing failures in the LLDB test suite on
GreenDragon.
LLVM ERROR: unsupported relocation with subtraction expression, symbol
'__GLOBAL_OFFSET_TABLE_' can not be undefined in a subtraction
expression
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335894
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Jonas Devlieghere [Thu, 28 Jun 2018 17:56:27 +0000 (17:56 +0000)]
Revert "[OrcMCJIT] Fix test after r335508 causing it to fail on green dragon"
This reverts commit
a6b904daa1d55e31187c85e5b54ef2ddc37fa713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335893
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Zachary Turner [Thu, 28 Jun 2018 17:55:54 +0000 (17:55 +0000)]
2 VS natvis improvements.
Optional<T> was broken due to a change in the class's internals.
That is fixed, and additionally a visualizer is added for
Expected<T>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335892
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Zachary Turner [Thu, 28 Jun 2018 17:52:06 +0000 (17:52 +0000)]
Set line ending style of llvm.natvis to CRLF.
This file is used by MSVC which is obviously a Windows-only tool and prefers windows line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335889
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Sanjay Patel [Thu, 28 Jun 2018 17:48:04 +0000 (17:48 +0000)]
[InstCombine] allow shl+mul combos with shuffle (select) fold (PR37806)
This is an enhancement to D48401 that was discussed in:
https://bugs.llvm.org/show_bug.cgi?id=37806
We can convert a shift-left-by-constant into a multiply (we canonicalize IR in the other
direction because that's generally better of course). This allows us to remove the shuffle
as we do in the regular opcodes-are-the-same cases.
This requires a small hack to make sure we don't introduce any extra poison:
https://rise4fun.com/Alive/ZGv
Other examples of opcodes where this would work are add+sub and fadd+fsub, but we already
canonicalize those subs into adds, so there's nothing to do for those cases AFAICT. There
are planned enhancements for opcode transforms such or -> add.
Note that there's a different fold needed if we've already managed to simplify away a binop
as seen in the test based on PR37806, but we manage to get that one case here because this
fold is positioned above the demanded elements fold currently.
Differential Revision: https://reviews.llvm.org/D48485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335888
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Jessica Paquette [Thu, 28 Jun 2018 17:45:43 +0000 (17:45 +0000)]
[MachineOutliner] Define MachineOutliner support in TargetOptions
Targets should be able to define whether or not they support the outliner
without the outliner being added to the pass pipeline. Before this, the
outliner pass would be added, and ask the target whether or not it supports the
outliner.
After this, it's possible to query the target in TargetPassConfig, before the
outliner pass is created. This ensures that passing -enable-machine-outliner
will not modify the pass pipeline of any target that does not support it.
https://reviews.llvm.org/D48683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335887
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Simon Pilgrim [Thu, 28 Jun 2018 17:33:41 +0000 (17:33 +0000)]
[DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)
We could get away with it for constant folded cases, but not for rL335719.
Thanks to Krzysztof Parzyszek for noticing.
Reapply original commit rL335821 which was reverted at rL335871 due to a WebAssembly bug that was fixed at rL335884.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335886
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Matt Davis [Thu, 28 Jun 2018 17:33:24 +0000 (17:33 +0000)]
[llvm-mca] Delete Pipeline's copy ctor and assignement operator.
Prevent copying of the Pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335885
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Simon Pilgrim [Thu, 28 Jun 2018 17:27:09 +0000 (17:27 +0000)]
[WebAssembly] Add getSetCCResultType placeholder override to handle vector compare results.
Necessary to get the rL335821 bugfix (which was reverted at rL335871) un-reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335884
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Jessica Paquette [Thu, 28 Jun 2018 17:26:19 +0000 (17:26 +0000)]
Revert "[MachineOutliner] Add always and never options to -enable-machine-outliner"
I accidentally committed this instead of D48683 because I haven't had coffee
yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335883
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Jessica Paquette [Thu, 28 Jun 2018 17:26:18 +0000 (17:26 +0000)]
Revert "[MachineOutliner] Never add the outliner in -O0"
This reverts commit
9c7c10e4073a0bc6a759ce5cd33afbac74930091.
It relies on r335872 since that introduces the machine outliner
flags test. I meant to commit D48683 in that commit, but got mixed
up and committed D48682 instead. So, I'm reverting this and
r335872, since D48682 hasn't made it through review yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335882
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