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Emil Velikov [Mon, 16 May 2016 17:55:08 +0000 (18:55 +0100)]
scons: gallium: link against nir as needed
... otherwise we'll produce uncomplete binaries with introduction of NIR
as alternative IR with next commits.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Jason Ekstrand [Mon, 16 May 2016 21:30:25 +0000 (14:30 -0700)]
i965/fs: Add an allow_spilling flag to brw_compile_fs
This allows us to disable spilling for blorp shaders since blorp state
setup doesn't handle spilling. Without this, blorp fails hard if you run
with INTEL_DEBUG=spill.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Francisco Jerez <currojerez@riseup.net>
Ilia Mirkin [Tue, 17 May 2016 07:27:02 +0000 (03:27 -0400)]
nvc0/ir: fix shared atomic lowering to preserve shared memory location
We were always doing atomics on shared memory location 0 instead of the
originally supplied location. Make sure to pass through the original
symbol and any indirection.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org # note: expect minor conflict
Rob Clark [Mon, 16 May 2016 17:37:24 +0000 (13:37 -0400)]
freedreno/ir3: fix compiler warning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 14 May 2016 19:40:54 +0000 (15:40 -0400)]
nir/validate: dump annotated shader with error msgs
Log all the errors, and at the end dump the shader w/ error annotations
to make it easier to see where the problems are.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Rob Clark [Mon, 16 May 2016 16:44:59 +0000 (12:44 -0400)]
nir/validate: assert() -> validate_assert()
Prep work for next patch.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Rob Clark [Sat, 14 May 2016 19:37:32 +0000 (15:37 -0400)]
nir/print: add support for print annotations
Caller can pass a hashtable mapping NIR object (currently instr or var,
but I guess others could be added as needed) to annotation msg to print
inline with the shader dump. As the annotation msg is printed, it is
removed from the hashtable to give the caller a way to know about any
unassociated msgs.
This is used in the next patch, for nir_validate to try to associate
error msgs to nir_print dump.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Alejandro Piñeiro [Tue, 26 Apr 2016 12:35:24 +0000 (14:35 +0200)]
i965: Expose OpenGL 4.2 for gen8+
ARB_vertex_attrib_64bit was the only feature missing.
v2: we can expose 4.2 instead of 4.1 (Ian Romanick)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alejandro Piñeiro [Tue, 26 Apr 2016 12:37:38 +0000 (14:37 +0200)]
docs: Mark ARB_vertex_attrib_64bit as done for i965/gen8+
v2: label as done for i965/gen8+ instead of i965 (Kenneth Graunke)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alejandro Piñeiro [Sat, 12 Mar 2016 11:34:06 +0000 (12:34 +0100)]
i965: Enable ARB_vertex_attrib_64bit for gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Fri, 15 Apr 2016 10:51:05 +0000 (12:51 +0200)]
i965: take care of doubles when lowering VS inputs
Input attributes can require 2 vec4 or 1 vec4 depending on whether they
are double-precision or not.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Mon, 4 Apr 2016 10:47:57 +0000 (12:47 +0200)]
i965/fs: calculate first non-payload GRF using attrib slots
When computing where the first non-payload GRF starts, we can't rely on
the number of attributes, as each attribute can be using 1 or 2 slots
depending on whether they are a dvec3/4 or other.
Instead, we need to use the number of slots used by the attributes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Mon, 4 Apr 2016 10:47:57 +0000 (12:47 +0200)]
i965/vec4: use attribute slots to calculate URB read length
Do not use total attributes because a dvec3/dvec4 attribute requires two
slots. So rather use total attribute slots.
v2: do not use loop to calculate required attribute slots (Kenneth
Graunke)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Fri, 1 Apr 2016 15:25:03 +0000 (17:25 +0200)]
i965: take care of doubles when remapping VS attributes
Double-precision types require 1 slot in VUE for double and dvec2, and 2 slots for
anything else.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Fri, 15 Apr 2016 10:30:54 +0000 (12:30 +0200)]
nir: add double input bitmap
This bitmap tracks which input attributes are double-precision.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juan A. Suarez Romero [Thu, 31 Mar 2016 10:49:53 +0000 (11:49 +0100)]
i965/fs: shuffle 32bits into 64bits for doubles
VS Thread Payload handles attributes in URB as vec4, no matter if they
are actually single or double precision.
So with double-precision types, value ends up in the registers split in
32bits chunks, in different positions.
We need to shuffle the chunks to get the doubles correctly.
v2:
* Extra blank line. Add { } on if body (Ian Romanick)
* Use dest directly (Kenneth Graunke)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alejandro Piñeiro [Wed, 23 Mar 2016 11:20:05 +0000 (12:20 +0100)]
i965/fs: half exec_size when dealing with 64 bits attributes
The HW has a restriction that only vertical stride may cross register
boundaries. Until now this was only handled on VGRFs at
rw_reg_from_fs_reg, but it is also needed for attributes.
v2:
* Remove reference to commit id on commit message (Juan Suarez)
* Simplify code that compute final exec_size (Ian Romanick)
* Use REG_SIZE on that same code (Kenneth Graunke)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alejandro Piñeiro [Thu, 24 Mar 2016 10:49:53 +0000 (11:49 +0100)]
i965: passthru formats cannot be used width edge flag enabled
Add an assertion to detect this case.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Antia Puentes [Fri, 15 Apr 2016 09:32:46 +0000 (11:32 +0200)]
i965: Configure how to store *64*PASSTHRU vertex components
From the Broadwell specification, structure VERTEX_ELEMENT_STATE
description:
"When SourceElementFormat is set to one of the *64*_PASSTHRU
formats, 64-bit components are stored in the URB without any
conversion. In this case, vertex elements must be written as 128
or 256 bits, with VFCOMP_STORE_0 being used to pad the output
as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into
the URB, Component 1 must be specified as VFCOMP_STORE_0 (with
Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit
vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0
in order to output a 256-bit vertex element. Likewise, use of
R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0
in order to output a 256-bit vertex element."
Uses 128-bits to write double and dvec2 vertex elements, and 256-bits for
dvec3 and dvec4 vertex elements.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alejandro Piñeiro [Tue, 15 Mar 2016 11:53:07 +0000 (12:53 +0100)]
i965: get the proper vertex surface type for doubles on gen8+
This commit adds support for PASSTHRU format when pushing
double-precision attributes.
Check glarray->Doubles in order to know if we should choose a format
that does a conversion to float, or just passthru the 64-bit double.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 15 May 2016 19:35:04 +0000 (15:35 -0400)]
nvc0/ir: make sure out-of-bounds buffer loads/atomics get a 0 result
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Tue, 17 May 2016 01:18:50 +0000 (11:18 +1000)]
glsl: make reserved_varying_slot() static
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Sat, 27 Feb 2016 01:16:34 +0000 (12:16 +1100)]
glsl: include per-patch varyings when generating reserved slot bitfield
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 17 May 2016 01:34:38 +0000 (11:34 +1000)]
glsl: don't incorrectly eliminate patches with explicit locations
These varying have a separate location domain from per-vertex varyings
and need to be handled separately.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 17 May 2016 01:31:00 +0000 (11:31 +1000)]
glsl: remove remainings tabs in link_varyings.cpp
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 17 May 2016 01:29:40 +0000 (11:29 +1000)]
glsl: fix location and component packing validation on patches
These varyings have a separate location domain from per-vertex varyings
and need to be handled separately.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 17 May 2016 00:49:21 +0000 (17:49 -0700)]
i965: Enable ARB_shader_precision on Gen8+.
I recently fixed a bug in the Piglit tests:
https://lists.freedesktop.org/archives/piglit/2016-May/019802.html
With that patch in place, we pass all the tests. So, turn it on.
We could probably expose this earlier than Gen8, but the extension
says that OpenGL 4.0 is required, and all of our tests are written
against GLSL 4.00 (which is only supported on Gen8+).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Jose Fonseca [Mon, 16 May 2016 20:46:58 +0000 (21:46 +0100)]
vl/dri: Move the DRI3 check out of sources include into C.
Fixes SCons build.
Trivial. Built locally with SCons and autotools.
Leo Liu [Tue, 26 Apr 2016 15:23:53 +0000 (11:23 -0400)]
st/vdpau: add dri3 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 9 May 2016 20:03:41 +0000 (16:03 -0400)]
vl/dri3: implement functions for get and set timestamp
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 9 May 2016 19:53:48 +0000 (15:53 -0400)]
vl/dri3: handle PresentCompleteNotify event
and get timestamp calculated based on the event's reply
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 25 Apr 2016 20:07:21 +0000 (16:07 -0400)]
st/va: add dri3 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 9 May 2016 19:27:49 +0000 (15:27 -0400)]
vl/dri3: implement DRI3 BufferFromPixmap
We also need render to the front buffer of temporary X pixmap,
this is the case of when we using opengl as video out for vaapi.
the basic implementation is to pass pixmap ID to X server, and
then X will return dma-buf fd, we will get the buffer object
through this dma-buf fd.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 25 Apr 2016 19:49:28 +0000 (15:49 -0400)]
vl/dri3: add support for resizing
When drawable size changed, PresentConfigureNotify event will be
emitted, by handling the event to re-allocate resized buffer.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 9 May 2016 19:09:45 +0000 (15:09 -0400)]
vl/dri3: implement funciton for get dirty area
This will clear presentation area not covered by video content
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 25 Apr 2016 18:37:57 +0000 (14:37 -0400)]
vl/dri3: implement function for flush frontbuffer
Request drawable content in pixmap by calling DRI3 PresentPixmap,
and handle PresentIdleNotify event.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 10 May 2016 19:11:18 +0000 (15:11 -0400)]
vl/dri3: add back buffers support
This implements DRI3 PixmapFromBuffer. Create buffer objects, and
associate it to a dma-buf fd, and then pass this fd with a pixmap
ID to X server for creating pixmap object; also add a function
for wait events.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 25 Apr 2016 17:46:36 +0000 (13:46 -0400)]
vl/dri3: implement flushing for queued events
also place holder for present events handling
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 10 May 2016 18:56:51 +0000 (14:56 -0400)]
vl/dri3: register present events
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 25 Apr 2016 17:06:20 +0000 (13:06 -0400)]
vl/dri3: set drawable geometry
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 7 Mar 2016 19:51:32 +0000 (14:51 -0500)]
vl/dri3: add DRI3 support and implement create and destroy
Required functions into place for implementation, create screen
with device fd returned from X server, also bail out to DRI2
with certain conditions.
v2: -organize the error out path (Axel)
-squash previous patch 1 and 2 into one (Emil)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Dave Airlie [Mon, 16 May 2016 20:06:01 +0000 (06:06 +1000)]
mesa/version.c: enable cull distance in version check.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ian Romanick [Sat, 14 May 2016 00:45:49 +0000 (17:45 -0700)]
glsl/linker: Include the interface name for input and output blocks
On my oes_shader_io_blocks branch, this fixes 71
dEQP-GLES31.functional.program_interface_query.* tests.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Ian Romanick [Sat, 14 May 2016 00:44:58 +0000 (17:44 -0700)]
glsl/linker: Use canonical format for ARB_program_interface_query spec quotes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Fri, 13 May 2016 20:04:56 +0000 (13:04 -0700)]
i965: check tcs for NULL dereference
Coverity issue
1361544 found an instance where the tcs variable is
checked for NULL, but unconditionally dereferenced later in the same
function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 16 May 2016 18:08:55 +0000 (11:08 -0700)]
i965: Mark is_lossless_compressed_aux UNUSED to silence warning.
Used only in assert().
Matt Turner [Fri, 13 May 2016 20:25:41 +0000 (13:25 -0700)]
genxml: Use llroundf() and store to appropriate type.
Both functions return uint64_t, so I expect the masking/shifting should
be done on 64-bit types.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Fri, 13 May 2016 20:17:34 +0000 (13:17 -0700)]
nir: Mark nir_start_block()/nir_impl_last_block() with returns_nonnull.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 13 May 2016 20:17:02 +0000 (13:17 -0700)]
util: Add ATTRIBUTE_RETURNS_NONNULL.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jan Vesely [Mon, 16 May 2016 00:08:09 +0000 (20:08 -0400)]
clover: grid_offset should be padded with 0 not 1
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Tue, 23 Feb 2016 11:15:36 +0000 (12:15 +0100)]
i965: Expose OpenGL 4.0 for gen8+
ARB_gpu_shader_fp64 was the only feature missing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 23 Feb 2016 11:14:11 +0000 (12:14 +0100)]
docs: Mark ARB_gpu_shader_fp64 as done for i965/gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 23 Feb 2016 11:14:52 +0000 (12:14 +0100)]
i965: Enable ARB_gpu_shader_fp64 for gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 9 May 2016 07:43:56 +0000 (09:43 +0200)]
i965/tes/scalar: Fix load input for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Mon, 9 May 2016 13:23:34 +0000 (15:23 +0200)]
i965/tcs/scalar: fix store output for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 9 May 2016 08:31:50 +0000 (10:31 +0200)]
i965/tcs/scalar: fix load input for doubles
v2: do not write to the original indirect_offset since that is
an expression that could be used somewhere else (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 9 May 2016 08:14:48 +0000 (10:14 +0200)]
i965/fs: fix nir_intrinsic_store_output for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 9 May 2016 08:14:18 +0000 (10:14 +0200)]
i965/fs: fix number of output components for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 9 May 2016 13:21:25 +0000 (15:21 +0200)]
i965/vec4: handle doubles in type_size_vec4()
The scalar backend uses this to check URB input sizes.
v2: Removed redundant break after return (Curro)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Tue, 26 Jan 2016 09:30:39 +0000 (10:30 +0100)]
i965/fs: support doubles with shared variable stores
This is pretty much the same we do with SSBOs.
v2: do not shuffle in-place, it is not safe since the original 64-bit data
could be used after the write, instead use a temporary like we do
for SSBO stores (Iago)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 25 Jan 2016 12:42:19 +0000 (13:42 +0100)]
i965/fs: support doubles with ssbo stores
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 25 Jan 2016 12:37:50 +0000 (13:37 +0100)]
i965/fs: add shuffle_64bit_data_for_32bit_write helper
This does the inverse operation of shuffle_32bit_load_result_to_64bit_data
and we will use it when we need to write 64-bit data in the layout expected
by untyped write messages.
v2 (curro):
- Use subscript() instead of stride()
- Assert on the input types rather than silently retyping.
- Use offset() instead of horiz_offset(), drop the multiplier definition.
- Drop the temporary vgrf and force_writemask_all.
- Make component_i const.
- Move to brw_fs_nir.cpp
v3 (curro):
- Pass dst and src by reference.
- Simplify allocation of tmp register.
- Move to brw_fs_nir.cpp.
- Get rid of the temporary.
v3 (Iago):
- Check that the src and dst regions do not overlap, since that would
typically be a bug in the caller.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Mon, 25 Jan 2016 09:58:59 +0000 (10:58 +0100)]
i965/fs: support doubles with SSBO loads
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Thu, 5 May 2016 10:58:19 +0000 (12:58 +0200)]
i965/fs: support doubles with shared variable loads
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Thu, 5 May 2016 10:55:44 +0000 (12:55 +0200)]
i965/fs: Add do_untyped_vector_read helper
We are going to need the same logic for anything that reads
doubles via untyped messages (CS shared variables and SSBOs). Add a
helper function with that logic so that we can reuse it.
v2:
- Make this a static function instead of a method of fs_visitor (Iago)
- We only support types with a size of 4 or 8 (Curro)
- Avoid retypes by using a separate vgrf for the packed result (Curro)
- Put dst parameter before source parameters (Curro)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Wed, 13 Jan 2016 09:17:10 +0000 (10:17 +0100)]
i965/fs: support doubles with UBO loads
UBO loads with constant offset use the UNIFORM_PULL_CONSTANT_LOAD
instruction, which reads 16 bytes (a vec4) of data from memory. For dvec
types this only provides components x and y. Thus, if we are reading
more than 2 components we need to issue a second load at offset+16 to
read the next 16-byte chunk with components w and z.
UBO loads with non-constant offset emit a load for each component
in the vector (and rely in CSE to fix redundant loads), so we only
need to consider the size of the data type when computing the offset
of each element in a vector.
v2 (Sam):
- Adapt the code to use component() (Curro).
v3 (Sam):
- Use type_sz(dest.type) in VARYING_PULL_CONSTANT_LOAD() call (Curro).
- Add asserts to ensure std140 vector alignment rules are followed
(Curro).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Mon, 18 Jan 2016 12:09:31 +0000 (13:09 +0100)]
i965/fs: fix pull constant load component selection for doubles
UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4 starting at a
constant offset that is 16-byte aligned. If we need to access an unaligned
offset we emit a load with an aligned offset and use the remaining constant
offset to select the component into the vec4 result that we are interested
in. This component must be computed in units of the type size, since that
is what fs_reg::set_smear expects.
This patch does this change in the two places where we use this message:
In demote_pull_constants when we lower uniform access with constant offset
into the pull constant buffer and in UBO loads with constant offset.
v2 (Sam):
- Fix set_smear() in fs_visitor::lower_constant_loads(), take into account
source type instead and remove MAX2 (Curro).
- Improve changes to nir_intrinsic_load_ubo case in nir_emit_intrinsic()
(Curro).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Wed, 11 May 2016 19:54:26 +0000 (12:54 -0700)]
i965/fs: Fix and document component().
This fixes a number of bugs of component() by reimplementing it in
terms of horiz_offset(): Handling of base registers starting at a
non-zero subreg_offset, handling of strided registers and overflow of
subreg_offset into reg_offset.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Thu, 14 Jan 2016 07:55:28 +0000 (08:55 +0100)]
i965/fs: Fix fs_visitor::VARYING_PULL_CONSTANT_LOAD for doubles
v2 (Curro):
- Assert on scale == 1 when shuffling 64-bit data.
- Remove type_slots, use type_sz(vec4_result.type) instead.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Fri, 22 Jan 2016 13:00:38 +0000 (14:00 +0100)]
i965/fs: add shuffle_32bit_load_result_to_64bit_data helper
There will be a few places where we need to shuffle the result of a 32-bit
load into valid 64-bit data, so extract this logic into a separate helper
that we can reuse.
v2 (Curro):
- Use subscript() instead of stride()
- Assert on the input types rather than retyping.
- Use offset() instead of horiz_offset(), drop the multiplier definition.
- Don't use force_writemask_all.
- Mark component_i as const.
- Make the function name lower case.
v3 (Curro):
- Pass src and dst by reference.
- Move to brw_fs_nir.cpp
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Wed, 4 May 2016 04:26:13 +0000 (21:26 -0700)]
i965/fs: Stop using the LOAD_PAYLOAD instruction in lower_simd_width.
Instead of using the LOAD_PAYLOAD instruction (emitted through the
emit_transpose() helper that is no longer useful and this commit
removes) which had to be marked force_writemask_all in some cases,
emit a series of moves to apply proper channel enable signals to the
destination. Until now lower_simd_width() had mainly been used to
lower things that invariably had a basic block-local temporary as
destination so it didn't seem like a big deal, but I found it to be
the reason for several Piglit regressions in my SIMD32 branch and
Igalia discovered the same issue independently while working on FP64
support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Fri, 11 Mar 2016 07:46:36 +0000 (08:46 +0100)]
i965/fs: fix copy/constant propagation regioning checks
We were not accounting for subreg_offset in the check for the start
of the region.
Also, fs_reg::regs_read() already takes the stride into account, so we
should not multiply its result by the stride again. This was making
copy-propagation fail to copy-propagate cases that would otherwise be
safe to copy-propagate. Again, this was observed in fp64 code, since
there we use stride > 1 often.
v2 (Sam):
- Rename function and add comment (Jason, Curro).
- Assert that register files and number are the same (Jason).
- Fix code to take into account the assumption that src.subreg_offset
is strictly less than the reg_offset unit (Curro).
- Don't pass the registers by value to the function, use
'const fs_reg &' instead (Curro).
- Remove obsolete comment in the commit log (Curro).
v3 (Sam):
- Remove the assert and put the condition in the return (Curro).
- Fix function name (Curro).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Tue, 12 Apr 2016 11:53:24 +0000 (13:53 +0200)]
i965/fs: fix copy propagation from load payload
We were not considering the case where the load payload is writing to
a destination with a reg_offset > 0.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Fri, 11 Mar 2016 13:35:07 +0000 (14:35 +0100)]
i965/fs: fix copy propagation of partially invalidated entries
We were not invalidating entries with a src that reads more than one register
when we find writes that overwrite any register read by entry->src after
the first. This leads to incorrect copy propagation because we re-use
entries from the ACP that have been partially invalidated. Same thing for
entries with a dst that writes to more than one register.
v2 (Sam):
- Improve code by defining regions_overlap() and using it instead of a
loop (Curro).
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Tue, 10 May 2016 23:03:36 +0000 (16:03 -0700)]
i965/fs: Reindent register offset calculation of try_copy_propagate().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Tue, 10 May 2016 23:01:56 +0000 (16:01 -0700)]
i965/fs: Simplify and fix register offset calculation of try_copy_propagate().
try_copy_propagate() was special-casing UNIFORM registers (the
BAD_FILE, ARF and FIXED_GRF cases are dead, see the assertion at the
top of the function) and then failing to take into account the
possibility of the instruction reading from a non-zero offset of the
destination of the copy. The VGRF/ATTR handling takes it into account
correctly, and there is no reason we couldn't use the exact same logic
for the UNIFORM file aside from the fact that uniforms represent
reg_offset in different units. We can work around that easily by
defining an additional constant with the right unit reg_offset is
expressed in.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 23 Mar 2016 11:02:21 +0000 (12:02 +0100)]
i965/fs: disallow type change in copy-propagation if types have different sizes
Because the semantics of source modifiers are type-dependent, the type of the
original source of the copy must be kept unmodified while propagating it into
some instruction, which implies that we need to have the guarantee that the
meaning of the instruction is going to remain the same after we have changed
the types. Whenthe size of the new type is different from the size of the old
type the new and old instructions cannot possibly be equivalent because the new
instruction will be reading more data than the old one was.
Prevents that we turn this:
load_payload(8) vgrf17:DF, |vgrf4+0.0|:DF 1sthalf
mov(8) vgrf18:DF, vgrf17:DF 1sthalf
load_payload(8) vgrf5:DF, vgrf18:DF, vgrf20:DF NoMask 1sthalf WE_all
load_payload(8) vgrf21:UD, vgrf5+0.4<2>:UD 1sthalf
mov(8) vgrf22:UD, vgrf21:UD 1sthalf
into:
load_payload(8) vgrf17:DF, |vgrf4+0.0|:DF 1sthalf
mov(8) vgrf18:DF, |vgrf4+0.0|:DF 1sthalf
load_payload(8) vgrf5:DF, |vgrf4+0.0|:DF, |vgrf4+2.0|:DF NoMask 1sthalf WE_all
load_payload(8) vgrf21:UD, vgrf5+0.4<2>:UD 1sthalf
mov(8) vgrf22:DF, |vgrf4+0.4|<2>:DF 1sthalf
where the semantics of the last instruccion have changed.
v2 (Curro):
- Update commit log and add comment to explain the problem better.
- Simplify the condition.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 18 Jan 2016 09:44:20 +0000 (10:44 +0100)]
i965/fs: Fix copy propagation of load payload for double operands
Specifically, consider the size of the data type of the operand to compute
the number of registers written.
v2 (Sam):
- Fix line width (Jordan).
- Add an assert (Jordan).
- Use REG_SIZE in the calculation of regs_written (Curro)
v3 (Sam):
- Fix assert and calculation of regs_written (Curro).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Mon, 25 Apr 2016 22:40:05 +0000 (15:40 -0700)]
i965/fs: Fix propagation of copies with strided source.
This has likely been broken since we started propagating copies not
matching the offset of the instruction exactly
(
1728e74957a62b1b4b9fbb62a7de2c12b77c8a75). The copy source stride
needs to be taken into account to find out the offset at the origin
that corresponds to the offset at the destination of the copy which is
being read by the instruction. This has led to program miscompilation
on both my SIMD32 branch and Igalia's FP64 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 6 Apr 2016 08:27:14 +0000 (10:27 +0200)]
i965/fs: fix subreg_offset overflow in byte_offset()
This can happen if the register already has a non-zero subreg_offset
when byte_offset() is called.
v2 (Sam):
- Refactor byte_offset() (Jordan).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sun, 15 May 2016 06:54:48 +0000 (23:54 -0700)]
i965: Fix JIP to skip over sibling do...while loops.
We've apparently always been botching JIP for sequences such as:
do
cmp.f0.0 ...
(+f0.0) break
...
do
...
while
...
while
Because the "do" instruction doesn't actually exist, the inner "while"
is at the same depth as the "break". brw_find_next_block_end() thus
mistook the inner "while" as the end of the loop containing the "break",
and set the "break" to point to the wrong place.
Only "while" instructions that jump before our instruction are relevant.
We need to ignore the rest, as they're sibling control flow nodes (or
children, but this was already handled by the depth == 0 check).
See also commit
1ac1581f3889d5f7e6e231c05651f44fbd80f0b6.
This prevents channel masks from being screwed up, and fixes GPU
hangs(*) in dEQP-GLES31.functional.shaders.multisample_interpolation.
interpolate_at_sample.centroid_qualified.multisample_texture_16.
The test ended up executing code with no channels enabled, and that
code contained FIND_LIVE_CHANNEL, which returned 8 (out of range for
a SIMD8 program), which then was used in indirect GRF addressing,
which randomly got a boolean value (0xFFFFFFFF), interpreted it as
a sample ID, OR'd it into an indirect send message descriptor,
which corrupted the message length, sending a pixel interpolator
message with mlen 15, which is illegal. Whew :)
(*) Technically, the test doesn't GPU hang currently, but only
because another bug prevents it from issuing pixel interpolator
messages entirely...with that fixed, it hangs.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Sun, 15 May 2016 06:53:19 +0000 (23:53 -0700)]
i965: Make a "does this while jump before our instruction?" helper.
I need to use this in an additional place.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Wed, 27 Apr 2016 16:35:03 +0000 (09:35 -0700)]
i965: Send the minimal number of STATE_BASE_ADDRESS packets.
STATE_BASE_ADDRESS stalls the whole pipeline, and the documentation
cautions us to emit it as little as possible for better performance.
We recently put some hacks in BLORP to try and avoid emitting it
if it was already set correctly. However, this wasn't quite minimal:
if BLORP is the first operation (i.e. glClear()), then it would emit
it, and subsequent draw calls would emit it again.
This caused a small drop in performance in GPUTest Triangle when
switching from Meta to BLORP.
Unlike most packets, STATE_BASE_ADDRESS isn't influenced by GL state:
it needs to be emitted once per batch, before most other commands, or
whenever we change the program cache BO. It's also valid in both the
3D and compute pipelines, which makes it even more unique.
This patch removes it from the atom mechanism and instead directly
calls it as part of every draw, compute dispatch, or BLORP operation.
We introduce a new flag indicating that STATE_BASE_ADDRESS has already
been emitted this batch, and if so, skip doing it again. When we make
a new program cache BO, we simply reset the flag, so the next operation
will emit it again. When we flush/reset the batch, we reset the flag.
This guarantees that we'll emit STATE_BASE_ADDRESS only when we have to.
It's also less code than the old atom mechanism.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 27 Apr 2016 16:30:34 +0000 (09:30 -0700)]
i965: Combine Gen4-7 and Gen8+ state base address emitters.
We're about to start calling it directly, and this means the callers
won't have to think about generations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 27 Apr 2016 18:25:26 +0000 (11:25 -0700)]
i965: Move Gen4-5 programs to brw_upload_programs() too.
This way all the programs are in one place again, and it also should
make some future STATE_BASE_ADDRESS related changes possible.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 27 Apr 2016 18:26:08 +0000 (11:26 -0700)]
i965: Mark brw const in brw_state_dirty and callers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 29 Apr 2016 20:13:01 +0000 (13:13 -0700)]
glsl: Don't do constant propagation in opt_constant_folding.
opt_constant_folding is supposed to fold trees of constants into a
single constant. Surprisingly, it was also propagating constant values
from variables into expression trees - even when the result couldn't be
folded together. This is opt_constant_propagation's job.
The ir_dereference_variable::constant_expression_value() method returns
a clone of var->constant_value. So we would replace the dereference
with a constant, propagating it into the tree.
Skip over ir_dereference_variable to avoid this surprising behavior.
However, add code to explicitly continue doing it in the constant
propagation pass, as it's useful to do so.
shader-db statistics on Broadwell:
total instructions in shared programs:
8905349 ->
8905126 (-0.00%)
instructions in affected programs: 30100 -> 29877 (-0.74%)
helped: 93
HURT: 20
total cycles in shared programs:
71017030 ->
71015944 (-0.00%)
cycles in affected programs: 132456 -> 131370 (-0.82%)
helped: 54
HURT: 45
The only hurt programs are by a single instruction, while the helped
ones are helped by 1-4 instructions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 29 Apr 2016 20:19:33 +0000 (13:19 -0700)]
glsl: Avoid excess tree walking when folding ir_dereference_arrays.
If an ir_dereference_array has non-constant components, there's no
point in trying to evaluate its value (which involves walking down
the tree and possibly allocating memory for portions of the subtree
which are constant).
This also removes convoluted tree walking in opt_constant_folding(),
which tries to fold constants while walking up the tree. No need to
walk down, then up, then down again.
We did this for swizzles and expressions already, but I was lazy
back in the day and didn't do this for ir_dereference_array.
No change in shader-db.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 29 Apr 2016 21:40:26 +0000 (14:40 -0700)]
glsl: Consolidate duplicate copies of constant folding.
We could probably clean this up more (maybe make it a method), but at
least there's only one copy of this code now, and that's a start.
No change in shader-db.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 29 Apr 2016 21:04:17 +0000 (14:04 -0700)]
glsl: Remove bonus tree walking in opt_constant_folding().
It looks like this was missed when converting opt_constant_folding()
from a hierarchical visitor to an rvalue visitor in
6606fde3.
ir_rvalue_visitor already processes values on the way back up the tree,
so we will have already visited every child node. There's no point in
doing it again.
No change in shader-db.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 29 Apr 2016 19:53:03 +0000 (12:53 -0700)]
glsl: Make opt_constant_variable() bail in useless cases.
The pass ultimately skips over any entries with assignment_count != 1,
so there's no need to do further work once we've determined that there
are multiple assignments.
The constant value could be a large array (i.e. uvec4[327]), at which
point skipping the constant_expression_value() call (and the clone()
call within) can save us piles of memory.
No change in shader-db.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 13 May 2016 01:53:23 +0000 (18:53 -0700)]
i965: Flip interpolateAtOffset's y offset when necessary.
Fixes 4 dEQP-GLES31.functional.shaders.multisample_interpolation tests:
- interpolate_at_offset.no_qualifiers.default_framebuffer
- interpolate_at_offset.centroid_qualifier.default_framebuffer
- interpolate_at_offset.sample_qualifier.default_framebuffer
- interpolate_at_offset.array_element.default_framebuffer
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 13 May 2016 06:53:13 +0000 (23:53 -0700)]
nir: Add a nir->info.uses_interp_var_at_offset flag.
I've added this to nir_gather_info(), but also to glsl_to_nir() as a
temporary measure, since the i965 GL driver today doesn't use
nir_gather_info() yet.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sat, 14 May 2016 02:26:37 +0000 (19:26 -0700)]
glsl: Drop bad ASSERT_TRUE in gl_CullDistance link_varyings test.
I don't know what the intention was here, but this function returns
void. We can't assert anything about its return value.
Fixes "make check" failures.
v2: Also fix prototype for the function (caught by Jordan).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jan Vesely [Thu, 12 May 2016 20:24:58 +0000 (16:24 -0400)]
clover: Handle PIPE_SHADER_IR_NIR in switch
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Rob Clark [Sat, 14 May 2016 17:39:57 +0000 (13:39 -0400)]
freedreno/ir3: small standalone compiler cleanup
Don't hard-code the gpu-id anymore.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 14 May 2016 17:35:54 +0000 (13:35 -0400)]
nir: forward-declare 'struct gl_shader_program'
Drop extra #include which is otherwise unneeded (and makes this header
difficult to include from outside of src/mesa).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Mon, 9 May 2016 16:36:03 +0000 (12:36 -0400)]
nir: return progress from lower_idiv
With algebraic-opt support for lowering div to shift, the driver would
like to be able to run this pass *after* the main opt-loop, and then
conditionally re-run the opt-loop if this pass actually lowered some-
thing.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Sat, 14 May 2016 17:40:48 +0000 (13:40 -0400)]
freedreno/ir3: lower fdiv
Not sure how we didn't hit this already, but since we want fdiv
converted into mul + rcp, we should set this.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 21 Mar 2016 17:56:04 +0000 (13:56 -0400)]
freedreno/ir3: handle VARYING_SLOT_PNTC
In the glsl->tgsi path, this already gets translated to VAR8, which
matches up with rasterizer->sprite_coord_enable.
Signed-off-by: Rob Clark <robclark@freedesktop.org>