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Christoph Bumiller [Sun, 30 Jun 2013 13:23:15 +0000 (15:23 +0200)]
nvc0/ir: add f32 long immediate cannot saturate
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Tiziano Bacocco [Tue, 30 Jul 2013 20:04:49 +0000 (22:04 +0200)]
nvc0/ir: fix use after free in texture barrier insertion pass
Fixes crash with Amnesia: The Dark Descent.
Cc: "9.2 and 9.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sun, 1 Sep 2013 16:38:52 +0000 (12:38 -0400)]
nv30: find first unused texcoord rather than bailing if first is used
This fixes shaders produced by supertuxkart.
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Emil Velikov [Fri, 9 Aug 2013 18:51:02 +0000 (19:51 +0100)]
nouveau: initialise the nouveau_transfer maps
Cc: "9.2 and 9.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Chris Forbes [Tue, 27 Aug 2013 07:35:49 +0000 (19:35 +1200)]
i965/fs: Gen4: Zero out extra coordinates when using shadow compare
Fixes broken rendering if these MRFs contained anything other than zero.
NOTE: This is a candidate for stable branches.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sun, 25 Aug 2013 14:36:18 +0000 (07:36 -0700)]
i965/gs: Implement support for geometry shader samplers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sun, 25 Aug 2013 15:05:44 +0000 (08:05 -0700)]
i965/gs: add geometry shader support to brw_texture_surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Fri, 21 Jun 2013 16:24:16 +0000 (09:24 -0700)]
i965/gs: generalize brw_texture_surfaces in preparation for gs.
There is a slight functionality change. Previously we would compute a
common value for num_samplers for all stages, and populate that many
entries in each stage's surf_offset table regardless of how many
samplers each stage used. Now we only populate the number of entries
in the surf_offset table corresponding to the number of samplers
actually used by the stage.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sun, 25 Aug 2013 15:50:57 +0000 (08:50 -0700)]
i965: Modify signature to update_texture_surface functions.
Previously these functions would accept a pointer to the binding table
and an index indicating which entry in the binding table should be
updated. Now they merely take a pointer to the binding table entry to
be updated.
This will make it easier to generalize brw_texture_surfaces to support
geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Wed, 27 Mar 2013 20:15:45 +0000 (13:15 -0700)]
i965/vs: generalize gen6_vs_push_constants in preparation for GS.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Fri, 22 Mar 2013 19:34:19 +0000 (12:34 -0700)]
i965/gs: make the state atom for compiling Gen7 geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Use "unsigned" rather than "GLuint".
Paul Berry [Sun, 25 Aug 2013 13:47:34 +0000 (06:47 -0700)]
i965/gs: Implement support for geometry shader surfaces.
This patch implements pull constant upload, binding table upload, and
surface setup for geometry shaders, by re-using vertex shader code
that was generalized in previous patches.
Based on work by Eric Anholt <eric@anholt.net>.
v2: Update ditry bits for brw_gs_ubo_surfaces to account for commit
77d8fbc (mesa: add & use a new driver flag for UBO updates instead of
_NEW_BUFFER_OBJECT).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sun, 25 Aug 2013 08:23:08 +0000 (01:23 -0700)]
i965/vs: generalize brw_vs_binding_table in preparation for GS.
v2: Use GLbitfield instead of GLbitfield64 in
brw_vec4_upload_binding_table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sat, 24 Aug 2013 20:08:57 +0000 (13:08 -0700)]
i965: generalize brw_vs_pull_constants in preparation for GS.
v2: Use GLbitfield instead of GLbitfield64 in
brw_upload_vec4_pull_constants.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sun, 18 Aug 2013 15:23:51 +0000 (08:23 -0700)]
i965: Make sure constants re-sent after constant buffer reallocation.
The hardware requires that after constant buffers for a stage are
allocated using a 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS}
command, and prior to execution of a 3DPRIMITIVE, the corresponding
stage's constant buffers must be reprogrammed using a
3DSTATE_CONSTANT_{VS,HS,DS,GS,PS} command.
Previously we didn't need to worry about this, because we only
programmed 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS} once on
startup (or, previous to that, whenever BRW_NEW_CONTEXT was flagged).
But now that we reallocate the constant buffers whenever geometry
shaders are switched on and off, we need to make sure the constant
buffers are reprogrammed.
We do this by adding a new bit, BRW_NEW_PUSH_CONSTANT_ALLOCATION, to
brw->state.dirty.brw.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Wed, 27 Mar 2013 17:34:55 +0000 (10:34 -0700)]
i965/gs: Allocate push constant space for use by GS.
Previously, we would always use the same push constant allocation
regardless of what shader programs were being run: the available push
constant space was split into 2 equal size partitions, one for the
vertex shader, and one for the fragment shader.
Now that we are adding geometry shader support, we need to do
something smarter. This patch adjusts things so that when a geometry
shader is in use, we split the available push constant space into 3
nearly-equal size partitions instead of 2.
Since the push constant allocation is now affected by GL state, it can
no longer be set up by brw_upload_initial_gpu_state(); instead it must
be set up by a state atom.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Thu, 29 Aug 2013 17:17:31 +0000 (10:17 -0700)]
i965/gen7: Emit CS stall after 3DSTATE_PUSH_CONSTANT_ALLOC_PS.
This is required by the internal hardware docs and the PRM. Probably
the reason we were getting away with not doing it was because we only
emitted 3DSTATE_PUSH_CONSTANT_ALLOC_PS during startup. However that's
going to change with the introduction of geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Wed, 27 Mar 2013 16:49:17 +0000 (09:49 -0700)]
i965/gs: Allocate URB space for use by GS.
Previously, we gave all of the URB space (other than the small amount
that is used for push constants) to the vertex shader. However, when
a geometry shader is active, we need to divide it up between the
vertex and geometry shaders.
The size of the URB entries for the vertex and geometry shaders can
vary dramatically from one shader to the next. So it doesn't make
sense to simply split the available space in two. In particular:
- On Ivy Bridge GT1, this would not leave enough space for the worst
case geometry shader, which requires 64k of URB space.
- Due to hardware-imposed limits on the maximum number of URB entries,
sometimes a given shader stage will only be capable of using a small
amount of URB space. When this happens, it may make sense to
allocate substantially less than half of the available space to that
stage.
Our algorithm for dividing space between the two stages is to first
compute (a) the minimum amount of URB space that each stage needs in
order to function properly, and (b) the amount of additional URB space
that each stage "wants" (i.e. that it would be capable of making use
of). If the total amount of space available is not enough to satisfy
needs + wants, then each stage's "wants" amount is scaled back by the
same factor in order to fit.
When only a vertex shader is active, this algorithm produces
equivalent results to the old algorithm (if the vertex shader stage
can make use of all the available URB space, we assign all the space
to it; if it can't, we let it use as much as it can).
In the future, when we need to support tessellation control and
tessellation evaluation pipeline stages, it should be straightforward
to expand this algorithm to cover them.
v2: Use "unsigned" rather than "GLuint".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sat, 24 Aug 2013 16:14:38 +0000 (09:14 -0700)]
i965: Make CACHE_NEW_GS_PROG.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Fri, 22 Mar 2013 19:34:19 +0000 (12:34 -0700)]
i965/gs: Create brw_context::gs structure to track GS program state.
v2: Change name from "vec4_gs" to simply "gs".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sat, 24 Aug 2013 15:24:57 +0000 (08:24 -0700)]
i965: Move data from brw->vs into a base class if gs will also need it.
This paves the way for sharing the code that will set up the vertex
and geometry shader pipeline state.
v2: Rename the base class to brw_stage_state.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sun, 25 Aug 2013 16:28:08 +0000 (09:28 -0700)]
i965/gs: Update defines related to GS surface organization.
Defines that previously referred to VS now refer to VEC4, since they
will be shared by the user-programmable vertex shader and geometry
shader stages.
Defines that previously referred to the Gen6 geometry shader stage
(which is only used for transform feedback) are now renamed to
explicitly refer to Gen6, to avoid confusion with the Gen7
user-programmable geometry shader stage.
Based on work by Eric Anholt <eric@anholt.net>.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sat, 24 Aug 2013 05:26:19 +0000 (22:26 -0700)]
i965: Move vec4 register allocation data structures to brw->vec4.
This will avoid confusion when we add geometry shaders, since these
data structures will be shared by vertex and geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sat, 24 Aug 2013 04:49:50 +0000 (21:49 -0700)]
i965: Rename user-defined gs structs from vec4_gs to gs.
Now that the name "gs" is no longer used to refer to the legacy fixed
function geometry shaders, we can use it to refer to user-defined
geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sat, 24 Aug 2013 03:14:00 +0000 (20:14 -0700)]
i965: rename legacy gs structs and functions to ff_gs.
"ff" is for "fixed function". This frees up the name "gs" to refer to
user-defined geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Marek Olšák [Mon, 26 Aug 2013 15:19:39 +0000 (17:19 +0200)]
radeonsi: simplify and improve flushing
This mimics r600g. The R600_CONTEXT_xxx flags are added to rctx->b.flags
and si_emit_cache_flush emits the packets. That's it. The shared radeon code
tells us when the streamout cache should be flushed, so we have to check
the flags anyway.
There is a new atom "cache_flush", because caches must be flushed *after*
resource descriptors are changed in memory.
Functional changes:
* Write caches are flushed at the end of CS and read caches are flushed
at its beginning.
* Sampler view states are removed from si_state, they only held the flush
flags.
* Everytime a shader is changed, the I cache is flushed. Is this needed?
Due to a hw bug, this also flushes the K cache.
* The WRITE_DATA packet is changed to use TC, which fixes a rendering issue
in openarena. I'm not sure how TC interacts with CP DMA, but for now it
seems to work better than any other solution I tried. (BTW CIK allows us
to use TC for CP DMA.)
* Flush the K cache instead of the texture cache when updating resource
descriptors (due to a hw bug, this also flushes the I cache).
I think the K cache flush is correct here, but I'm not sure if the texture
cache should be flushed too (probably not considering we use TC
for WRITE_DATA, but we don't use TC for CP DMA).
* The number of resource contexts is decreased to 16. With all of these cache
changes, 4 doesn't work, but 8 works, which suggests I'm actually doing
the right thing here and the pipeline isn't drained during flushes.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Sat, 17 Aug 2013 17:19:30 +0000 (19:19 +0200)]
radeonsi: convert constant buffers to si_descriptors
There is a new "class" si_buffer_resources, which should be good enough for
implementing any kind of buffer bindings (constant buffers, vertex buffers,
streamout buffers, shader storage buffers, etc.)
I don't even keep a copy of pipe_constant_buffer - we don't need it.
The main motivation behind this is to have a well-tested infrastrusture
for setting up streamout buffers.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Tue, 13 Aug 2013 23:04:39 +0000 (01:04 +0200)]
radeonsi: use r600_common_context, r600_common_screen, r600_resource
Also r600_hw_context_priv.h and si_state_streamout.c are removed, because
they are no longer needed.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Tue, 13 Aug 2013 19:49:59 +0000 (21:49 +0200)]
r600g: move streamout state to drivers/radeon
This streamout state code will be used by radeonsi.
There are new structures r600_common_context and r600_common_screen.
What is inherited by what is shown here:
pipe_context -> r600_common_context -> r600_context
pipe_screen -> r600_common_screen -> r600_screen
The common structures reside in drivers/radeon. Currently they only contain
enough functionality to be able to handle streamout. Eventually I'd like
the whole pipe_screen implementation to be shared and some of the context
stuff too.
This is quite big, but most changes are because of the new structures and
the fact r600_write_value is replaced by radeon_emit.
Thanks to Tom Stellard for fixing the build for r600g/compute.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Sat, 17 Aug 2013 23:57:40 +0000 (01:57 +0200)]
radeonsi: cleanup initialization of SGPR shader parameters
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Sat, 17 Aug 2013 12:17:28 +0000 (14:17 +0200)]
r600g,radeonsi: remove unused variables
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Tue, 27 Aug 2013 19:57:41 +0000 (21:57 +0200)]
draw: fix segfaults with aaline and aapoint stages disabled
There are drivers not using these optional stages.
Broken by
a3ae5dc7dd5c2f8893f86a920247e690e550ebd4.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Kenneth Graunke [Wed, 28 Aug 2013 18:22:01 +0000 (11:22 -0700)]
i965/fs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
It is incorrect to assume that src[0] of a SEND-from-GRF opcode is the
GRF. For example, FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD uses src[1] for
the GRF.
To be safe, loop over all the source registers and mark any GRFs. We
probably won't ever have more than one, but it's simpler to just check
all three rather than attempting to bail early.
Not observed to fix anything yet, but likely to. Parallels the bug fix
in the previous commit, which actually does fix known failures.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Wed, 28 Aug 2013 18:16:27 +0000 (11:16 -0700)]
i965/vs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
It is incorrect to assume that src[0] of a SEND-from-GRF opcode is the GRF.
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7 uses an IMM as src[0], and stores the
GRF as src[1].
To be safe, loop over all the source registers and mark any GRFs. We
probably won't ever have more than one, but it's simpler to just check
all three rather than attempting to bail early.
Fixes assertion failures in Unigine Sanctuary since we started making
register allocation rely on split_virtual_grfs working. (The register
classes were actually sufficient, we were just interpreting an IMM as
a virtual GRF number.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68637
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: mesa-stable@lists.freedesktop.org
Niels Ole Salscheider [Wed, 28 Aug 2013 16:42:40 +0000 (18:42 +0200)]
radeonsi: Do not suspend timer queries
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Fri, 30 Aug 2013 15:24:59 +0000 (17:24 +0200)]
draw: fix PIPE_MAX_SAMPLER/PIPE_MAX_SHADER_SAMPLER_VIEWS issues
pstipple/aaline stages used PIPE_MAX_SAMPLER instead of
PIPE_MAX_SHADER_SAMPLER_VIEWS when dealing with sampler views.
Now these stages can't actually handle sampler_unit != texture_unit anyway
(they cannot work with d3d10 shaders at all due to using tex not sample
opcodes as "mixed mode" shaders are impossible) but this leads to crashes if
a driver just installs these stages and then more than PIPE_MAX_SAMPLER views
are set even if the stages aren't even used.
Reviewed-by: Zack Rusin <zackr@vmware.com>
Roland Scheidegger [Fri, 30 Aug 2013 14:40:21 +0000 (16:40 +0200)]
gallivm: handle unbound textures in texture sampling / texture queries
Turns out we don't need to do much extra work for detecting this case,
since we are guaranteed to get a empty static texture state in this case,
hence just rely on format being 0 and return all zero then.
Previously needed dummy textures (would just have crashed on format being 0
otherwise) which cannot return the correct result for size queries and when
sampling textures with wrap modes using border.
As a bonus should hugely increase performance when sampling unbound textures -
too bad it isn't a useful feature :-).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Roland Scheidegger [Fri, 30 Aug 2013 14:35:40 +0000 (16:35 +0200)]
softpipe: handle NULL sampler views for texture sampling / queries
Instead of crashing just return all zero.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Roland Scheidegger [Fri, 30 Aug 2013 14:34:26 +0000 (16:34 +0200)]
softpipe: check if so_target is NULL before accessing it
No idea if this is working right but copied straight from llvmpipe.
(Not only does this check the so_target but also use buffer->data instead
of buffer for the mapping.)
Just trying to get rid of a segfault testing something else...
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Roland Scheidegger [Thu, 29 Aug 2013 18:52:35 +0000 (20:52 +0200)]
gallivm: (trivial) don't pass sampler_unit variable down to filtering funcs
The only reason this was needed was because the fetch texel function had to
get the (dynamic) border color, but this is now done much earlier.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 29 Aug 2013 18:52:18 +0000 (20:52 +0200)]
gallivm: don't use AoS path if min/mag filter are different with multiple lods
Instead of enhancing the AoS path so it can deal with it, just use SoA. Fixing
AoS path wouldn't be all that difficult (use all the same logic as SoA) but
considered not worth it for now.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Thu, 29 Aug 2013 15:09:05 +0000 (08:09 -0700)]
mesa: Don't choose S3TC for generic compression if we can't compress.
If the app is asking us to do GL_COMPRESSED_RGBA, then the app obviously
doesn't have pre-compressed data to hand us. So don't choose a storage
format that we won't actually be able to compress and store.
Fixes black screen in warzone2100 when libtxc_dxtn is not present. Also
66 piglit tests.
NOTE: This is a candidate for the 9.2 branch.
Reported-by: Paul Wise <pabs@debian.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Thu, 29 Aug 2013 15:07:09 +0000 (08:07 -0700)]
mesa: Rip out more extension checking from texformat.c.
You should only be flagging the formats as supported if you support them
anyway.
NOTE: This is a candidate for the 9.2 branch. (required for next commit)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 28 Aug 2013 18:53:09 +0000 (11:53 -0700)]
i965: Switch gen4-6 to using the sampler's base level for GL BASE_LEVEL.
Thanks to Ken for trawling through my neglected public branches and
finding the bug in this change (inside a megacommit) that made me abandon
this work.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 28 Aug 2013 19:06:31 +0000 (12:06 -0700)]
i965/gen7: Use the base_level field of the sampler to handle GL's BASE_LEVEL.
This avoids the need to get the inter- and intra-tile offset and adjust
our miptree info based on them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 18 Jun 2013 21:54:18 +0000 (14:54 -0700)]
i965: Add missing state reset at the end of blorp.
These are things that happen to be occurring because of the batch flush at
the start of the blorp op (which exists to prevent batch space or aperture
space overflow), but the intention was for this sequence of state resets at
the end of blorp to be everything necessary for the next draw call.
Found when debugging the next commit, by comparing brw_new_batch() and
intel_batchbuffer_reset() to brw_blorp_exec().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 27 Aug 2013 19:33:48 +0000 (12:33 -0700)]
i965: Drop extra flush when calling intel_miptree_map_raw().
The code that got replaced with map_raw didn't do the flush, but now
map_raw() is responsible for it and we don't have to worry about it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 27 Aug 2013 19:25:58 +0000 (12:25 -0700)]
i965: Make a slight distinction in perf debug for BOs versus miptrees.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 28 Dec 2012 20:25:14 +0000 (12:25 -0800)]
intel: Reuse intel_glFlush().
v2 (Kenneth Graunke): Rebase on latest master.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 28 Dec 2012 19:44:08 +0000 (11:44 -0800)]
intel: Add support for the new flush_with_flags extension.
This gives us more information about why we're flushing that we can
use for handling our throttling.
v2 (Kenneth Graunke): Rebase on latest master, add missing
FLUSH_VERTICES and FLUSH_CURRENT, which fixes a regression in Glean's
polygonOffset test.
v3 (anholt): Drop FLUSH_CURRENT -- FLUSH_VERTICES is what we need, which
is "get any queued prims out of VBO and into the driver", not "update
ctx->Current so we can read it with the CPU." Also drop batch->used
check, which intel_batchbuffer_flush() does anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 28 Dec 2012 20:19:42 +0000 (12:19 -0800)]
intel: Add a batch flush between front-buffer downsample and X protocol.
This was already happening because blorp happens to flush at the end of
every call, but we have been talking about removing that at some point,
and this would surely get overlooked.
v2 (Kenneth Graunke): Rebase on latest master. Note that we did remove
the other flush, and this change actually did get overlooked!
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 27 Aug 2013 19:30:39 +0000 (12:30 -0700)]
i965: Directly call intel_batchbuffer_flush() after i915 split.
intel_flush() now did nothing except call through (and
intel_batchbuffer_flush() does the no-op check, too!)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 30 Aug 2013 17:45:00 +0000 (10:45 -0700)]
i965/vs: Fix regression on pre-gen6 with no VS uniforms in use.
df06745c5adb524e15d157f976c08f1718f08efa made it so that we didn't
allocate extra uniform space for unused clip planes, which also
incidentally made us not allocate any space at all, which we were relying
on for this no-uniforms case. Instead of putting the knowledge of this
special HW exception into the thing that normally preallocates prog_data
for us, just allocate it here.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68766
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Vadim Girlin [Fri, 23 Aug 2013 20:54:54 +0000 (00:54 +0400)]
r600g: enable SB backend by default
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Vadim Girlin [Sun, 25 Aug 2013 14:52:17 +0000 (18:52 +0400)]
r600g: fix color exports when we have no CBs
We need to export at least one color if the shader writes it,
even when nr_cbufs==0.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vinson Lee [Sat, 13 Jul 2013 06:56:06 +0000 (23:56 -0700)]
nvc0/ir: Initialize NVC0LegalizePostRA member variables.
Fixes "Uninitialized pointer field" defects reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Roland Scheidegger [Thu, 29 Aug 2013 23:30:29 +0000 (01:30 +0200)]
gallivm: support per-pixel min/mag filter in SoA path
Since we can have per-pixel lod we should also honor the filter per-pixel
(in fact we didn't honor it per quad neither in the multiple quad case).
Do this by running the linear path and simply beating the weights into shape
(the sample with the higher weight is the one which should have been chosen
with nearest filtering hence adjust filter weight to 1.0/0.0 based on that).
If all pixels use nearest filter (either min and mag) then still run just a
nearest filter as this is way cheaper (probably around 4 times faster for 2d,
more for 3d case) and it should be relatively rare that pixels really need
different filtering. OTOH if all pixels would require linear don't do anything
special since the linear path with filter adjustments shouldn't really be all
that much more expensive than ordinary linear, and we think it's rare that
min/mag filters are configured differently so there doesn't seem much value
in trying to optimize this further.
This does not yet fix the AoS path (though currently AoS is only used for
single quads hence it could be considered less broken, just never honoring
per-pixel filter decision but doing it per quad).
v2: simplify code a bit (unify min linear and min nearest cases)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 29 Aug 2013 01:58:18 +0000 (03:58 +0200)]
gallivm: don't calculate square root of rho if we use accurate rho method
While a sqrt here and there shouldn't hurt much (depending on the cpu) it is
possible to completely omit it since rho is only used for calculating lod and
there log2(x) == 0.5*log2(x^2). Depending on the exact path taken for
calculating lod this means we get a simple mul instead of sqrt (in case of
nearest mip filter in fact we don't need to replace the sqrt with something
else at all), only in some not very useful path this doesn't work (combined
brilinear calculation of int level and fractional lod, accurate rho calc but
brilinear filtering seems odd).
Apart from being faster as an added bonus this should increase our crappy
fractional accuracy of lod, since fast_log2 is only good for ~3bits and this
should increase accuracy by one bit (though not used if dimension is just one
as we'd need an extra mul there as we never had the squared rho in the first
place).
v2: use separate ilog2_sqrt function if we have squared rho.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 28 Aug 2013 14:26:43 +0000 (16:26 +0200)]
gallivm: refactor num_lods handling
This is just preparation for per-pixel (or per-quad in case of multiple quads)
min/mag filter since some assumptions about number of miplevels being equal
to number of lods no longer holds true.
This change does not change behavior yet (though theoretically when forcing
per-element path it might be slower with different min/mag filter since the
code will respect this setting even when there's no mip maps now in this case,
so some lod calcs will be done per-element just ultimately still the same
filter used for all pixels).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Vinson Lee [Thu, 29 Aug 2013 20:13:02 +0000 (13:13 -0700)]
radeonsi: Early return if no depth or stencil on release builds.
Fixes "Missing break in switch" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Thu, 29 Aug 2013 21:26:16 +0000 (17:26 -0400)]
freedreno: pipe loader for either kgsl or msm
The downstream android kernel driver is "kgsl", the upstream drm/kms
driver is called "msm". Since libdrm_freedreno handles the differences
between the two, we need to load the same thing for either device.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 29 Aug 2013 21:24:33 +0000 (17:24 -0400)]
freedreno: updates for msm drm/kms driver
There where some small API tweaks in libdrm_freedreno to enable support
for msm drm/kms driver.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 27 Aug 2013 23:24:53 +0000 (19:24 -0400)]
freedreno/a3xx/compiler: handle sync flags better
We need to set the flag on all the .xyzw components that are written by
the instruction, not just on .x. Otherwise a later use of rN.y (for
example) will not trigger the appropriate sync bit to be set.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 24 Aug 2013 21:30:50 +0000 (17:30 -0400)]
freedreno/a3xx/compiler: better const handling
Seems like most/all instructions have some restrictions about const src
registers. In seems like the 2 src (cat2) instructions can take at most
one const, and the 3 src (cat3) instructions can take at most one const
in the first 2 arguments. And so on. Handle this properly now.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Anuj Phogat [Tue, 27 Aug 2013 01:21:03 +0000 (18:21 -0700)]
glsl: Allow precision qualifiers for sampler types
GLSL 1.30 doesn't allow precision qualifiers on sampler types,
but in GLSL ES, sampler types are also allowed. This seems like
an oversight (since the intention of including these in GLSL 1.30
is to allow compatibility with ES shaders).
Currently, Mesa allows "default" precision qualifiers to be set for
sampler types in GLSL (commit
d5948f2). This patch makes it follow
GLSL ES rules and also allow declaring sampler variables with a
precision qualifier in GLSL 1.30 (and later). e.g.
uniform lowp sampler2D sampler;
This fixes a shader compilation error in Khronos OpenGL conformance
test "depth_texture_mipmap".
V2: Update comments.
Signed-off-by: Ian Romanick <idr@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <idr@lists.freedesktop.org>
Cc: <mesa-stable@lists.freedesktop.org>
Matt Turner [Sun, 4 Aug 2013 21:01:30 +0000 (14:01 -0700)]
glsl: Add heuristics to print floating-point numbers better.
v2: Fix *.expected files to match.
Reviewed-by: Paul Berry <strereotype441@gmail.com>
Jonathan Gray [Thu, 18 Jul 2013 13:05:13 +0000 (23:05 +1000)]
radeonsi: Make sure libdrm_radeon headers are picked up from the right place
And remove libdrm/ from a winsys include statement.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Brian Paul [Wed, 28 Aug 2013 23:13:11 +0000 (17:13 -0600)]
draw: fix point/line/triangle determination in draw_need_pipeline()
The previous point/line/triangle() functions didn't handle GS primitives.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Christian König [Wed, 28 Aug 2013 16:55:56 +0000 (18:55 +0200)]
radeon/uvd: fix MPEG2/4 ref frame index limit
Otherwise the first few frames have an incorrect reference index.
Signed-off-by: Christian König <christian.koenig@amd.com>
Vinson Lee [Sat, 17 Aug 2013 22:23:15 +0000 (15:23 -0700)]
nouveau: Copy m4x4 and m8x8 separately.
Silences Coverity "Out-of-bounds access" defect.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Kenneth Graunke [Mon, 26 Aug 2013 04:38:29 +0000 (21:38 -0700)]
i965: Allocate just enough space for user clip planes in uniform arrays.
Previously, we allocated space in brw_vs_prog_data's params and
pull_params arrays for MAX_CLIP_PLANES vec4s---even when it wasn't
necessary.
On a 64-bit architecture, this used 0.5 kB of space (8 clip planes *
4 floats per plane * 8 bytes per float pointer * 2 arrays of pointers =
512 bytes). Since this cost was per-vertex shader, it added up.
Conveniently, we already store the number of clip plane constants in the
program key. By using that, we can allocate the exact amount of space
needed. For the common case where user clipping is disabled, this means
0 bytes.
While we're here, mention exactly what code requires this extra space,
since it wasn't obvious.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Chad Versace [Tue, 27 Aug 2013 22:08:00 +0000 (15:08 -0700)]
i965: Silence unused variable warning in release build
Use `(void) success;` to silence this warning:
i965/brw_vs.c:481:12:
warning: unused variable 'success' [-Wunused-variable]
bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Brian Paul [Wed, 28 Aug 2013 00:57:35 +0000 (18:57 -0600)]
docs: minor fixes for 9.2 release notes
Fix incorrect </li> tag, fix language.
(cherry picked from commit
2377205bcb3bb0b5db48772224f5f80f2cf9abf7)
Ian Romanick [Tue, 27 Aug 2013 23:38:09 +0000 (16:38 -0700)]
docs: Add news item for 9.2 release
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Tue, 27 Aug 2013 23:37:13 +0000 (16:37 -0700)]
docs: Import 9.2 release notes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Fabian Bieler [Sat, 25 May 2013 11:33:42 +0000 (13:33 +0200)]
mesa/main: Check for 0 size draws after validation.
When validating draw parameters move check for 0 draw count last
(drawing with count 0 is not an error), so that other parameters (e.g.: the
primitive type) are validated and the correct errors (if applicable) are
generated.
>From the OpenGL 3.3 spec page 33 (page 48 of the PDF):
"[Regarding DrawArraysOneInstance, in terms of which other draw operations
are defined:]
If count is negative, an INVALID_VALUE error is generated."
This patch also changes the bahavior of MultiDrawElements to perform the draw
operation if some primitive's index counts are zero.
Signed-off-by: Fabian Bieler <fabianbieler@fastmail.fm>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Wed, 7 Aug 2013 04:45:30 +0000 (21:45 -0700)]
glsl: Add built-ins from ARB_shader_bit_encoding to ARB_gpu_shader5.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Fri, 2 Aug 2013 17:28:16 +0000 (10:28 -0700)]
i965/vs: Add support for translating ir_triop_fma into MAD.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 24 Apr 2013 00:32:26 +0000 (17:32 -0700)]
i965/fs: Add support for translating ir_triop_fma into MAD.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 27 Aug 2013 05:01:17 +0000 (22:01 -0700)]
i965/fs: Assert that ir_expressions are usable by 3-src instructions.
MAD will be generated directly from ir_triop_fma, so this assertion
checks that all ir_expressions are usable.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Wed, 24 Apr 2013 00:19:06 +0000 (17:19 -0700)]
glsl: Add support for new fma built-in in ARB_gpu_shader5.
v2: Add constant folding support.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 24 Apr 2013 00:10:20 +0000 (17:10 -0700)]
glsl: Add new fma built-in IR and prototype from ARB_gpu_shader5.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Sun, 11 Aug 2013 00:15:12 +0000 (02:15 +0200)]
r300g: enable MSAA on r300-r400, be careful about using color compression
MSAA was tested by one user on RS690 and it works for him with color
compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM.
Since we don't have hardware documentation about which chipsets actually have
CMASK RAM, I had to take a guess based on the presence of HiZ.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fabio Pedretti [Mon, 12 Aug 2013 11:48:04 +0000 (13:48 +0200)]
configure.ac: Bump Wayland requirement to 1.2.0
Since
8d29b52 wayland 1.2.0 is required.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Roland Scheidegger [Fri, 23 Aug 2013 21:08:43 +0000 (23:08 +0200)]
draw: clean up setting stream out information a bit
In particular noone is interested in the vertex count, so drop that,
and also drop the duplicated num_primitives_generated /
so.primitives_storage_needed variables in drivers. I am unable for now to figure
out if primitives_storage_needed in SO stats (used for d3d10) should
increase if SO is disabled, though the equivalent num_primitives_generated
used for OpenGL definitely should increase. In any case we were only counting
when SO is active both in softpipe and llvmpipe anyway so don't pretend there's
an independent num_primitives_generated counter which would count always.
(This means the PIPE_QUERY_PRIMITIVES_GENERATED count will still be wrong just
as before, should eventually fix this by doing either separate counting for this
query or adjust the code so it always counts this even if SO is inactive depending
on what's correct for d3d10.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Fri, 23 Aug 2013 19:25:01 +0000 (21:25 +0200)]
llvmpipe: support nested/overlapping queries for all query types
There's just no way resetting the counters is working with nested/overlapping
queries.
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Fri, 23 Aug 2013 19:23:07 +0000 (21:23 +0200)]
softpipe: support nested/overlapping queries for all query types
There's just no way resetting the counters is working with nested/overlapping
queries.
Reviewed-by: Brian Paul <brianp@vmware.com>
Matt Turner [Mon, 26 Aug 2013 21:14:03 +0000 (14:14 -0700)]
glsl: Disallow uniform block layout qualifiers on non-uniform block vars.
Cc: 9.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68460
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kristian Lehmann [Mon, 26 Aug 2013 19:19:50 +0000 (21:19 +0200)]
Fixed and/or order mistake, resulting in compiling llvmpipe without llvm installed
Cc: 9.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68544
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 22 Aug 2013 02:37:30 +0000 (19:37 -0700)]
i915: Optimize SEQ and SNE when two operands are uniforms
SEQ and SNE are not native i915 instructions, so they each generate at
least 3 instructions. If both operands are uniforms or constants, we
get 5 instructions like:
U[1] = MOV CONST[1]
U[0].xyz = SGE CONST[0].xxxx, U[1]
U[1] = MOV CONST[1].-x-y-z-w
R[0].xyz = SGE CONST[0].-x-x-x-x, U[1]
R[0].xyz = MUL R[0], U[0]
This code is stupid. Instead of having the individual calls to
i915_emit_arith generate the moves to utemps, do it in the caller. This
results in code like:
U[1] = MOV CONST[1]
U[0].xyz = SGE CONST[0].xxxx, U[1]
R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w
R[0].xyz = MUL R[0], U[0]
This allows fs-temp-array-mat2-index-col-wr and
fs-temp-array-mat2-index-row-wr to fit in hardware limits (instead of
falling back to software rasterization).
NOTE: Without pending patches to the piglit tests, these tests will now
fail. This is an unrelated, pre-existing issue.
v2: Copy most of the body of the commit message into comments in the
code. Suggested by Eric.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tom Stellard [Tue, 27 Aug 2013 00:52:47 +0000 (17:52 -0700)]
clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
CC: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Niels Ole Salscheider [Fri, 9 Aug 2013 09:59:26 +0000 (11:59 +0200)]
st/clover: Add event to deps even if it has been triggered
The command is submitted once the event has been triggered, but it might not
have completed yet. Therefore, we have to add it to deps in order to wait on it.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Niels Ole Salscheider [Fri, 9 Aug 2013 09:59:25 +0000 (11:59 +0200)]
st/clover: Profiling support
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Dave Airlie [Tue, 13 Aug 2013 00:13:12 +0000 (10:13 +1000)]
tgsi_build: fix order of arguments for ind register build
This was broken when arrayid was added.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 12 Aug 2013 07:34:27 +0000 (17:34 +1000)]
tgsi: finish declaration parsing for arrays.
I previously fixed this partly in
9e8400f4c95bde1f955c7977066583b507159a10,
however I didn't go far enough in testing it, now when I parse a TGSI shader
with arrays in it my iterator can see the ArrayID set to the proper value.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Mon, 26 Aug 2013 21:49:16 +0000 (15:49 -0600)]
svga: replace 0 with PIPE_OK in a few places
Brian Paul [Fri, 23 Aug 2013 21:33:14 +0000 (15:33 -0600)]
swrast: init i0, i1 values to silence warnings
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Brian Paul [Fri, 23 Aug 2013 21:32:28 +0000 (15:32 -0600)]
mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT()
to silence gcc 4.8.1 warnings. And improve the ASSERT(0) call.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Brian Paul [Fri, 23 Aug 2013 21:12:07 +0000 (15:12 -0600)]
glsl: init limit=0 to silence uninitialized var warning
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Kenneth Graunke [Wed, 21 Aug 2013 23:27:11 +0000 (16:27 -0700)]
i965/vs: Allocate register set once at context creation.
Now that we use a fixed set of register classes, we can set up the
register set and conflict graphs once, at context creation, rather than
on every VS compile. This is obviously less expensive, and also what
we already do in the FS backend.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>