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Diana Picus [Fri, 14 Dec 2018 12:37:24 +0000 (12:37 +0000)]
[ARM GlobalISel] Minor refactoring. NFCI
Refactor the ARMInstructionSelector to cache some opcodes in the
constructor instead of checking all the time if we're in ARM or Thumb
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349143
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Diana Picus [Fri, 14 Dec 2018 11:58:14 +0000 (11:58 +0000)]
[ARM GlobalISel] Allow simple binary ops in Thumb2
Mark G_ADD, G_SUB, G_MUL, G_AND, G_OR and G_XOR as legal for both ARM
and Thumb2.
Extract the legalizer tests for these opcodes into another file.
Add tests for the instruction selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349142
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Simon Tatham [Fri, 14 Dec 2018 11:39:55 +0000 (11:39 +0000)]
[TableGen:AsmWriter] Cope with consecutive tied operands.
When you define an instruction alias as a subclass of InstAlias, you
specify all the MC operands for the instruction it expands to, except
for operands that are tied to a previous one, which you leave out in
the expectation that the Tablegen output code will fill them in
automatically.
But the code in Tablegen's AsmWriter backend that skips over a tied
operand was doing it using 'if' instead of 'while', because it wasn't
expecting to find two tied operands in sequence.
So if an instruction updates a pair of registers in place, so that its
MC representation has two input operands tied to the output ones (for
example, Arm's UMLAL instruction), then any alias which wants to
expand to a special case of that instruction is likely to fail to
match, because the indices of subsequent operands will be off by one
in the generated printAliasInstr function.
This patch re-indents some existing code, so it's clearest when
viewed as a diff with whitespace changes ignored.
Reviewers: fhahn, rengolin, sdesmalen, atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund
Reviewed By: rengolin
Subscribers: javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D53816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349141
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Simon Pilgrim [Fri, 14 Dec 2018 09:25:08 +0000 (09:25 +0000)]
Revert rL349136: [llvm-exegesis] Optimize ToProcess in dbScan
Summary:
Use `vector<char> Added + vector<size_t> ToProcess` to replace `SetVector ToProcess`
We also check `Added[P]` to enqueueing a point more than once, which
also saves us a `ClusterIdForPoint_[Q].isUndef()` check.
Reviewers: courbet, RKSimon, gchatelet, john.brawn, lebedev.ri
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D54442
........
Patch wasn't approved and breaks buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349139
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Craig Topper [Fri, 14 Dec 2018 08:28:24 +0000 (08:28 +0000)]
[DAGCombiner][X86] Prevent visitSIGN_EXTEND from returning N when (sext (setcc)) already has the target desired type for the setcc
Summary:
If the setcc already has the target desired type we can reach the getSetCC/getSExtOrTrunc after the MatchingVecType check with the exact same types as the nodes we started with. This causes those causes VsetCC to be CSEd to N0 and the getSExtOrTrunc will CSE to N. When we return N, the caller will think that meant we called CombineTo and did our own worklist management. But that's not what happened. This prevents target hooks from being called for the node.
To fix this, I've now returned SDValue if the setcc is already the desired type. But to avoid some regressions in X86 I've had to disable one of the target combines that wasn't being reached before in the case of a (sext (setcc)). If we get vector widening legalization enabled that entire function will be deleted anyway so hopefully this is only for the short term.
Reviewers: RKSimon, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D55459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349137
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Fangrui Song [Fri, 14 Dec 2018 08:27:35 +0000 (08:27 +0000)]
[llvm-exegesis] Optimize ToProcess in dbScan
Summary:
Use `vector<char> Added + vector<size_t> ToProcess` to replace `SetVector ToProcess`
We also check `Added[P]` to enqueueing a point more than once, which
also saves us a `ClusterIdForPoint_[Q].isUndef()` check.
Reviewers: courbet, RKSimon, gchatelet, john.brawn, lebedev.ri
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D54442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349136
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Fangrui Song [Fri, 14 Dec 2018 08:21:08 +0000 (08:21 +0000)]
[ThinLTO] Fix test added in rL349076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349135
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Fangrui Song [Fri, 14 Dec 2018 07:46:58 +0000 (07:46 +0000)]
[Object] Rename getRelrRelocationType to getRelativeRelocationType
Summary:
The two utility functions were added in D47919 to support SHT_RELR.
However, these are just relative relocations types and are't
necessarily be named Relr.
Reviewers: phosek, dberris
Reviewed By: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D55691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349133
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Petr Hosek [Fri, 14 Dec 2018 06:06:19 +0000 (06:06 +0000)]
[llvm-xray] Use correct variable name
This fixes the compiler error introduced in r349129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349130
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Petr Hosek [Fri, 14 Dec 2018 05:56:20 +0000 (05:56 +0000)]
[llvm-xray] Store offset pointers in temporaries
DataExtractor::getU64 modifies the OffsetPtr which also pass to
RelocateOrElse which breaks on Windows. This addresses the issue
introduced in r349120.
Differential Revision: https://reviews.llvm.org/D55689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349129
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Nico Weber [Fri, 14 Dec 2018 03:20:46 +0000 (03:20 +0000)]
[gn build] Merge r348963 and r349076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349124
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Petr Hosek [Fri, 14 Dec 2018 01:37:56 +0000 (01:37 +0000)]
[llvm-xray] Support for PIE
When the instrumented binary is linked as PIE, we need to apply the
relative relocations to sleds. This is handled by the dynamic linker
at runtime, but when processing the file we have to do it ourselves.
Differential Revision: https://reviews.llvm.org/D55542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349120
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Alex Lorenz [Fri, 14 Dec 2018 01:14:10 +0000 (01:14 +0000)]
[macho] save the SDK version stored in module metadata into the version min and
build version load commands in the object file
This commit introduces a new metadata node called "SDK Version". It will be set
by the frontend to mark the platform SDK (macOS/iOS/etc) version which was used
during that particular compilation.
This node is used when machine code is emitted, by either saving the SDK version
into the appropriate macho load command (version min/build version), or by
emitting the assembly for these load commands with the SDK version specified as
well.
The assembly for both load commands is extended by allowing it to contain the
sdk_version X, Y [, Z] trailing directive to represent the SDK version
respectively.
rdar://
45774000
Differential Revision: https://reviews.llvm.org/D55612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349119
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Reid Kleckner [Fri, 14 Dec 2018 00:17:12 +0000 (00:17 +0000)]
Silence CMP0048 warning in the benchmark utility library
I'm testing this in LLVM before sending it upstream.
Part of PR38874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349097
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Nico Weber [Fri, 14 Dec 2018 00:16:33 +0000 (00:16 +0000)]
[gn build] Add infrastructure to create symlinks and use it to create lld's symlinks
This is slightly involved, see the comments in the code.
The GN build now builds a functional lld!
Differential Revision: https://reviews.llvm.org/D55606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349096
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Sanjay Patel [Fri, 14 Dec 2018 00:09:08 +0000 (00:09 +0000)]
[DAGCombiner] clean up visitEXTRACT_VECTOR_ELT
This isn't quite NFC, but I don't know how to expose
any outward diffs from these changes. Mostly, this
was confusing because it used 'VT' to refer to the
operand type rather the usual type of the input node.
There's also a large block at the end that is dedicated
solely to matching loads, but that wasn't obvious. This
could probably be split up into separate functions to
make it easier to see.
It's still not clear to me when we make certain transforms
because the legality and constant conditions are
intertwined in a way that might be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349095
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Craig Topper [Thu, 13 Dec 2018 23:55:30 +0000 (23:55 +0000)]
[X86] Demote EmitTest to a helper function of EmitCmp. Route all callers except EmitCmp through EmitCmp.
This requires the two callers to manifest a 0 to make EmitCmp call EmitTest.
I'm looking into changing how we combine TEST and flag setting instructions to not be part of lowering. And instead be part of DAG combine or isel. Which will mean EmitTest will probably become gutted and maybe disappear entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349094
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Evgeniy Stepanov [Thu, 13 Dec 2018 23:47:50 +0000 (23:47 +0000)]
Revert "[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)"
Breaks sanitizer-android buildbot.
This reverts commit
af8443a984c3b491c9ca2996b8d126ea31e5ecbe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349092
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Evandro Menezes [Thu, 13 Dec 2018 23:19:46 +0000 (23:19 +0000)]
[AArch64] Fix Exynos predicates (NFC)
Fix the logic in the definition of the `ExynosShiftExPred` as a more
specific version of `ExynosShiftPred`. But, since `ExynosShiftExPred` is
not used yet, this change has NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349091
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Wei Mi [Thu, 13 Dec 2018 21:51:42 +0000 (21:51 +0000)]
[SampleFDO] handle ProfileSampleAccurate when initializing function entry count
ProfileSampleAccurate is used to indicate the profile has exact match to the
code to be optimized.
Previously ProfileSampleAccurate is handled in ProfileSummaryInfo::isColdCallSite
and ProfileSummaryInfo::isColdBlock. A better solution is to initialize function
entry count to 0 when ProfileSampleAccurate is true, so we don't have to handle
ProfileSampleAccurate in multiple places.
Differential Revision: https://reviews.llvm.org/D55660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349088
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Aakanksha Patil [Thu, 13 Dec 2018 21:23:12 +0000 (21:23 +0000)]
Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute
This patch breaks RADV (and probably RadeonSI as well)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349084
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Matt Arsenault [Thu, 13 Dec 2018 20:34:15 +0000 (20:34 +0000)]
AMDGPU/GlobalISel: Legalize/regbankselect block_addr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349081
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Nikita Popov [Thu, 13 Dec 2018 20:04:27 +0000 (20:04 +0000)]
Reapply "[MemCpyOpt] memset->memcpy forwarding with undef tail"
Currently memcpyopt optimizes cases like
memset(a, byte, N);
memcpy(b, a, M);
to
memset(a, byte, N);
memset(b, byte, M);
if M <= N. Often this allows further simplifications down the line,
which drop the first memset entirely.
This patch extends this optimization for the case where M > N, but we
know that the bytes a[N..M] are undef due to alloca/lifetime.start.
This situation arises relatively often for Rust code, because Rust does
not initialize trailing structure padding and loves to insert redundant
memcpys. This also fixes https://bugs.llvm.org/show_bug.cgi?id=39844.
The previous version of this patch did not perform dependency checking
properly: While the dependency is checked at the position of the memset,
the used size must be that of the memcpy. Previously the size of the
memset was used, which missed modification in the region
MemSetSize..CopySize, resulting in miscompiles. The added tests cover
variations of this issue.
Differential Revision: https://reviews.llvm.org/D55120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349078
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Easwaran Raman [Thu, 13 Dec 2018 19:54:27 +0000 (19:54 +0000)]
[ThinLTO] Compute synthetic function entry count
Summary:
This patch computes the synthetic function entry count on the whole
program callgraph (based on module summary) and writes the entry counts
to the summary. After function importing, this count gets attached to
the IR as metadata. Since it adds a new field to the summary, this bumps
up the version.
Reviewers: tejohnson
Subscribers: mehdi_amini, inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D43521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349076
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Mircea Trofin [Thu, 13 Dec 2018 19:40:59 +0000 (19:40 +0000)]
[llvm] Address base discriminator overflow in X86DiscriminateMemOps
Summary:
Macros are expanded on a single line. In case of large expansions,
with sufficiently many instructions with memory operands (and when
-fdebug-info-for-profiling is requested), we may be unable to generate
new base discriminator values - new values overflow (base
discriminators may not be larger than 2^12).
This CL warns instead of asserting in such a case. A subsequent CL
will add APIs to check for overflow before creating new debug info.
See https://bugs.llvm.org/show_bug.cgi?id=39890
Reviewers: davidxl, wmi, gbedwell
Reviewed By: davidxl
Subscribers: aprantl, llvm-commits
Differential Revision: https://reviews.llvm.org/D55643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349075
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Jordan Rupprecht [Thu, 13 Dec 2018 19:40:12 +0000 (19:40 +0000)]
[llvm-size][libobject] Add explicit "inTextSegment" methods similar to "isText" section methods to calculate size correctly.
Summary:
llvm-size uses "isText()" etc. which seem to indicate whether the section contains code-like things, not whether or not it will actually go in the text segment when in a fully linked executable.
The unit test added (elf-sizes.test) shows some types of sections that cause discrepencies versus the GNU size tool. llvm-size is not correctly reporting sizes of things mapping to text/data segments, at least for ELF files.
This fixes pr38723.
Reviewers: echristo, Bigcheese, MaskRay
Reviewed By: MaskRay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349074
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Craig Topper [Thu, 13 Dec 2018 19:08:10 +0000 (19:08 +0000)]
[CostModel][X86] Don't count 2 shuffles on the last level of a pairwise arithmetic or min/max reduction
This is split from D55452 with the correct patch this time.
Pairwise reductions require two shuffles on every level but the last. On the last level the two shuffles are <1, u, u, u...> and <0, u, u, u...>, but <0, u, u, u...> will be dropped by InstCombine/DAGCombine as being an identity shuffle.
Differential Revision: https://reviews.llvm.org/D55615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349072
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Stefan Granitz [Thu, 13 Dec 2018 18:51:19 +0000 (18:51 +0000)]
[CMake] llvm_codesign workaround for Xcode double-signing errors
Summary:
When using Xcode to build LLVM with code signing, the post-build rule is executed even if the actual build-step was skipped. This causes double-signing errors. We can currently only avoid it by passing the `--force` flag.
Plus some polishing for my previous patch D54443.
Reviewers: beanz, kubamracek
Reviewed By: kubamracek
Subscribers: #lldb, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D55116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349070
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Davide Italiano [Thu, 13 Dec 2018 18:37:23 +0000 (18:37 +0000)]
[LoopUtils] Use i32 instead of `void`.
The actual type of the first argument of the @dbg intrinsic
doesn't really matter as we're setting it to `undef`, but the
bitcode reader is picky about `void` types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349069
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Tom Stellard [Thu, 13 Dec 2018 18:21:23 +0000 (18:21 +0000)]
Don't add unnecessary compiler flags to llvm-config output
Summary:
llvm-config --cxxflags --cflags, should only output the minimal flags
required to link against the llvm libraries. They currently contain
all flags used to compile llvm including flags like -g, -pedantic,
-Wall, etc, which users may not always want.
This changes the llvm-config output to only include flags that have been
explictly added to the COMPILE_FLAGS property of the llvm-config target
by the llvm build system.
llvm.org/PR8220
Output from llvm-config when running cmake with:
cmake -G Ninja .. -DCMAKE_CXX_FLAGS=-funroll-loops
Before:
--cppflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include
-D_GNU_SOURCE -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
--cflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include
-fPIC -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings \
-Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough \
-Wno-comment -fdiagnostics-color -g -D_GNU_SOURCE -D_DEBUG -D__STDC_CONSTANT_MACROS \
-D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
--cxxflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include\
-funroll-loops -fPIC -fvisibility-inlines-hidden -Werror=date-time -std=c++11 -Wall \
-Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers \
-pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-maybe-uninitialized \
-Wno-class-memaccess -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment \
-fdiagnostics-color -g -fno-exceptions -fno-rtti -D_GNU_SOURCE -D_DEBUG \
-D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS"
After:
--cppflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include \
-D_GNU_SOURCE -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
--cflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include \
-D_GNU_SOURCE -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
--cxxflags: -I$HEADERS_DIR/llvm/include -I$HEADERS_DIR/llvm/build/include \
-std=c++11 -fno-exceptions -fno-rtti \
-D_GNU_SOURCE -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
Reviewers: sylvestre.ledru, infinity0, mgorny
Reviewed By: sylvestre.ledru, mgorny
Subscribers: mgorny, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D55391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349068
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Zachary Turner [Thu, 13 Dec 2018 18:11:33 +0000 (18:11 +0000)]
Correctly handle skewed streams in drop_front() method.
When calling BinaryStreamArray::drop_front(), if the stream
is skewed it means we must never drop the first bytes of the
stream since offsets which occur in records assume the existence
of those bytes. So if we want to skip the first record in a
stream, then what we really want to do is just set the begin
pointer to the next record. But we shouldn't actually remove
those bytes from the underlying view of the data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349066
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Francis Visoiu Mistrih [Thu, 13 Dec 2018 17:23:30 +0000 (17:23 +0000)]
[MachO][TLOF] Add support for local symbols in the indirect symbol table
On 32-bit archs, before, we would assume that an indirect symbol will
never have local linkage. This can lead to miscompiles where the
symbol's value would be 0 and the linker would use that value, because
the indirect symbol table would contain the value
`INDIRECT_SYMBOL_LOCAL` for that specific symbol.
Differential Revision: https://reviews.llvm.org/D55573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349060
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Sanjay Patel [Thu, 13 Dec 2018 17:05:01 +0000 (17:05 +0000)]
[DAGCombiner] after simplifying demanded elements of vector operand of extract, revisit the extract; 2nd try
This is a retry of rL349051 (reverted at rL349056). I changed the check for dead-ness from
number of uses to an opcode test for DELETED_NODE based on existing similar code.
Differential Revision: https://reviews.llvm.org/D55655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349058
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Simon Pilgrim [Thu, 13 Dec 2018 16:39:29 +0000 (16:39 +0000)]
[X86][SSE] Add SSE vector imm/var shift support to SimplifyDemandedVectorEltsForTargetNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349057
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Sanjay Patel [Thu, 13 Dec 2018 16:32:44 +0000 (16:32 +0000)]
revert rL349051: [DAGCombiner] after simplifying demanded elements of vector operand of extract, revisit the extract
This causes an address sanitizer bot failure:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/27187/steps/check-llvm%20asan/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349056
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Daniel Sanders [Thu, 13 Dec 2018 16:17:54 +0000 (16:17 +0000)]
Recommit r349041: [tblgen][disasm] Separate encodings from instructions
Removed const from the ArrayRef<const EncodingAndInst> to avoid the
std::vector<const EncodingAndInst> that G++ saw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349055
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Simon Pilgrim [Thu, 13 Dec 2018 15:50:31 +0000 (15:50 +0000)]
[X86][SSE] Fix all remaining modulo vector rotation amounts (PR38243)
There's still a couple of minor SimplifyDemandedElts regressions in some of the shift amount splats that will be fixed in future patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349052
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Sanjay Patel [Thu, 13 Dec 2018 15:44:26 +0000 (15:44 +0000)]
[DAGCombiner] after simplifying demanded elements of vector operand of extract, revisit the extract
Differential Revision: https://reviews.llvm.org/D55655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349051
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Daniel Cederman [Thu, 13 Dec 2018 15:29:12 +0000 (15:29 +0000)]
[Sparc] Add membar assembler tags
Summary: The Sparc V9 membar instruction can enforce different types of
memory orderings depending on the value in its immediate field. In the
architectural manual the type is selected by combining different assembler
tags into a mask. This patch adds support for these tags.
Reviewers: jyknight, venkatra, brad
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D53491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349048
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Simon Pilgrim [Thu, 13 Dec 2018 15:23:09 +0000 (15:23 +0000)]
[X86][SSE] Fix modulo rotation amounts for v8i16/v16i16/v4i32 (PR38243)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349047
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Daniel Sanders [Thu, 13 Dec 2018 15:14:21 +0000 (15:14 +0000)]
Revert r349041: [tblgen][disasm] Separate encodings from instructions
One of the GCC based bots is objecting to a vector of const EncodingAndInst's:
In file included from /usr/include/c++/8/vector:64,
from /export/users/atombot/llvm/clang-atom-d525-fedora-rel/llvm/utils/TableGen/CodeGenInstruction.h:22,
from /export/users/atombot/llvm/clang-atom-d525-fedora-rel/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp:15:
/usr/include/c++/8/bits/stl_vector.h: In instantiation of 'class std::vector<const {anonymous}::EncodingAndInst, std::allocator<const {anonymous}::EncodingAndInst> >':
/export/users/atombot/llvm/clang-atom-d525-fedora-rel/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp:375:32: required from here
/usr/include/c++/8/bits/stl_vector.h:351:21: error: static assertion failed: std::vector must have a non-const, non-volatile value_type
static_assert(is_same<typename remove_cv<_Tp>::type, _Tp>::value,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/include/c++/8/bits/stl_vector.h:354:21: error: static assertion failed: std::vector must have the same value_type as its allocator
static_assert(is_same<typename _Alloc::value_type, _Tp>::value,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349046
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Daniel Cederman [Thu, 13 Dec 2018 15:13:29 +0000 (15:13 +0000)]
[Sparc] Use float register for integer constrained with "f" in inline asm
Summary:
Constraining an integer value to a floating point register using "f"
causes an llvm_unreachable to trigger. This patch allows i32 integers
to be placed in a single precision float register and i64 integers to
be placed in a double precision float register. This matches the behavior
of GCC.
For other types the llvm_unreachable is removed to instead trigger an
error message that points out the offending line.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D51614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349045
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Jinsong Ji [Thu, 13 Dec 2018 15:12:57 +0000 (15:12 +0000)]
[PowerPC][NFC] Sorting out Pseudo related classes to avoid confusion
There are several Pseudo in PowerPC backend.
eg:
* ISel Pseudo-instructions , which has let usesCustomInserter=1 in td
ExpandISelPseudos -> EmitInstrWithCustomInserter will deal with them.
* Post-RA pseudo instruction, which has let isPseudo = 1 in td, or Standard pseudo (SUBREG_TO_REG,COPY etc.)
ExpandPostRAPseudos -> expandPostRAPseudo will expand them
* Multi-instruction pseudo operations will expand them PPCAsmPrinter::EmitInstruction
* Pseudo instruction in CodeEmitter, which has encoding of 0.
Currently, in td files, especially PPCInstrVSX.td,
we did not distinguish Post-RA pseudo instruction and Pseudo instruction in CodeEmitter very clearly.
This patch is to
* Rename Pseudo<> class to PPCEmitTimePseudo, which means encoding of 0 in CodeEmitter
* Introduce new class PPCPostRAExpPseudo <> for previous PostRA Pseudo
* Introduce new class PPCCustomInserterPseudo <> for previous Isel Pseudo
Differential Revision: https://reviews.llvm.org/D55143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349044
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Daniel Sanders [Thu, 13 Dec 2018 15:05:27 +0000 (15:05 +0000)]
[mir] Fix uninitialized variable in r349035 noticed by clang-atom-d525-fedora-rel and 3 other bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349043
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Daniel Sanders [Thu, 13 Dec 2018 14:55:57 +0000 (14:55 +0000)]
[tblgen][disasm] Separate encodings from instructions
Summary:
Separate the concept of an encoding from an instruction. This will enable
the definition of additional encodings for the same instruction which can
be used to support variable length instruction sets in the disassembler
(and potentially assembler but I'm not working towards that right now)
without causing an explosion in the number of Instruction records that
CodeGen then has to pick between.
Reviewers: bogner, charukcs
Reviewed By: bogner
Subscribers: kparzysz, llvm-commits
Differential Revision: https://reviews.llvm.org/D52366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349041
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Simon Pilgrim [Thu, 13 Dec 2018 14:51:28 +0000 (14:51 +0000)]
[X86][SSE] Merge the vXi16/vXi32 vector rotation expansion cases. NFCI.
Merged the repeated code into a single if().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349040
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Jonas Paulsson [Thu, 13 Dec 2018 14:37:05 +0000 (14:37 +0000)]
[SystemZ] Pass copy-hinted regs first from getRegAllocationHints().
When computing register allocation hints for a GRX32Bit register, make sure
that any of the hinted registers that are also copy hints are returned first
in the list.
Review: Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349037
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Daniel Sanders [Thu, 13 Dec 2018 14:25:27 +0000 (14:25 +0000)]
[mir] Serialize DILocation inline when not possible to use a metadata reference
Summary:
Sometimes MIR-level passes create DILocations that were not present in the
LLVM-IR. For example, it may merge two DILocations together to produce a
DILocation that points to line 0.
Previously, the address of these DILocations were printed which prevented the
MIR from being read back into LLVM. With this patch, DILocations will use
metadata references where possible and fall back on serializing them inline like so:
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 1, scope: !15)
Reviewers: aprantl, vsk, arphaman
Reviewed By: aprantl
Subscribers: probinson, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D55243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349035
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Simon Pilgrim [Thu, 13 Dec 2018 13:44:33 +0000 (13:44 +0000)]
[X86][BWI] Don't custom lower vXi8 rotations.
We always expand to shifts anyhow - test changes are just different scheduling only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349034
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Chen Zheng [Thu, 13 Dec 2018 12:55:42 +0000 (12:55 +0000)]
[NFC][PowerPC] add verify-machineinstrs check
After rL349029 and rL348566, sj-ctr-loop.ll is ok for verify-machineinstrs check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349030
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Chen Zheng [Thu, 13 Dec 2018 12:25:20 +0000 (12:25 +0000)]
[PowerPC] intrinsic llvm.eh.sjlj.setjmp should not have flag isBarrier.
Differential Revision: https://reviews.llvm.org/D55499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349029
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Simon Pilgrim [Thu, 13 Dec 2018 12:23:32 +0000 (12:23 +0000)]
[DAGCombine] Moved X86 rotate_amount % bitwidth == 0 early out to DAGCombiner
Remove common code from custom lowering (code is still safe if somehow a zero value gets used).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349028
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Diana Picus [Thu, 13 Dec 2018 12:06:54 +0000 (12:06 +0000)]
[ARM GlobalISel] Support exts and truncs for Thumb2
Mark G_SEXT, G_ZEXT and G_ANYEXT to 32 bits as legal and add support for
them in the instruction selector. This uses handwritten code again
because the patterns that are generated with TableGen are tuned for what
the DAG combiner would produce and not for simple sext/zext nodes.
Luckily, we only need to update the opcodes to use the Thumb2 variants,
everything else can be reused from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349026
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Simon Pilgrim [Thu, 13 Dec 2018 11:20:48 +0000 (11:20 +0000)]
[TargetLowering] Add ISD::ROTL/ROTR vector expansion
Move existing rotation expansion code into TargetLowering and set it up for vectors as well.
Ideally this would share more of the funnel shift expansion, but we handle the shift amount modulo quite differently at the moment.
Begun removing x86 vector rotate custom lowering to use the expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349025
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Alex Bradbury [Thu, 13 Dec 2018 10:49:05 +0000 (10:49 +0000)]
[RISCV] Add support for the various RISC-V FMA instruction variants
Adds support for the various RISC-V FMA instructions (fmadd, fmsub, fnmsub, fnmadd).
The criteria for choosing whether a fused add or subtract is used, as well as
whether the product is negated or not, is whether some of the arguments to the
llvm.fma.* intrinsic are negated or not. In the tests, extraneous fadd
instructions were added to avoid the negation being performed using a xor
trick, which prevented the proper FMA forms from being selected and thus
tested.
The FMA instruction patterns might seem incorrect (e.g., fnmadd: -rs1 * rs2 -
rs3), but they should be correct. The misleading names were inherited from
MIPS, where the negation happens after computing the sum.
The llvm.fmuladd.* intrinsics still do not generate RISC-V FMA instructions,
as that depends on TargetLowering::isFMAFasterthanFMulAndFAdd.
Some comments in the test files about what type of instructions are there
tested were updated, to better reflect the current content of those test
files.
Differential Revision: https://reviews.llvm.org/D54205
Patch by LuÃs Marques.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349023
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Arnaud A. de Grandmaison [Thu, 13 Dec 2018 10:31:32 +0000 (10:31 +0000)]
[AArch64] Catch some more CMN opportunities.
Fixes https://bugs.llvm.org/show_bug.cgi?id=33486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349022
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Clement Courbet [Thu, 13 Dec 2018 09:56:19 +0000 (09:56 +0000)]
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
Summary:
All targets either just return false here or properly model `Fast`, so I
don't think there is any reason to prevent CodeGen from doing the right
thing here.
Subscribers: nemanjai, javed.absar, eraman, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D55365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349016
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Vitaly Buka [Thu, 13 Dec 2018 09:47:39 +0000 (09:47 +0000)]
[asan] Don't check ODR violations for particular types of globals
Summary:
private and internal: should not trigger ODR at all.
unnamed_addr: current ODR checking approach fail and rereport false violation if
a linker merges such globals
linkonce_odr, weak_odr: could cause similar problems and they are already not
instrumented for ELF.
Reviewers: eugenis, kcc
Subscribers: kubamracek, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D55621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349015
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Matt Arsenault [Thu, 13 Dec 2018 08:27:48 +0000 (08:27 +0000)]
AMDGPU/GlobalISel: Legalize f64 fadd/fmul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349014
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Matt Arsenault [Thu, 13 Dec 2018 08:23:56 +0000 (08:23 +0000)]
Fix missing C++ mode comment in header
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349013
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Matt Arsenault [Thu, 13 Dec 2018 08:23:51 +0000 (08:23 +0000)]
AMDGPU/GlobalISel: RegBankSelect some simple operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349012
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Matt Arsenault [Thu, 13 Dec 2018 08:11:45 +0000 (08:11 +0000)]
AMDGPU/GlobalISel: Test cleanups
Remove IR and registers sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349011
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Craig Topper [Thu, 13 Dec 2018 06:14:25 +0000 (06:14 +0000)]
[X86] Remove assert leftover from when i1 was a legal type. Add more accurate assert. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349007
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Stanislav Mekhanoshin [Thu, 13 Dec 2018 05:52:11 +0000 (05:52 +0000)]
[AMDGPU] Fix build failure, second attempt
Some compilers complain that variable is captured and some
complain when it is not. Switch to [&].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349006
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Stanislav Mekhanoshin [Thu, 13 Dec 2018 05:21:25 +0000 (05:21 +0000)]
[AMDGPU] Fix build failure
Fixed error 'lambda capture 'CondReg' is not required to be captured
for this use'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349005
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Stanislav Mekhanoshin [Thu, 13 Dec 2018 03:17:40 +0000 (03:17 +0000)]
[AMDGPU] Simplify negated condition
Optimize sequence:
%sel = V_CNDMASK_B32_e64 0, 1, %cc
%cmp = V_CMP_NE_U32 1, %1
$vcc = S_AND_B64 $exec, %cmp
S_CBRANCH_VCC[N]Z
=>
$vcc = S_ANDN2_B64 $exec, %cc
S_CBRANCH_VCC[N]Z
It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
rebuildSetCC().
Differential Revision: https://reviews.llvm.org/D55402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349003
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David L. Jones [Thu, 13 Dec 2018 03:15:11 +0000 (03:15 +0000)]
Revert r348645 - "[MemCpyOpt] memset->memcpy forwarding with undef tail"
This revision caused trucated memsets for structs with padding. See:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20181210/610520.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349002
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Davide Italiano [Thu, 13 Dec 2018 01:11:52 +0000 (01:11 +0000)]
[LoopUtils] Prefer a set over a map. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348999
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Philip Reames [Thu, 13 Dec 2018 00:54:05 +0000 (00:54 +0000)]
[test] Add a set of test for constant folding deopt operands with CVP
For anyone curious, the first test example is illustrative of a real code idiom produced by branching on the result of a three way comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348997
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Shoaib Meenai [Thu, 13 Dec 2018 00:08:25 +0000 (00:08 +0000)]
[Support] Fix FileNameLength passed to SetFileInformationByHandle
The rename_internal function used for Windows has a minor bug where the
filename length is passed as a character count instead of a byte count.
Windows internally ignores this field, but other tools that hook NT
api's may use the documented behavior:
MSDN documentation specifying the size should be in bytes:
https://docs.microsoft.com/en-us/windows/desktop/api/winbase/ns-winbase-_file_rename_info
Patch by Ben Hillis.
Differential Revision: https://reviews.llvm.org/D55624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348995
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Shoaib Meenai [Wed, 12 Dec 2018 23:57:21 +0000 (23:57 +0000)]
[gn build] Fix defines define on Windows
On Windows, we won't go into the `host_os != "win"` block, so `defines`
won't have been defined, and we'll run into an undefined identifier
error when we try to later append to it. Unconditionally define it at
the start and append to it everywhere else.
Differential Revision: https://reviews.llvm.org/D55617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348993
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Daniel Sanders [Wed, 12 Dec 2018 23:48:13 +0000 (23:48 +0000)]
[globalisel] Add GISelChangeObserver::changingInstr()
Summary:
In addition to knowing that an instruction is changed. It's also useful to
know when it's about to change. For example, it might print the instruction so
you can track the changes in a debug log, it might remove it from some queue
while it's being worked on, or it might want to change several instructions as
a single transaction and act on all the changes at once.
Added changingInstr() to all existing uses of changedInstr()
Reviewers: aditya_nandakumar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D55623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348992
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Sam Clegg [Wed, 12 Dec 2018 23:40:58 +0000 (23:40 +0000)]
[WebAssembly] Update dylink section parsing
This updates the format of the dylink section in accordance with
recent "spec" change:
https://github.com/WebAssembly/tool-conventions/pull/77
Differential Revision: https://reviews.llvm.org/D55609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348989
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Davide Italiano [Wed, 12 Dec 2018 23:32:35 +0000 (23:32 +0000)]
[LoopDeletion] Update debug values after loop deletion.
When loops are deleted, we don't keep track of variables modified inside
the loops, so the DI will contain the wrong value for these.
e.g.
int b() {
int i;
for (i = 0; i < 2; i++)
;
patatino();
return a;
-> 6 patatino();
7 return a;
8 }
9 int main() { b(); }
(lldb) frame var i
(int) i = 0
We mark instead these values as unavailable inserting a
@llvm.dbg.value(undef to make sure we don't end up printing an incorrect
value in the debugger. We could consider doing something fancier,
for, e.g. constants, in the future.
PR39868.
rdar://problem/
46418795)
Differential Revision: https://reviews.llvm.org/D55299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348988
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Nikita Popov [Wed, 12 Dec 2018 23:19:03 +0000 (23:19 +0000)]
[InstCombine] Fix negative GEP offset evaluation for 32-bit pointers
This fixes https://bugs.llvm.org/show_bug.cgi?id=39908.
The evaluateGEPOffsetExpression() function simplifies GEP offsets for
use in comparisons against zero, basically by converting X*Scale+Offset==0
to X+Offset/Scale==0 if Scale divides Offset. However, before this is done,
Offset is masked down to the pointer size. This results in incorrect
results for negative Offsets, because we basically end up dividing the
32-bit offset *zero* extended to 64-bit bits (rather than sign extended).
Fix this by explicitly sign extending the truncated value.
Differential Revision: https://reviews.llvm.org/D55449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348987
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Fangrui Song [Wed, 12 Dec 2018 22:46:37 +0000 (22:46 +0000)]
[llvm-objcopy] Change Segment::Type from uint64_t to uint32_t
Summary:
In both Elf{32,64}_Phdr, the field Elf{32,64}_World p_type is uint32_t.
Also reorder the fields to be similar to Elf64_Phdr (which is different
from Elf32_Phdr but quite similar).
Reviewers: rupprecht, jhenderson, jakehehrlich, alexshap, espindola
Reviewed By: rupprecht
Subscribers: emaste, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D55618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348985
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Ryan Prichard [Wed, 12 Dec 2018 22:45:06 +0000 (22:45 +0000)]
[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)
Summary:
The change is needed to support ELF TLS in Android. See D55581 for the
same change in compiler-rt.
Reviewers: srhines, eugenis
Reviewed By: eugenis
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D55592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348983
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Sanjay Patel [Wed, 12 Dec 2018 22:11:05 +0000 (22:11 +0000)]
[PhaseOrdering] add test for funnel shift (rotate); NFC
As mentioned in D55604, there are 2 bugs here:
1. The new pass manager is speculating wildly by default.
2. The old pass manager is not converting this to funnel shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348980
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Daniel Sanders [Wed, 12 Dec 2018 21:32:01 +0000 (21:32 +0000)]
[globalisel] Rename GISelChangeObserver's erasedInstr() to erasingInstr() and related nits. NFC
Summary:
There's little of interest that can be done to an already-erased instruction.
You can't inspect it, write it to a debug log, etc. It ought to be notification
that we're about to erase it. Rename the function to clarify the timing of the
event and reflect current usage.
Also fixed one case where we were trying to print an erased instruction.
Reviewers: aditya_nandakumar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D55611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348976
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Craig Topper [Wed, 12 Dec 2018 21:21:31 +0000 (21:21 +0000)]
[X86] Don't emit MULX by default with BMI2
MULX has somewhat improved register allocation constraints compared to the legacy MUL instruction. Both output registers are encoded instead of fixed to EAX/EDX, but EDX is used as input. It also doesn't touch flags. Unfortunately, the encoding is longer.
Prefering it whenever BMI2 is enabled is probably not optimal. Choosing it should somehow be a function of register allocation constraints like converting adds to three address. gcc and icc definitely don't pick MULX by default. Not sure what if any rules they have for using it.
Differential Revision: https://reviews.llvm.org/D55565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348975
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David Blaikie [Wed, 12 Dec 2018 21:15:48 +0000 (21:15 +0000)]
Fix for llvm-dwarfdump changes for subroutine types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348974
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Craig Topper [Wed, 12 Dec 2018 20:50:24 +0000 (20:50 +0000)]
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well
A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX.
Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348972
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Aakanksha Patil [Wed, 12 Dec 2018 20:49:17 +0000 (20:49 +0000)]
[AMDGPU] Support for "uniform-work-group-size" attribute
Updated the annotate-kernel-features pass to support the propagation of uniform-work-group attribute from the kernel to the called functions. Once this pass is run, all kernels, even the ones which initially did not have the attribute, will be able to indicate weather or not they have uniform work group size depending on the value of the attribute.
Differential Revision: https://reviews.llvm.org/D50200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348971
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Saleem Abdulrasool [Wed, 12 Dec 2018 20:35:47 +0000 (20:35 +0000)]
Support: use internal `call_once` on PPC64le
Use the replacement execute once threading support in LLVM for PPC64le. It
seems that GCC does not define `__ppc__` and so we would actually call out to
the C++ runtime there which is not what the current code intended. Check both
`__ppc__` and `__PPC__`. This avoids the need for checking the endianness.
Thanks to nemanjai for the hint about GCC's behaviour and the fact that the
reviewed condition could be simplified.
Original patch by Sarvesh Tamba!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348970
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Simon Pilgrim [Wed, 12 Dec 2018 19:56:38 +0000 (19:56 +0000)]
[X86] Added missing constant pool checks. NFCI.
So the extra checks in D55600 don't look like a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348966
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David Blaikie [Wed, 12 Dec 2018 19:53:03 +0000 (19:53 +0000)]
DebugInfo/DWARF: Pretty print subroutine types
Doesn't handle varargs and other fun things, but it's a start. (also
doesn't print these strictly as valid C++ when it's a pointer to
function, it'll print as "void(int)*" instead of "void (*)(int)")
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348965
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Scott Linder [Wed, 12 Dec 2018 19:39:27 +0000 (19:39 +0000)]
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
Continue to present HSA metadata as YAML in ASM and when output by tools
(e.g. llvm-readobj), but encode it in Messagepack in the code object.
Differential Revision: https://reviews.llvm.org/D48179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348963
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David Blaikie [Wed, 12 Dec 2018 19:34:02 +0000 (19:34 +0000)]
DebugInfo/DWARF: Improve dumping of pointers to members ('int foo::*' rather than 'int*')
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348962
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David Blaikie [Wed, 12 Dec 2018 19:33:08 +0000 (19:33 +0000)]
DebugInfo/DWARF: Refactor type dumping to dump types, rather than DIEs that reference types
This lays the foundation for dumping types not referenced by DW_AT_type
attributes (in the near-term, that'll be DW_AT_containing_type for a
DW_TAG_ptr_to_member_type - in the future, potentially dumping the
pretty printed name next to the DW_TAG for the type, rather than only
when the type is referenced from elsewhere)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348961
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David Blaikie [Wed, 12 Dec 2018 19:23:55 +0000 (19:23 +0000)]
DebugInfo/DWARF: Refactor getAttributeValueAsReferencedDie to accept a DWARFFormValue
Save searching for the attribute again when you already have the
DWARFFormValue at hand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348960
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Craig Topper [Wed, 12 Dec 2018 19:20:21 +0000 (19:20 +0000)]
[X86] Emit SBB instead of SETCC_CARRY from LowerSELECT. Break false dependency on the SBB input.
I'm hoping we can just replace SETCC_CARRY with SBB. This is another step towards that.
I've explicitly used zero as the input to the setcc to avoid a false dependency that we've had with the SETCC_CARRY. I changed one of the patterns that used NEG to instead use an explicit compare with 0 on the LHS. We needed the zero anyway to avoid the false dependency. The negate would clobber its input register. By using a CMP we can avoid that which could be useful.
Differential Revision: https://reviews.llvm.org/D55414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348959
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Simon Pilgrim [Wed, 12 Dec 2018 19:01:39 +0000 (19:01 +0000)]
Fix Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348958
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Florian Hahn [Wed, 12 Dec 2018 18:55:14 +0000 (18:55 +0000)]
[ConstantFold] Use getMinSignedBits for APInt in isIndexInRangeOfArrayType.
Indices for getelementptr can be signed so we should use
getMinSignedBits instead of getActiveBits here. The function later calls
getSExtValue to get the int64_t value, which also checks
getMinSignedBits.
This fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=11647.
Reviewers: mssimpso, efriedma, davide
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D55536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348957
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Simon Pilgrim [Wed, 12 Dec 2018 18:53:12 +0000 (18:53 +0000)]
[X86] Added missing constant pool checks. NFCI.
So the extra checks in D55600 don't look like a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348956
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David Blaikie [Wed, 12 Dec 2018 18:46:25 +0000 (18:46 +0000)]
llvm-dwarfdump: Dump array dimensions in stringified type names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348954
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Simon Pilgrim [Wed, 12 Dec 2018 18:32:29 +0000 (18:32 +0000)]
[SelectionDAG] Add a generic isSplatValue function
This patch introduces a generic function to determine whether a given vector type is known to be a splat value for the specified demanded elements, recursing up the DAG looking for BUILD_VECTOR or VECTOR_SHUFFLE splat patterns.
It also keeps track of the elements that are known to be UNDEF - it returns true if all the demanded elements are UNDEF (as this may be useful under some circumstances), so this needs to be handled by the caller.
A wrapper variant is also provided that doesn't take the DemandedElts or UndefElts arguments for cases where we just want to know if the SDValue is a splat or not (with/without UNDEFS).
I had hoped to completely remove the X86 local version of this function, but I'm seeing some regressions in shift/rotate codegen that will take a little longer to fix and I hope to get this in sooner so I can continue work on PR38243 which needs more capable splat detection.
Differential Revision: https://reviews.llvm.org/D55426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348953
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Artem Belevich [Wed, 12 Dec 2018 18:31:04 +0000 (18:31 +0000)]
[NVPTX] do not rely on cached subtarget info.
If a module has function references, but no functions
themselves, we may end up never calling runOnMachineFunction
and therefore would never initialize nvptxSubtarget field
which would eventually cause a crash.
Instead of relying on nvptxSubtarget being initialized by
one of the methods, retrieve subtarget info directly.
Differential Revision: https://reviews.llvm.org/D55580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348952
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Michael Kruse [Wed, 12 Dec 2018 18:07:19 +0000 (18:07 +0000)]
[LV] Fix signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348949
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Nico Weber [Wed, 12 Dec 2018 18:04:57 +0000 (18:04 +0000)]
[gn build] Merge r348944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348948
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Michael Kruse [Wed, 12 Dec 2018 17:59:01 +0000 (17:59 +0000)]
[docs] Use correct ending quotes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348947
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