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Mikhail Dvoretckii [Tue, 19 Jun 2018 10:49:12 +0000 (10:49 +0000)]
[InstCombine] Replacing X86-specific rounding intrinsics with generic floor-ceil
This patch replaces calls to X86-specific intrinsics with floor-ceil semantics
with calls to target-independent @llvm.floor.* and @llvm.ceil.* intrinsics. This
doesn't affect the resulting machine code, as those intrinsics are lowered to
the same instructions, but exposes these specific rounding cases to generic
optimizations.
Differential Revision: https://reviews.llvm.org/D48067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335039
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Clement Courbet [Tue, 19 Jun 2018 10:39:50 +0000 (10:39 +0000)]
[llvm-exegesis] A mechanism to add target-specific functionality.
Summary: This is a step towards implementing memory operands and X87.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335038
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Mikhail Dvoretckii [Tue, 19 Jun 2018 10:37:52 +0000 (10:37 +0000)]
[X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns
This patch handles back-end folding of generic patterns created by lowering the
X86 rounding intrinsics to native IR in cases where the instruction isn't a
straightforward packed values rounding operation, but a masked operation or a
scalar operation.
Differential Revision: https://reviews.llvm.org/D45203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335037
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David Green [Tue, 19 Jun 2018 09:43:36 +0000 (09:43 +0000)]
[LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFG
LoopSimplifyCFG, being a loop pass, needs to preserve scalar
evolution. This invalidates SE for the loops altered during
block merging.
Differential Revision: https://reviews.llvm.org/D48258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335036
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Roman Lebedev [Tue, 19 Jun 2018 09:21:27 +0000 (09:21 +0000)]
[MCA][NFC] Add generic XOP resource tests
Summary:
Based on
* [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]],
* [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]],
* https://en.wikipedia.org/wiki/XOP_instruction_set
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, andreadb, spatel
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335034
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Roman Lebedev [Tue, 19 Jun 2018 09:21:22 +0000 (09:21 +0000)]
[MCA][NFC] Add generic TBM resource tests
Summary:
Based on https://support.amd.com/TechDocs/24594.pdf,
https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, simark, andreadb
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335033
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Simon Pilgrim [Tue, 19 Jun 2018 09:16:06 +0000 (09:16 +0000)]
[SLPVectorizer] Pull out AltOpcode determination from reorderAltShuffleOperands.
Minor step towards making the alternate opcode system work with a wider range of opcode pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335032
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Bjorn Pettersson [Tue, 19 Jun 2018 08:41:34 +0000 (08:41 +0000)]
Remove valueCoversEntireFragment asserts in ConvertDebugDeclareToDebugValue
This is a fixup for r334830 causing problems in polly-aosp buildbot.
Focus in r334830 was to fix a problem seen with
ConvertDebugDeclareToDebugValue involving store instructions.
It also added some asserts to find out of similar problems
existed for the ConvertDebugDeclareToDebugValue functions
involving load and phi instructions. One of those asserts seems
to blow in the polly-aosp buildbot, so I'll revert the asserts
while debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335031
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Adrian Kuegel [Tue, 19 Jun 2018 08:12:28 +0000 (08:12 +0000)]
Add a factory method to ConstantDataArray that allows to pass in the data as StringRef
This simplifies the case if we already have access to the raw data that we need to store in a ConstantDataArray.
The new factor method can also be reused for implementing the factory method that gets the data as ArrayRef.
Differential Revision: https://reviews.llvm.org/D47706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335028
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Florian Hahn [Tue, 19 Jun 2018 08:03:24 +0000 (08:03 +0000)]
[LoopInterchange] Move PHI handling to adjustLoopBranches.
This patch moves the logic to handle reduction PHI nodes to the end of
adjustLoopBranches. Reduction PHI nodes in the outer loop header can be
moved to the inner loop header and reduction PHI nodes from the inner loop
header can be moved to the outer loop header. In the latter situation,
we have to deal with 1 kind of PHI nodes:
PHI nodes that are part of inner loop-only reductions.
We can replace the PHI node with the value coming from outside
the inner loop.
Reviewers: mcrosier, efriedma, karthikthecool
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D46198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335027
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Mikhail Dvoretckii [Tue, 19 Jun 2018 07:55:10 +0000 (07:55 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335026
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QingShan Zhang [Tue, 19 Jun 2018 06:54:51 +0000 (06:54 +0000)]
If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating,
and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction.
Differential Revision: https://reviews.llvm.org/D47568
Reviewed By: Nemanjai
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335024
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Roger Ferrer Ibanez [Tue, 19 Jun 2018 06:45:47 +0000 (06:45 +0000)]
[RISCV] Add tests for overflow intrinsics
This is using the existing codegen so we can see the change once we custom
lower ISD::{U,S}{ADD,SUB}O nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335023
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Max Kazantsev [Tue, 19 Jun 2018 04:48:34 +0000 (04:48 +0000)]
[SimplifyIndVars] Eliminate redundant truncs
This patch adds logic to deal with the following constructions:
%iv = phi i64 ...
%trunc = trunc i64 %iv to i32
%cmp = icmp <pred> i32 %trunc, %invariant
Replacing it with
%iv = phi i64 ...
%cmp = icmp <pred> i64 %iv, sext/zext(%invariant)
In case if it is legal. Specifically, if `%iv` has signed comparison users, it is
required that `sext(trunc(%iv)) == %iv`, and if it has unsigned comparison
uses then we require `zext(trunc(%iv)) == %iv`. The current implementation
bails if `%trunc` has other uses than `icmp`, but in theory we can handle more
cases here (e.g. if the user of trunc is bitcast).
Differential Revision: https://reviews.llvm.org/D47928
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335020
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Craig Topper [Tue, 19 Jun 2018 04:24:44 +0000 (04:24 +0000)]
[X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.
This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information.
Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions.
Finally, remove the manual table from the emitter.
This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335018
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Craig Topper [Tue, 19 Jun 2018 04:24:42 +0000 (04:24 +0000)]
[X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.
EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity.
The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1.
This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0.
This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335017
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Sanjoy Das [Tue, 19 Jun 2018 04:09:44 +0000 (04:09 +0000)]
Revert "[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags"
This reverts r334428. It incorrectly marks some multiplications as nuw. Tim
Shen is working on a proper fix.
Original commit message:
[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe.
Summary:
Previously we would add them for adds, but not multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335016
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Craig Topper [Tue, 19 Jun 2018 03:17:46 +0000 (03:17 +0000)]
[X86] Simplify the TSFlags checking code in EvexToVexInstPass. NFCI
The code was previously checking the L2 and L flag on 3 separate lines, treating the combination as an encoding. Instead its better to think of the L2 bit as being something that can't be done with VEX and early returning. Then we just need to check the L bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335015
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Heejin Ahn [Tue, 19 Jun 2018 01:23:14 +0000 (01:23 +0000)]
[WebAssembly] Remove an extra ';' at the end of a namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335008
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Heejin Ahn [Tue, 19 Jun 2018 00:32:03 +0000 (00:32 +0000)]
[WebAssembly] Add more utility functions
Summary:
Added more utility functions that will be used in EH-related passes Also
changed `LoopBottom` function to `getBottom` and uses templates to be
able to handle other classes as well, which will be used in CFGSort
later.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335006
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Heejin Ahn [Tue, 19 Jun 2018 00:26:39 +0000 (00:26 +0000)]
[WebAssembly] Add WasmEHFuncInfo for unwind destination information
Summary:
Add WasmEHFuncInfo and routines to calculate and fill in this struct to
keep track of unwind destination information. This will be used in
other EH related passes.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D48263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335005
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Eli Friedman [Tue, 19 Jun 2018 00:14:10 +0000 (00:14 +0000)]
[ARM] Thumb2 constant cmp testcases.
Shows some missed optimizations for the -
7929856 and -2166 testcases.
-
7929856 is due to a bug in ARMTargetLowering::getARMCmp, I think;
the -2166 case is a missing pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335004
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Eli Friedman [Tue, 19 Jun 2018 00:12:13 +0000 (00:12 +0000)]
[ARM] Testcase for Thumb1 cmp with constants.
Even if a comparison isn't legal, we should try to prefer constants
which can be materialized with a two-instruction sequence. (Thinking
about it a bit more, there might be some more clever sequence we could
generate for certain comparisons invoving powers of two, but I'm not
sure exactly what that would look like.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335003
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Eli Friedman [Tue, 19 Jun 2018 00:09:44 +0000 (00:09 +0000)]
[ARM] Add Thumb1 coverage for cmn testcases.
There's a missed optimization for immediates: we can save two
instructions by using adds instead of movs+mvns+cmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335002
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Eli Friedman [Tue, 19 Jun 2018 00:08:32 +0000 (00:08 +0000)]
[ARM] Testcase for missed optimization for masking.
When the result of masking is truncated to i16, we should try to use
"bic" instead of "and".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335001
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Eli Friedman [Tue, 19 Jun 2018 00:07:30 +0000 (00:07 +0000)]
[ARM] Testcase for missed optimization with i16 compare.
The result looks weird because the DAG actually has an explicit
shift; I haven't figured out why, exactly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335000
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Derek Schuff [Tue, 19 Jun 2018 00:02:34 +0000 (00:02 +0000)]
[WebAssembly] Fixed disassembler unit test failure.
Summary: A recent commit forgot to update the unit tests.
Differential Revision: https://reviews.llvm.org/D48304
Patch by Wouter Van Oortmerssen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334999
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Heejin Ahn [Mon, 18 Jun 2018 23:54:29 +0000 (23:54 +0000)]
[WebAssembly] Make rethrow instruction take a target BB argument
Summary:
This patch changes the rethrow instruction to take a BB argument in LLVM
backend, like `br` and `br_if`s. This BB is a target catch BB the
rethrow instruction unwinds to. This BB argument will be converted to an
relative depth immediate at the end of CFGStackify pass, as in the same
way of branches.
RETHROW_TO_CALLER is a codegen-only instruction that should be used when
a rethrow instruction does not have an unwind destination BB, i.e., it
should rethrow to its caller function.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334998
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Heejin Ahn [Mon, 18 Jun 2018 23:51:16 +0000 (23:51 +0000)]
[VPlan] Add Analysis and Core to LLVM_LINK_COMPONENTS
Summary: Without these, build with `-DSHARED_LIB=ON` fails.
Reviewers: dschuff
Subscribers: mgorny, bollu, tschuett, rkruppe, rogfer01, llvm-commits
Differential Revision: https://reviews.llvm.org/D48300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334997
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Michael Berg [Mon, 18 Jun 2018 23:44:59 +0000 (23:44 +0000)]
Utilize new SDNode flag functionality to expand current support for fadd
Summary: This patch originated from D46562 and is a proper subset, with some issues addressed.
Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar
Reviewed By: spatel
Subscribers: wdng, nhaehnle
Differential Revision: https://reviews.llvm.org/D47909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334996
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Craig Topper [Mon, 18 Jun 2018 23:20:57 +0000 (23:20 +0000)]
[X86] Remove ReadAfterLd from avx512_shift_rmbi multiclass.
The instructions that use this class don't have another source register. So I think this was just marking one of the address operands as ReadAfterLd?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334994
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Xin Tong [Mon, 18 Jun 2018 23:20:08 +0000 (23:20 +0000)]
Revert "Simplify blockaddress usage before giving up in MergeBlockIntoPredecessor"
This reverts commit
f976cf4cca0794267f28b54e468007fd476d37d9.
I am reverting this because it causes break in a few bots and its going
to take me sometime to look at this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334993
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Xin Tong [Mon, 18 Jun 2018 22:59:13 +0000 (22:59 +0000)]
Simplify blockaddress usage before giving up in MergeBlockIntoPredecessor
Summary:
Simplify blockaddress usage before giving up in MergeBlockIntoPredecessor
This is a missing small optimization in MergeBlockIntoPredecessor.
This helps with one simplifycfg test which expects this case to be handled.
Reviewers: davide, spatel, brzycki, asbirlea
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334992
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Eric Christopher [Mon, 18 Jun 2018 22:21:19 +0000 (22:21 +0000)]
Tidy comment language and explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334990
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Eric Christopher [Mon, 18 Jun 2018 22:21:18 +0000 (22:21 +0000)]
Pull non-lazy stub table emission into a separate function alongside
the individual stub creation to increase readability a bit in the
non-object file format specific function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334989
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Eric Christopher [Mon, 18 Jun 2018 22:21:13 +0000 (22:21 +0000)]
Add return statements to make it clear that all of these are mutually exclusive conditions.
else if would have worked just as well, but this keeps the original readability a bit more clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334988
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Stanislav Mekhanoshin [Mon, 18 Jun 2018 21:49:07 +0000 (21:49 +0000)]
Tests for dag combine select (binop) -> select. NFC.
Tests will be updated with https://reviews.llvm.org/D48223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334987
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Matt Davis [Mon, 18 Jun 2018 21:38:38 +0000 (21:38 +0000)]
[llvm-mca] Cleanup the header syntax line. Fix a comment. NFC.
This patch removes a few dashes from the header comment to make room for the syntax line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334986
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Wouter van Oortmerssen [Mon, 18 Jun 2018 21:22:44 +0000 (21:22 +0000)]
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.
Summary:
One for register based, much like the existing definitions,
and one for stack based (suffix _S).
This allows us to use registers in most of LLVM (which works better),
and stack based in MC (which results in a simpler and more readable
assembler / disassembler).
Tried to keep this change as small as possible while passing tests,
follow-up commit will:
- Add reg->stack conversion in MI.
- Fix asm/disasm in MC to be stack based.
- Fix emitter to be stack based.
tests passing:
llvm-lit -v `find test -name WebAssembly`
test/CodeGen/WebAssembly
test/MC/WebAssembly
test/MC/Disassembler/WebAssembly
test/DebugInfo/WebAssembly
test/CodeGen/MIR/WebAssembly
test/tools/llvm-objdump/WebAssembly
Reviewers: dschuff, sbc100, jgravelle-google, sunfish
Subscribers: aheejin, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D48183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334985
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Michael Berg [Mon, 18 Jun 2018 21:12:21 +0000 (21:12 +0000)]
refactor of visitFADD for AllowNewConst cases
Summary: Refactoring for all constant cases which require AllowNewConst and some staging for future fmf usage.
Reviewers: spatel, hfinkel, wristow
Reviewed By: spatel
Subscribers: nhaehnle
Differential Revision: https://reviews.llvm.org/D48289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334984
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Sander de Smalen [Mon, 18 Jun 2018 21:03:02 +0000 (21:03 +0000)]
[AArch64][SVE] Asm: Fix predicate pattern diagnostics.
This patch uses the DiagnosticPredicate for SVE predicate patterns
to improve their diagnostics, now giving a 'invalid operand' diagnostic
if the type is not an immediate or one of the expected pattern
labels.
Reviewers: samparker, SjoerdMeijer, javed.absar, fhahn
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334983
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Sander de Smalen [Mon, 18 Jun 2018 20:50:33 +0000 (20:50 +0000)]
[AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.
The variants added by this patch are:
- SQINC signed increment, e.g. sqinc x0, w0, all, mul #4
- SQDEC signed decrement, e.g. sqdec x0, w0, all, mul #4
- UQINC unsigned increment, e.g. uqinc w0, all, mul #4
- UQDEC unsigned decrement, e.g. uqdec w0, all, mul #4
This patch includes asmparser changes to parse a GPR64 as a GPR32 in
order to satisfy the constraint check:
x0 == GPR64(w0)
in:
sqinc x0, w0, all, mul #4
^___^ (must match)
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334980
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Wouter van Oortmerssen [Mon, 18 Jun 2018 20:45:49 +0000 (20:45 +0000)]
[WebAssembly] Cleaned up register accessors in WebAssemblyMachineFunctionInfo.h
Tested: llvm-lit -v `find test -name WebAssembly`
(This is a commit access "test commit" :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334979
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Sanjay Patel [Mon, 18 Jun 2018 20:05:16 +0000 (20:05 +0000)]
[x86] regenerate checks and adjust tests
2 of these tests were clearly not doing what the comments
said they were doing.
The last test was added at rL177933 with no assertions
(presumably it used to crash). But either we don't have
that problem anymore, or this test is folded sooner,
so we don't hit the bug that was fixed by disabling late
FP constant creation. Looking at this as part of reviewing
D48289.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334977
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Simon Pilgrim [Mon, 18 Jun 2018 20:05:02 +0000 (20:05 +0000)]
[docs] Fix indentation of llvm-exegesis command line arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334976
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Craig Topper [Mon, 18 Jun 2018 18:47:07 +0000 (18:47 +0000)]
[X86] Encode the EVEX2VEX exception list information in .td files instead of the emitter source.
Rather than having an exclusion list in tablegen sources, add a flag to the X86 instruction records that can be used to suppress checking for convertibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334971
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Michael Berg [Mon, 18 Jun 2018 18:37:48 +0000 (18:37 +0000)]
[NFC] make MIFlag accessor functions consistant with usage model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334970
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Florian Hahn [Mon, 18 Jun 2018 18:28:49 +0000 (18:28 +0000)]
[VPlan] Add VPInstruction to VPRecipe transformation.
This patch introduces a VPInstructionToVPRecipe transformation, which
allows us to generate code for a VPInstruction based VPlan re-using the
existing infrastructure.
Reviewers: dcaballe, hsaito, mssimpso, hfinkel, rengolin, mkuper, javed.absar, sguggill
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D46827
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334969
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Lang Hames [Mon, 18 Jun 2018 18:01:43 +0000 (18:01 +0000)]
[ORC] Add an initial implementation of a replacement CompileOnDemandLayer.
CompileOnDemandLayer2 is a replacement for CompileOnDemandLayer built on the ORC
Core APIs. Functions in added modules are extracted and compiled lazily.
CompileOnDemandLayer2 supports multithreaded JIT'd code, and compilation on
multiple threads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334967
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Lang Hames [Mon, 18 Jun 2018 18:01:41 +0000 (18:01 +0000)]
[ORC] Keep weak flag on VSO symbol tables during materialization, but treat
materializing weak symbols as strong.
This removes some elaborate flag tweaking and plays nicer with RuntimeDyld,
which relies of weak/common flags to determine whether it should emit a given
weak definition. (Switching to strong up-front makes it appear as if there is
already an overriding definition, which would require an extra back-channel to
override).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334966
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Krzysztof Parzyszek [Mon, 18 Jun 2018 17:16:39 +0000 (17:16 +0000)]
Shrink interval after moving copy in removePartialRedundancy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334963
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Andrea Di Biagio [Mon, 18 Jun 2018 17:04:56 +0000 (17:04 +0000)]
[llvm-mca] Use an ordered map to collect hardware statistics. NFC.
Histogram entries are now ordered by key. This should improves their
readability when statistics are printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334961
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Nirav Dave [Mon, 18 Jun 2018 16:26:11 +0000 (16:26 +0000)]
Fix typoed cast to avoid assertion in MCFragment::dump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334959
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Simon Pilgrim [Mon, 18 Jun 2018 16:25:01 +0000 (16:25 +0000)]
[SLPVectorizer] Tidyup isShuffle helper
Ensure we keep track of the input vectors in all cases instead of just for SK_Select.
Ideally we'd reuse the shuffle mask pattern matching in TargetTransformInfo::getInstructionThroughput here to easily add support for all TargetTransformInfo::ShuffleKind without mass code duplication, I've added a TODO for now but D48236 should help us here.
Differential Revision: https://reviews.llvm.org/D48023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334958
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Craig Topper [Mon, 18 Jun 2018 16:17:46 +0000 (16:17 +0000)]
[TableGen] Make TiedAsmOperandTable in the AsmMatcher 'static' since its at file scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334957
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Craig Topper [Mon, 18 Jun 2018 16:17:45 +0000 (16:17 +0000)]
[TableGen] Remove unused member variable.
I think this became unused after r324196.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334956
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Florian Hahn [Mon, 18 Jun 2018 15:18:48 +0000 (15:18 +0000)]
[VPlanRecipeBase] Add eraseFromParent().
Reviewers: dcaballe, hsaito, mkuper, hfinkel
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D48081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334951
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Sander de Smalen [Mon, 18 Jun 2018 14:47:52 +0000 (14:47 +0000)]
[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.
Summary:
The variants added by this patch are:
- SQINC (signed increment)
- UQINC (unsigned increment)
- SQDEC (signed decrement)
- UQDEC (unsigned decrement)
For example:
uqincw x0, all, mul #4
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Differential Revision: https://reviews.llvm.org/D47715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334948
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Simon Pilgrim [Mon, 18 Jun 2018 14:31:14 +0000 (14:31 +0000)]
[X86][BtVer2] Flag AVX2+ scheduler classes as unsupported
Jaguar only supports up to AVX1
Differential Revision: https://reviews.llvm.org/D48274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334947
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Andrea Di Biagio [Mon, 18 Jun 2018 14:00:30 +0000 (14:00 +0000)]
[llvm-mca] Add tests for XOP and AVX512 instructions that implicitly clear the upper portion of a super-register.
When the destination register of a XOP instruction is an XMM register, bits
[255:128] of the corresponding YMM register are cleared.
When the destination register of a EVEX encoded instruction is an XMM/YMM
register, the upper bits of the corresponding ZMM are cleared.
On processors that feature AVX512, a write to an XMM registers always clears the
upper portion of the corresponding ZMM register if the instruction is VEX or
EVEX encoded.
These new tests show some interesting cases which aren't correctly analyzed by
llvm-mca. The lack of knowledge related to the implicit update on the
super-registers is addressed by D48225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334945
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Florian Hahn [Mon, 18 Jun 2018 13:51:28 +0000 (13:51 +0000)]
[VPlan] Fix sanitizer problem with insertBefore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334943
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Sander de Smalen [Mon, 18 Jun 2018 13:39:29 +0000 (13:39 +0000)]
[TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases.
Allow a tied operand of a different operand class in InstAliases,
so that the operand can be printed (and added to the MC instruction)
as the appropriate register. For example, 'GPR64as32', which would
be printed/parsed as a 32bit register and should match a tied 64bit
register operand, where the former is a sub-register of the latter.
This patch also generalizes the constraint checking to an overrideable
method in MCTargetAsmParser, so that target asmparsers can specify
whether a given operand satisfies the tied register constraint.
Reviewers: olista01, rengolin, fhahn, SjoerdMeijer, samparker, dsanders, craig.topper
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334942
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Paul Robinson [Mon, 18 Jun 2018 12:22:17 +0000 (12:22 +0000)]
Update copyright year to 2018.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334936
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Simon Pilgrim [Mon, 18 Jun 2018 11:35:36 +0000 (11:35 +0000)]
[SLPVectorizer] Avoid calling const VL.size() repeatedly in for-loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334934
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Florian Hahn [Mon, 18 Jun 2018 11:34:17 +0000 (11:34 +0000)]
[VPlanRecipeBase] Add insertBefore helper.
Reviewers: dcaballe, mkuper, hfinkel, hsaito, mssimpso
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D48080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334933
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Clement Courbet [Mon, 18 Jun 2018 11:27:47 +0000 (11:27 +0000)]
[llvm-exegesis] Optionally ignore instructions without a sched class.
Summary: See PR37602.
Reviewers: RKSimon
Subscribers: llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D48267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334932
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Sander de Smalen [Mon, 18 Jun 2018 10:59:19 +0000 (10:59 +0000)]
[AArch64][SVE] Asm: Support for vector element compares.
This patch adds instructions for comparing elements from two vectors, e.g.
cmpgt p0.s, p0/z, z0.s, z1.s
and also adds support for comparing to a 64-bit wide element vector, e.g.
cmpgt p0.s, p0/z, z0.s, z1.d
The patch also contains aliases for certain comparisons, e.g.:
cmple p0.s, p0/z, z0.s, z1.s => cmpge p0.s, p0/z, z1.s, z0.s
cmplo p0.s, p0/z, z0.s, z1.s => cmphi p0.s, p0/z, z1.s, z0.s
cmpls p0.s, p0/z, z0.s, z1.s => cmphs p0.s, p0/z, z1.s, z0.s
cmplt p0.s, p0/z, z0.s, z1.s => cmpgt p0.s, p0/z, z1.s, z0.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334931
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Clement Courbet [Mon, 18 Jun 2018 06:48:22 +0000 (06:48 +0000)]
[X86] Fix NOOP sched overrides on BDW/HSW/SKL.
Summary: Noop certainly does not use resources.
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits, gchatelet
Differential Revision: https://reviews.llvm.org/D48028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334927
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Craig Topper [Mon, 18 Jun 2018 06:32:22 +0000 (06:32 +0000)]
[X86] Create X86InstrFMA3Group objects fully in a static table instead of on the heap. NFCI
Previously we heap allocated the X86InstrFMA3Group objects which were created by passing them small register/memory opcode arrays that existed as individual static tables.
Rather than a bunch of small static arrays we now have one large static table of X86InstrFMA3Group objects. Rather than storing a pointer to the opcode arrays in the X86InstrFMA3Group object, we now store have a register and memory array as part of the object. If a group doesn't have memory or register opcodes, the array entries will be 0.
This greatly simplifies the destruction of the X86InstrFMA3Info object. We no longer need to delete the X86InstrFMA3Group objects as we destruct the DenseMap. And we don't need to keep track of which ones we already deleted.
This reduces the llc binary size on my local machine by ~50k. I can only assume that's really due to the fact that we had something like 512 small static arrays that we passed to the init functions either one at a time or in pairs. So there were between 256 and 512 distinct calls to the init functions in the initOnceImpl method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334925
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Craig Topper [Mon, 18 Jun 2018 05:00:50 +0000 (05:00 +0000)]
[X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions.
Also remove the vpextrw.s EVEX alias. That's not something gas implements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334922
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Craig Topper [Mon, 18 Jun 2018 01:28:05 +0000 (01:28 +0000)]
[X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves with reversed operands to InstAliases.
The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser.
Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334920
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Craig Topper [Mon, 18 Jun 2018 01:28:01 +0000 (01:28 +0000)]
[TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter.
Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string.
AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well.
To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334919
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Lang Hames [Sun, 17 Jun 2018 23:54:58 +0000 (23:54 +0000)]
[ORC] Remove redundant condition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334918
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Lang Hames [Sun, 17 Jun 2018 18:59:01 +0000 (18:59 +0000)]
[ORC] Only notify queries that they are resolved/ready when the query state
changes.
This guards against redundant notifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334916
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Craig Topper [Sun, 17 Jun 2018 18:00:16 +0000 (18:00 +0000)]
[X86] Add all the FMA instructions direclty to the load folding table instead of proxying through X86InstrFMA3Info.
These increases the size of the static tables, but is closer to what we would get if used the autogenerated table directly. This reduces the remaining large deltas between what's in the manual table and what's in the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334915
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Lang Hames [Sun, 17 Jun 2018 17:18:12 +0000 (17:18 +0000)]
[ORC] Suppress an unused variable warning for a debug-mode only use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334911
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Lang Hames [Sun, 17 Jun 2018 16:59:53 +0000 (16:59 +0000)]
[ORC] Erase empty dependence sets when adding new symbol dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334910
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Lang Hames [Sun, 17 Jun 2018 16:59:52 +0000 (16:59 +0000)]
[ORC] In MaterializationResponsibility, only maintain the Materializing flag on
symbols in debug mode.
The MaterializationResponsibility class hijacks the Materializing flag to track
symbols that have not yet been resolved in order to guard against redundant
resolution. Since this is an API contract check and only enforced in debug mode
there is no reason to maintain the flag state in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334909
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Craig Topper [Sun, 17 Jun 2018 16:29:46 +0000 (16:29 +0000)]
[X86] Pass the parent SDNode to X86DAGToDAGISel::selectScalarSSELoad to simplify the hasSingleUseFromRoot handling.
Some of the calls to hasSingleUseFromRoot were passing the load itself. If the load's chain result has a user this would count against that. By getting the true parent of the match and ensuring any intermediate between the match and the load have a single use we can avoid this case. isLegalToFold will take care of checking users of the load's data output.
This fixed at least fma-scalar-memfold.ll to succed without the peephole pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334908
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Simon Pilgrim [Sun, 17 Jun 2018 16:25:48 +0000 (16:25 +0000)]
[llvm-mca][X86] Add some avx512f/avx512vl resource test placeholders
There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334907
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Sander de Smalen [Sun, 17 Jun 2018 10:48:21 +0000 (10:48 +0000)]
[AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.
This patch adds support for instructions performing bitwise operations
on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and
their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS.
This patch also adds several aliases:
orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b
orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b
and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b
ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b
eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b
eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334906
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Sander de Smalen [Sun, 17 Jun 2018 10:11:04 +0000 (10:11 +0000)]
[AArch64][SVE] Asm: Support for SEL (vector/predicate) instructions.
Support for SVE's predicated select instructions to select elements
from either vector, both in a data-vector and a predicate-vector
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334905
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Jonas Hahnfeld [Sun, 17 Jun 2018 09:55:20 +0000 (09:55 +0000)]
[NVPTX] Ignore target-cpu and -features for inlining
We don't want to prevent inlining because of target-cpu and -features
attributes that were added to newer versions of LLVM/Clang: There are
no incompatible functions in PTX, ptxas will throw errors in such cases.
Differential Revision: https://reviews.llvm.org/D47691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334904
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Heejin Ahn [Sun, 17 Jun 2018 00:37:56 +0000 (00:37 +0000)]
[WebAssembly] Simple comment fix. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334899
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Craig Topper [Sat, 16 Jun 2018 23:25:50 +0000 (23:25 +0000)]
[X86] More additions to the load folding tables based on the autogenerated tables.
Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334898
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Craig Topper [Sat, 16 Jun 2018 23:25:48 +0000 (23:25 +0000)]
[X86] Hide POP16/32/64rmr and PUSH16/32/64rmr instructions from the assembly parser.
These all have a short form encoding that the assembler already prefers. Though that preference seems to only be based on order in the .td fie. Hiding the long form saves space in the table and prevents us from breaking the implicit order based priority.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334897
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Craig Topper [Sat, 16 Jun 2018 23:25:47 +0000 (23:25 +0000)]
[X86] Fix an inconsistency between AVX512 and AVX/SSE version on a couple instructions.
VMOVPQIto64Zmr is not a 64-bit mode only instruction. But I don't know how to test this because VMOVPQIto64mr should always have priority over it in 32-bit mode since its only advantage is XMM16-XMM31 which aren't usable in 32-bit mode.
VMOVPQIto64Zrr is a 64-bit mode only instruction, but we don't need to explicitly mark it as such because it uses a GR64 register which won't parse in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334896
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Michael Zolotukhin [Sat, 16 Jun 2018 18:57:31 +0000 (18:57 +0000)]
CorrelatedValuePropagation: Preserve DT.
Summary:
We only modify CFG in a couple of places, and we can preserve DT there
with a little effort.
Reviewers: davide, vsk
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334895
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Florian Hahn [Sat, 16 Jun 2018 14:47:05 +0000 (14:47 +0000)]
[Dominators] Change getNode parameter type to const NodeT * (NFC).
DominatorTreeBase::getNode does not modify its parameter and this change
allows callers that only have access to const pointers to use it without
casting.
Reviewers: kuhar, dblaikie, chandlerc
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D48231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334892
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Benjamin Kramer [Sat, 16 Jun 2018 13:37:52 +0000 (13:37 +0000)]
Fix namespaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334890
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Florian Hahn [Sat, 16 Jun 2018 13:00:33 +0000 (13:00 +0000)]
Revert r334887, as GCC 4.8 does not have is_trivially_copy_constructible & co
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334889
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Florian Hahn [Sat, 16 Jun 2018 12:50:32 +0000 (12:50 +0000)]
[SmallSet] Avoid using is_trivially_XXX<>::value which is C++17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334888
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Florian Hahn [Sat, 16 Jun 2018 12:36:19 +0000 (12:36 +0000)]
[SmallSet] Add SmallSetIterator.
This patch adds a simple const_iterator implementation for SmallSet by
delegating to either a SmallVector::const_iterator or
std::set::const_iterator, depending on which storage is used by the
SmallSet.
Reviewers: dblaikie, craig.topper
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D47942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334887
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Stanislav Mekhanoshin [Sat, 16 Jun 2018 03:46:59 +0000 (03:46 +0000)]
[AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc
This is the common case in the BE when we serialize condition and then
rematerialize it. Use either original or inverted condition.
Differential Revision: https://reviews.llvm.org/D48246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334882
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Nirav Dave [Sat, 16 Jun 2018 02:51:29 +0000 (02:51 +0000)]
Avoid needing to walk out legalization tables. NFCI.
Relanding after fixing expensive check from modifying tables.
To avoid redundant work, during DAG legalization we keep tables
mapping pre-legalized SDValues to post-legalized SDValues and a
SDValue-to-SDValue map to enable fast node replacements. However, as
the keys are nodes which may be reused it is possible that an entry in
a table refers to a now deleted node N (that should have been renamed
by the value replacement map) while a new node N' exists. If N' is
then replaced that entry would be wrong. Previously we avoided this by
when potentially violating this property, walking every table and
updating all node pointers. This is very expensive but hopefully rare
occurance.
This patch assigns each instance of a SDValue used in legalization a
unique id and uses these ids in the legalization tables. This avoids
any such aliasing issue, avoiding the full table search and allowing
more aggressive incremental table pruning.
In some cases this is a 1000x speedup to compilation.
Reviewers: jyknight, echristo, bogner, tra
Reviewed By: bogner
Subscribers: dberris, grandinj, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334880
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Justin Lebar [Sat, 16 Jun 2018 00:14:10 +0000 (00:14 +0000)]
Revert "[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV." -- breaks MSVC builds.
This reverts D48237.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334878
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Justin Lebar [Sat, 16 Jun 2018 00:13:57 +0000 (00:13 +0000)]
Revert "[SCEV] Simplify some flags expressions." -- dependent revision breaks MSVC builds.
This reverts D48238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334877
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Michael Berg [Sat, 16 Jun 2018 00:03:06 +0000 (00:03 +0000)]
Utilize new SDNode flag functionality to expand current support for fma
Summary: This patch originated from D47388 and is a proper subset of the originating changes, containing only the fmf optimization guard extensions.
Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar, rampitec, nhaehnle, nemanjai
Reviewed By: rampitec, nhaehnle
Subscribers: tpr, nemanjai, wdng
Differential Revision: https://reviews.llvm.org/D47918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334876
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Justin Lebar [Fri, 15 Jun 2018 23:52:11 +0000 (23:52 +0000)]
[SCEV] Simplify some flags expressions.
Summary:
Sending for presubmit review out of an abundance of caution; it would be
bad to mess this up.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334875
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Justin Lebar [Fri, 15 Jun 2018 23:51:57 +0000 (23:51 +0000)]
[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV.
Summary:
Obviates the need for mask/clear/setFlags helpers.
There are some expressions here which can be simplified, but to keep
this easy to review, I have not simplified them in this patch.
No functional change.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334874
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