OSDN Git Service
Simon Pilgrim [Sun, 23 Apr 2017 20:05:21 +0000 (20:05 +0000)]
[X86][SSE] Add scheduling latency/throughput tests for (most) SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301137
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Simon Pilgrim [Sun, 23 Apr 2017 19:56:49 +0000 (19:56 +0000)]
[X86][SSE] Add missing scheduling latency/throughput test for PINSRW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301136
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Xin Tong [Sun, 23 Apr 2017 17:36:25 +0000 (17:36 +0000)]
Correct grammar. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301135
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Craig Topper [Sun, 23 Apr 2017 17:16:26 +0000 (17:16 +0000)]
[APInt] Make clearUnusedBits branch free.
This makes the WordBits calculation calculate a value between 1 and 64 for the number of bits in the last word. Previously if the BitWidth was a multiple of 64 bits the WordBits value was 0 and we had to bail out early to avoid an undefined shift. Now with a value of 64 we no longer have an undefined shift issue.
This shows a 15-16k reduction in the size of the opt binary on my local x86-64 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301134
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Craig Topper [Sun, 23 Apr 2017 17:16:24 +0000 (17:16 +0000)]
[APInt] In sext single word case, use SignExtend64 and let the APInt constructor mask off any excess bits.
The current code is trying to be clever with shifts to avoid needing to clear unused bits. But it looks like the compiler is unable to optimize out the unused bit handling in the APInt constructor. Given this its better to just use SignExtend64 and have more readable code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301133
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Sanjay Patel [Sun, 23 Apr 2017 16:37:36 +0000 (16:37 +0000)]
[InstCombine] add tests for or-to-xor; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301131
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Sanjay Patel [Sun, 23 Apr 2017 16:03:00 +0000 (16:03 +0000)]
[InstCombine] add pattern matches for commuted variants of xor-to-xor
There's probably some better way to write this that eliminates the
code duplication without hurting readability, but at least this
eliminates the logic holes and is hopefully slightly more efficient
than creating new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301129
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Sanjay Patel [Sun, 23 Apr 2017 14:51:03 +0000 (14:51 +0000)]
[InstCombine] add tests for xor-to-xor; NFC
Besides missing 2 commuted patterns, the way we handle these folds is inefficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301128
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Simon Pilgrim [Sun, 23 Apr 2017 14:01:55 +0000 (14:01 +0000)]
[X86][SSE] Add scheduling latency/throughput tests for SSSE3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301127
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Simon Pilgrim [Sun, 23 Apr 2017 13:59:29 +0000 (13:59 +0000)]
[X86][SSE] Add scheduling latency/throughput tests for SSE3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301126
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Sanjay Patel [Sun, 23 Apr 2017 13:37:05 +0000 (13:37 +0000)]
[InstCombine] add tests for add-to-xor commuted variants; NFC
1 out of the 4 tests commuted the operands, so there's an asymmetry
somewhere under this in how we handle these transforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301125
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Renato Golin [Sun, 23 Apr 2017 12:15:30 +0000 (12:15 +0000)]
Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."
This reverts commit r301105, 4, 3 and 1, as a follow up of the previous
revert, which broke even more bots.
For reference:
Revert "[APInt] Use operator<<= where possible. NFC"
Revert "[APInt] Use operator<<= instead of shl where possible. NFC"
Revert "[APInt] Use ashInPlace where possible."
PR32754.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301111
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Renato Golin [Sun, 23 Apr 2017 12:02:07 +0000 (12:02 +0000)]
Revert "[APInt] Add ashrInPlace method and implement ashr using it. Also fix a bug in the shift by BitWidth handling."
This reverts commit r301094, as it broke all ARM self-hosting bots.
PR32754.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301110
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Ayman Musa [Sun, 23 Apr 2017 08:28:42 +0000 (08:28 +0000)]
[X86][MPX] Add load & store instructions of bnd values to getLoadStoreRegOpcode function.
This is needed for a follow up patch that generates the memory folding tables.
Differential Revision: https://reviews.llvm.org/D32232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301109
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Ayman Musa [Sun, 23 Apr 2017 07:41:40 +0000 (07:41 +0000)]
[X86] Convert test checks to generated checks of update_llc_test_checks.py. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301107
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Artyom Skrobov [Sun, 23 Apr 2017 06:58:08 +0000 (06:58 +0000)]
[ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs
Summary:
D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units.
Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC.
Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin
Reviewed By: javed.absar
Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB
Differential Revision: https://reviews.llvm.org/D31081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301106
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Craig Topper [Sun, 23 Apr 2017 06:41:11 +0000 (06:41 +0000)]
[APInt] Fix a few places that use APInt::getRawData to operate within the normal API.
getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail.
This patch fixes a few of the easy cases by using truncate, extract, or a rotate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301105
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Craig Topper [Sun, 23 Apr 2017 05:43:02 +0000 (05:43 +0000)]
[APInt] Use operator<<= where possible. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301104
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Craig Topper [Sun, 23 Apr 2017 05:18:31 +0000 (05:18 +0000)]
[APInt] Use operator<<= instead of shl where possible. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301103
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Davide Italiano [Sun, 23 Apr 2017 04:49:34 +0000 (04:49 +0000)]
[ThinLTO/Summary] Rename anonymous globals as last action ...
... in the per-TU -O0 pipeline.
The problem is that there could be passes registered using
`addExtensionsToPM()` introducing unnamed globals.
Asan is an example, but there may be others. Building cppcheck
with `-flto=thin` and `-fsanitize=address` triggers an assertion
while we're reading bitcode (in lib/LTO), as the BitcodeReader
assumes there are no unnamed globals (because the namer has run).
Unfortunately I wasn't able to find an easy way to test this.
I added a comment in the hope nobody moves this again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301102
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Craig Topper [Sun, 23 Apr 2017 03:45:59 +0000 (03:45 +0000)]
[APInt] Use ashInPlace where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301101
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Adrian Prantl [Sun, 23 Apr 2017 00:44:40 +0000 (00:44 +0000)]
Revert "Use DW_OP_stack_value when reconstructing variable values with arithmetic."
This reverts commit r301093 while investigating stage2 bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301099
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Jonathan Roelofs [Sat, 22 Apr 2017 23:43:44 +0000 (23:43 +0000)]
Fix testcase: s/CHECKNEXT/CHECK-NEXT/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301098
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Sanjay Patel [Sat, 22 Apr 2017 23:36:47 +0000 (23:36 +0000)]
[InstCombine] clean up tests and regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301097
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Craig Topper [Sat, 22 Apr 2017 22:00:03 +0000 (22:00 +0000)]
[APInt] Add ashrInPlace method and implement ashr using it. Also fix a bug in the shift by BitWidth handling.
For single word, shift by BitWidth was always returning 0, but for multiword it was based on original sign. Now single word matches multi word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301094
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Adrian Prantl [Sat, 22 Apr 2017 20:54:06 +0000 (20:54 +0000)]
Use DW_OP_stack_value when reconstructing variable values with arithmetic.
When the location description of a source variable involves arithmetic
on the value itself, it needs to be marked with DW_OP_stack_value since it
is not describing the variable's location, but rather its value.
This is a follow-up to r297971 and fixes the source testcase quoted in
the comment in debuginfo-dce.ll.
rdar://problem/
30725338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301093
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Simon Pilgrim [Sat, 22 Apr 2017 20:13:58 +0000 (20:13 +0000)]
[X86] Regenerate TLS tests
Use the correct check prefix for X86/X32/X64 target types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301092
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Craig Topper [Sat, 22 Apr 2017 19:59:11 +0000 (19:59 +0000)]
[APInt] Remove unnecessary min with BitWidth from countTrailingOnesSlowCase.
The unused upper bits are guaranteed to be 0 so we don't need to worry about accidentally counting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301091
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Xinliang David Li [Sat, 22 Apr 2017 19:24:19 +0000 (19:24 +0000)]
[PartialInlining] Using existing hasAddressTaken interface to legality check/NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301090
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Sanjay Patel [Sat, 22 Apr 2017 18:05:35 +0000 (18:05 +0000)]
[InstCombine] use 'match' to reduce code; NFCI
The later uses of dyn_castNotVal in this block are either
incomplete (doesn't handle vector constants) or overstepping
(shouldn't handle constants at all), but this first use is
just unnecessary. 'I' is obviously not a constant, and it
can't be a not-of-a-not because that would already be
instsimplified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301088
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Kamil Rytarowski [Sat, 22 Apr 2017 16:11:23 +0000 (16:11 +0000)]
Update documentation for the NetBSD target
LLVM is known to work on NetBSD x86 32-bit and 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301081
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Daniel Sanders [Sat, 22 Apr 2017 15:53:21 +0000 (15:53 +0000)]
[globalisel][tablegen] Add support for RegisterOperand.
Summary:
It functions just like RegisterClass except that the class is obtained
from a field.
Depends on D31761.
Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar
Reviewed By: ab
Subscribers: dberris, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D32229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301080
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Daniel Sanders [Sat, 22 Apr 2017 15:11:04 +0000 (15:11 +0000)]
[globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility.
Summary:
Some targets need to be able to do more complex rendering than just adding an
operand or two to an instruction. For example, it may need to insert an
instruction to extract a subreg first, or it may need to perform an operation
on the operand.
In SelectionDAG, targets would create SDNode's to achieve the desired effect
during the complex pattern predicate. This worked because SelectionDAG had a
form of garbage collection that would take care of SDNode's that were created
but not used due to a later predicate rejecting a match. This doesn't translate
well to GlobalISel and the churn was wasteful.
The API changes in this patch enable GlobalISel to accomplish the same thing
without the waste. The API is now:
InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const;
where Root is the root of the match. The return value can be omitted to
indicate that the predicate failed to match, or a function with the signature
ComplexRendererFn can be returned. For example:
return OptionalComplexRendererFn(
[=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); });
adds two immediate operands to the rendered instruction. Immed and ShVal are
captured from the predicate function.
As an added bonus, this also reduces the amount of information we need to
provide to GIComplexOperandMatcher.
Depends on D31418
Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar
Reviewed By: ab
Subscribers: dberris, kristof.beyls, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D31761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301079
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Daniel Sanders [Sat, 22 Apr 2017 14:31:28 +0000 (14:31 +0000)]
[globalisel][tablegen] Fix PR32733 by checking which instruction operands belong to.
canMutate() was returning true when the operands were all in the same order as
the matched instruction. However, it wasn't checking the operands were actually
on that instruction. This worked when we could only match a single instruction
but the addition of nested instruction matching led to cases where the operands
could be split across multiple instructions. canMutate() now returns false if
operands belong to instructions other than the root of the match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301077
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David Blaikie [Sat, 22 Apr 2017 08:17:39 +0000 (08:17 +0000)]
Fix test to handle .rel and .rela sections (& to actually specify the target architecture as X86)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301073
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David Blaikie [Sat, 22 Apr 2017 07:53:44 +0000 (07:53 +0000)]
Avoid using relocations for ref_addr in .dwo files
In dwo files the fixed offset can be used - if the dwos are linked into
a dwp, the dwo consumer must use the dwp tables to find out where the
original range of the debug_info was and resolve the "section relative"
value relative to that original range - effectively
avoiding/reimplementing the relocation handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301072
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David Blaikie [Sat, 22 Apr 2017 07:53:40 +0000 (07:53 +0000)]
Fix test from polluting the source tree
(though this seems like a "does this not crash" test - which isn't very
good. Should be fixed)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301071
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Artur Pilipenko [Sat, 22 Apr 2017 07:24:52 +0000 (07:24 +0000)]
Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029
The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The patch didn't expect that fadd can be on vectors not necessarily scalars. Add vector support along with the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301070
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Craig Topper [Sat, 22 Apr 2017 06:31:36 +0000 (06:31 +0000)]
[APInt] Add WORD_MAX constant and use it instead of UINT64_MAX. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301069
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David Blaikie [Sat, 22 Apr 2017 02:18:00 +0000 (02:18 +0000)]
Remove the unnecessary virtual dtor from the DIEUnit hierarchy (in favor of protected dtor in the base, final derived classes with public non-virtual dtors)
These objects are never polymorphically owned/destroyed, so the virtual
dtor was unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301068
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Matt Arsenault [Fri, 21 Apr 2017 23:54:12 +0000 (23:54 +0000)]
LowerSwitch: Fix producing invalid IR on unreachable code
If a switch was in an unreachable block that branched
to a block with a phi, it would leave phis with missing
predecessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301064
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David Blaikie [Fri, 21 Apr 2017 23:35:26 +0000 (23:35 +0000)]
Move Split DWARF handling to an MC option/command line argument rather than using metadata
Since Split DWARF needs to name the actual .dwo file that is generated,
it can't be known at the time the llvm::Module is produced as it may be
merged with other Modules before the object is generated and that object
may be generated with any name.
By passing the Split DWARF file name when LLVM is producing object code
the .dwo file name in the object file can match correctly.
The support for Split DWARF for implicit modules remains the same -
using metadata to store the dwo name and dwo id so that potentially
multiple skeleton CUs referring to different dwo files can be generated
from one llvm::Module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301062
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Kuba Mracek [Fri, 21 Apr 2017 23:28:01 +0000 (23:28 +0000)]
Fixup for r301054: Use an explicit constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301061
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Easwaran Raman [Fri, 21 Apr 2017 23:12:16 +0000 (23:12 +0000)]
Remove a repeated comment line. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301059
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Kuba Mracek [Fri, 21 Apr 2017 22:58:55 +0000 (22:58 +0000)]
Fixup for r301054: Only use __attribute__((no_sanitize("memory"))) when it's available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301058
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Matthias Braun [Fri, 21 Apr 2017 22:42:08 +0000 (22:42 +0000)]
AArch64FrameLowering: Check if the ExtraCSSpill register is actually unused
The code assumed that when saving an additional CSR register
(ExtraCSSpill==true) we would have a free register throughout the
function. This was not true if this CSR register is also used to pass
values as in the swiftself case.
rdar://
31451816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301057
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Kuba Mracek [Fri, 21 Apr 2017 22:38:24 +0000 (22:38 +0000)]
[libFuzzer] Always build libFuzzer
There are two reasons why users might want to build libfuzzer:
- To fuzz LLVM itself
- To get the libFuzzer.a archive file, so that they can attach it to their code
This change always builds libfuzzer, and supports the second use case if the specified flag is set.
The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler.
Patch by George Karpenkov.
Differential Revision: https://reviews.llvm.org/D32096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301054
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Craig Topper [Fri, 21 Apr 2017 22:32:27 +0000 (22:32 +0000)]
[APSInt] Use APInt::compare and APInt::compareSigned to implement APSInt::compareValue
APInt just got compare methods that return -1, 0, or 1 instead of just having ult/slt and eq.
This patch uses these methods to implement APSInt::compareValues so that we don't have to call do an equal comparison and then possibly a second less than comparison.
Differential Revision: https://reviews.llvm.org/D32381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301053
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Craig Topper [Fri, 21 Apr 2017 22:30:06 +0000 (22:30 +0000)]
[APSInt] Make use of APInt's recently acquired in place lshr and shl capabilities in APSInt's >>= and <<= operators.
APInt hasn't acquired an in place ashr yet, but hopefully soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301052
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Adrian Prantl [Fri, 21 Apr 2017 22:13:55 +0000 (22:13 +0000)]
Add test coverage for mem2reg dbg.declare lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301050
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Eugene Zelenko [Fri, 21 Apr 2017 22:03:05 +0000 (22:03 +0000)]
[Object] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301049
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Hans Wennborg [Fri, 21 Apr 2017 21:48:41 +0000 (21:48 +0000)]
Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"
In addition to the original commit, tighten the condition for when to
pad empty functions to COFF Windows. This avoids running into problems
when targeting e.g. Win32 AMDGPU, which caused test failures when this
was committed initially.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301047
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Frederich Munch [Fri, 21 Apr 2017 21:39:50 +0000 (21:39 +0000)]
[Test commit] Remove extra newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301046
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Matt Arsenault [Fri, 21 Apr 2017 21:35:04 +0000 (21:35 +0000)]
InferAddressSpaces: Infer for just GEPs
Fixes leaving intermediate flat addressing computations
where a GEP instruction's source is a constant expression.
Still leaves behind a trivial addrspacecast + gep pair that
instcombine is able to handle, which ideally could be folded
here directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301044
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Xinliang David Li [Fri, 21 Apr 2017 21:20:56 +0000 (21:20 +0000)]
[PartialInliner] Partial inliner needs to check use kind before transformation
Differential Revision: https://reviews.llvm.org/D32373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301042
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Hans Wennborg [Fri, 21 Apr 2017 21:10:37 +0000 (21:10 +0000)]
Revert r301040 "X86: Don't emit zero-byte functions on Windows"
This broke almost all bots. Reverting while fixing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301041
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Hans Wennborg [Fri, 21 Apr 2017 20:58:12 +0000 (20:58 +0000)]
X86: Don't emit zero-byte functions on Windows
Empty functions can lead to duplicate entries in the Guard CF Function
Table of a binary due to multiple functions sharing the same RVA,
causing the kernel to refuse to load that binary.
We had a terrific bug due to this in Chromium.
It turns out we were already doing this for Mach-O in certain
situations. This patch expands the code for that in
AsmPrinter::EmitFunctionBody() and renames
TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it
seems it was used for not just Mach-O anyway.
Differential Revision: https://reviews.llvm.org/D32330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301040
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Zachary Turner [Fri, 21 Apr 2017 20:45:11 +0000 (20:45 +0000)]
Add a dependency from llvm/test to llvm-cvtres.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301038
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Tim Northover [Fri, 21 Apr 2017 20:36:08 +0000 (20:36 +0000)]
AArch64: add test for "fence singlethread"
Forgot a git add yesterday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301037
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Tim Northover [Fri, 21 Apr 2017 20:35:52 +0000 (20:35 +0000)]
ARM: make sure we use all entries in a vector before forming a vpaddl.
Otherwise there's some mismatch, and we'll either form an illegal type or an
illegal node.
Thanks to Eli Friedman for pointing out the problem with my original solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301036
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Sanjay Patel [Fri, 21 Apr 2017 20:29:17 +0000 (20:29 +0000)]
[InstCombine] revert r300977 and r301021
This can cause an inf-loop. Investigating...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301035
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Zachary Turner [Fri, 21 Apr 2017 20:18:43 +0000 (20:18 +0000)]
Fixed a type conversion error in BitVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301033
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Zachary Turner [Fri, 21 Apr 2017 20:12:08 +0000 (20:12 +0000)]
[BitVector] Make BitVector store an ArrayRef.
This makes certain operations on the underlying storage
easier since we have access to ArrayRef methods such as
drop_front, drop_back, slice, range-based for loops, etc.
Differential Revision: https://reviews.llvm.org/D32367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301031
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Adrian Prantl [Fri, 21 Apr 2017 20:06:41 +0000 (20:06 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301030
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:57:53 +0000 (19:57 +0000)]
AMDGPU/GFX9: Enable FastFMAF32
Differential Revision: https://reviews.llvm.org/D32363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301029
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:45:22 +0000 (19:45 +0000)]
AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)
Differential Revision: https://reviews.llvm.org/D32361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301028
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:35:05 +0000 (19:35 +0000)]
AMDGPU: Fix S_PACK_HH_B32_B16
- We really ought to zero out lower 16 bits
Differential Revision: https://reviews.llvm.org/D32356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301026
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Yaxun Liu [Fri, 21 Apr 2017 19:32:02 +0000 (19:32 +0000)]
[AMDGPU] Handle SI_MASKED_UNREACHABLE in instruction emitter
SI_MASKED_UNREACHABLE does not have machine instruction encoding.
It needs special handling in AMDGPUAsmPrinter::EmitInstruction like some
other pseudo instructions.
This patch fixes compilation failure of RadeonRays.
Differential Revision: https://reviews.llvm.org/D32364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301025
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Matthias Braun [Fri, 21 Apr 2017 19:26:45 +0000 (19:26 +0000)]
Revert "X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC"
It seems we have on situation in a sanitizer enable bootstrap build
where the return instruction has a frame index operand that does not
point to a fixed object and fails the assert added here.
This reverts commit r300923.
This reverts commit r300922.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301024
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:25:33 +0000 (19:25 +0000)]
AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormals
Differential Revision: https://reviews.llvm.org/D32085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301023
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Sanjay Patel [Fri, 21 Apr 2017 19:16:52 +0000 (19:16 +0000)]
[InstCombine] use isSubsetOf() for efficiency
C | ~D == -1
~(C | ~D) == 0
~C & D == 0
D & ~C == 0
D.isSubsetOf(C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301021
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Akira Hatanaka [Fri, 21 Apr 2017 18:53:12 +0000 (18:53 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
This recommits r300932 and r300930, which was causing dag-combine to
loop forever. The problem was that optimizeLogicalImm was returning
true even when there was no change to the immediate node (which happened
when the immediate was all zeros or ones), which caused dag-combine to
push and pop the same node to the work list over and over again without
making any progress.
This commit fixes the bug by returning false early in optimizeLogicalImm
if the immediate is all zeros or ones. Also, it changes the code to
compare the immediate with 0 or Mask rather than calling
countPopulation.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301019
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Artur Pilipenko [Fri, 21 Apr 2017 18:45:25 +0000 (18:45 +0000)]
[InstCombine] fadd double (sitofp x), y check that the promotion is valid
Doing these transformations check that the result of integer addition is representable in the FP type.
(fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst))
(fadd double (sitofp x), (sitofp y)) --> (sitofp (add int x, y))
This is a fix for https://bugs.llvm.org//show_bug.cgi?id=27036
Reviewed By: andrew.w.kaylor, scanon, spatel
Differential Revision: https://reviews.llvm.org/D31182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301018
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Kuba Mracek [Fri, 21 Apr 2017 18:19:56 +0000 (18:19 +0000)]
Fixup for r301007: Restrict the -D hack to Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301017
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Zachary Turner [Fri, 21 Apr 2017 18:07:46 +0000 (18:07 +0000)]
[BitVector] Add find_last() and find_last_unset().
Differential Revision: https://reviews.llvm.org/D32302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301014
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Kuba Mracek [Fri, 21 Apr 2017 18:02:22 +0000 (18:02 +0000)]
Revert r301010: Bot failures on Windows, NetBSD and even some old Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301012
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Kuba Mracek [Fri, 21 Apr 2017 17:47:44 +0000 (17:47 +0000)]
[libFuzzer] Always build libFuzzer
There are two reasons why users might want to build libfuzzer:
- To fuzz LLVM itself
- To get the libFuzzer.a archive file, so that they can attach it to their code
This change always builds libfuzzer, and supports the second use case if the specified flag is set.
The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler.
Patch by George Karpenkov.
Differential Revision: https://reviews.llvm.org/D32096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301010
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Kuba Mracek [Fri, 21 Apr 2017 17:39:50 +0000 (17:39 +0000)]
[libFuzzer] Changing thread_local to __thread in libFuzzer
Old Apple compilers do not support thread_local keyword. This patch adds -Dthread_local=__thread when the compiler doesn't support thread_local.
Differential Revision: https://reviews.llvm.org/D32312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301007
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Zachary Turner [Fri, 21 Apr 2017 17:37:31 +0000 (17:37 +0000)]
Add llvm-cvtres to LLVMBuild.txt
It wasn't getting picked up as an implicit project, so it wasn't
being built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301006
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Joel Jones [Fri, 21 Apr 2017 17:31:03 +0000 (17:31 +0000)]
[AArch64] Refactor instruction selection lowering for addresses. NFCI
Factor out the common code used for generating addresses into common
templated functions that call overloaded versions of a new function,
getTargetNode.
Tested with make check-llvm with targets AArch64.
Differential Revision: https://reviews.llvm.org/D32169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301005
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Zachary Turner [Fri, 21 Apr 2017 17:30:29 +0000 (17:30 +0000)]
Add empty shell of llvm-cvtres.
This marks the beginning of an effort to port remaining
MSVC toolchain miscellaneous utilities to all platforms.
Currently clang-cl shells out to certain additional tools
such as the IDL compiler, resource compiler, and a few
other tools, but as these tools are Windows-only it
limits the ability of clang to target Windows on other
platforms. having a full suite of these tools directly
in LLVM should eliminate this constraint.
The current implementation provides no actual functionality,
it is just an empty skeleton executable for the purposes
of making incremental changes.
Differential Revision: https://reviews.llvm.org/D32095
Patch by Eric Beckmann (ecbeckmann@google.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301004
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Tim Northover [Fri, 21 Apr 2017 17:21:59 +0000 (17:21 +0000)]
ARM: don't try to create an i8 -> i32 vpaddl.
DAG combine was mistakenly assuming that the step-up it was looking at was
always a doubling, but it can sometimes be a larger extension in which case
we'd crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301002
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Kuba Mracek [Fri, 21 Apr 2017 16:57:37 +0000 (16:57 +0000)]
[libFuzzer] Check for target(popcnt) capability before usage
Older compilers (e.g. LLVM 3.4) do not support the attribute target("popcnt").
In order to support those, this diff check the attribute support using the preprocessor.
Patch by George Karpenkov.
Differential Revision: https://reviews.llvm.org/D32311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300999
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Craig Topper [Fri, 21 Apr 2017 16:43:32 +0000 (16:43 +0000)]
[ValueTracking] Use APInt::setAllBits and APInt::intersects to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300997
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Craig Topper [Fri, 21 Apr 2017 16:13:15 +0000 (16:13 +0000)]
[APInt] Add compare/compareSigned methods that return -1, 0, 1. Reimplement slt/ult and friends using them
Currently sle and ule have to call slt/ult and eq to get the proper answer. This results in extra code for both calls and additional scans of multiword APInts.
This patch replaces slt/ult with a compareSigned/compare that can return -1, 0, or 1 so we can cover all the comparison functions with a single call.
While I was there I removed the activeBits calls and other checks at the start of the slow part of ult. Both of the activeBits calls potentially scan through each of the APInts separately. I can't imagine that's any better than just scanning them in parallel and doing the compares. Now we just share the code with tcCompare.
These changes seem to be good for about a 7-8k reduction on the size of the opt binary on my local x86-64 build.
Differential Revision: https://reviews.llvm.org/D32339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300995
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Juergen Ributzka [Fri, 21 Apr 2017 16:05:01 +0000 (16:05 +0000)]
Remove empty and unused header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300994
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Daniel Sanders [Fri, 21 Apr 2017 15:59:56 +0000 (15:59 +0000)]
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).
Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.
Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab
Reviewed By: rovka
Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D31418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300993
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Craig Topper [Fri, 21 Apr 2017 15:53:42 +0000 (15:53 +0000)]
[SimplifyCFG] Fix the determination of PostBB in conditional store merging to handle the targets on the second branch being commuted
Currently we choose PostBB as the single successor of QFB, but its possible that QTB's single successor is QFB which would make QFB the correct choice.
Differential Revision: https://reviews.llvm.org/D32323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300992
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Wei Mi [Fri, 21 Apr 2017 15:50:16 +0000 (15:50 +0000)]
[ConstHoisting] Add BFI in constanthoisting pass and select the best insertion
places based on it.
Existing constant hoisting pass will merge a group of contants in a small range
and hoist the const materialization code to the common dominator of their uses.
However, if the uses are all in cold pathes, existing implementation may hoist
the materialization code from cold pathes to a hot place. This may hurt performance.
The patch introduces BFI to the pass and selects the best insertion places based
on it.
The change is controlled by an option consthoist-with-block-frequency which is
off by default for now.
Differential Revision: https://reviews.llvm.org/D28962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300989
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Chad Rosier [Fri, 21 Apr 2017 14:58:32 +0000 (14:58 +0000)]
[AArch64][Falkor] Refine modeling of store-release exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300987
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Joel Jones [Fri, 21 Apr 2017 14:49:27 +0000 (14:49 +0000)]
[Mips] Document Mips Backend Relocation Principles
This revision documents the combination of C++ and table-gen code that
handles relocations and addresses.
Thanks for Simon Dardis for the careful reviews.
Differential Revision: https://reviews.llvm.org/D31628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300986
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Chad Rosier [Fri, 21 Apr 2017 14:33:13 +0000 (14:33 +0000)]
[AArch64][Falkor] Refine resource needs of STRQ with register offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300984
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Matthew Simpson [Fri, 21 Apr 2017 14:14:54 +0000 (14:14 +0000)]
[LV] Model if-converted phi node costs
Phi nodes in non-header blocks are converted to select instructions after
if-conversion. This patch updates the cost model to account for the selects.
Differential Revision: https://reviews.llvm.org/D31906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300980
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Daniel Sanders [Fri, 21 Apr 2017 14:09:20 +0000 (14:09 +0000)]
Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I
haven't worked out why. Reverting to make it green while I figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300978
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Sanjay Patel [Fri, 21 Apr 2017 14:03:54 +0000 (14:03 +0000)]
[InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)
This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706
Differential Revision: https://reviews.llvm.org/D32255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300977
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Chad Rosier [Fri, 21 Apr 2017 13:55:41 +0000 (13:55 +0000)]
[AArch64][Falkor] Refine loads/stores that require an extra LD pipe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300976
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Chad Rosier [Fri, 21 Apr 2017 13:37:01 +0000 (13:37 +0000)]
[AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300975
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Chad Rosier [Fri, 21 Apr 2017 13:36:57 +0000 (13:36 +0000)]
[AArch64] Fix a few missed pre/post-inc in Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300974
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Diana Picus [Fri, 21 Apr 2017 13:16:50 +0000 (13:16 +0000)]
[ARM] GlobalISel: Add support for G_TRUNC
Select them as copies. We only select if both the source and the
destination are on the same register bank, so this shouldn't cause any
trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300971
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Daniel Sanders [Fri, 21 Apr 2017 12:51:43 +0000 (12:51 +0000)]
[globalisel][tablegen] Try again to fix builds on old MSVC's after r300964
This should fix llvm-clang-x86_64-expensive-checks-win
I reproduced the error using the following code:
namespace llvm {
// Moving this out of the llvm namespace fixes the error.
template<unsigned NumBits> class PredicateBitsetImpl {};
}
namespace {
const unsigned MAX_SUBTARGET_PREDICATES = 11;
// This works on Clang but is broken on MSVC
// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
// Some versions emit a syntax error here ("error C2061: syntax error: identifier
// 'PredicateBitsetImpl'") but others accept it and only emit the C3646 below.
//
// This works on Clang and MSVC
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
class Foo {
private:
PredicateBitset A; // error C3646: 'A': unknown override specifier
};
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300970
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