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Sanjay Patel [Sat, 26 Nov 2016 15:01:59 +0000 (15:01 +0000)]
add optional param to copy metadata when creating selects; NFC
There are other spots where we can use this; we're currently dropping
metadata in some places, and there are proposed changes where we will
want to propagate metadata.
IRBuilder's CreateSelect() already has a parameter like this, so this
change makes the regular 'Create' API line up with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287976
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Craig Topper [Sat, 26 Nov 2016 08:21:52 +0000 (08:21 +0000)]
[AVX-512] Add unmasked EVEX vpmovzx/sx instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287975
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Craig Topper [Sat, 26 Nov 2016 08:21:48 +0000 (08:21 +0000)]
[AVX-512] Add masked 128/256-bit integer add/sub instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287974
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Craig Topper [Sat, 26 Nov 2016 07:21:00 +0000 (07:21 +0000)]
[AVX-512] Add masked 512-bit integer add/sub instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287972
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Craig Topper [Sat, 26 Nov 2016 07:20:57 +0000 (07:20 +0000)]
[AVX-512] Teach LowerFormalArguments to use the extended register class when available. Fix the avx512vl stack folding tests to clobber more registers or otherwise they use xmm16 after this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287971
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Craig Topper [Sat, 26 Nov 2016 07:20:53 +0000 (07:20 +0000)]
[AVX-512] Add VLX versions of VDIVPD/PS and VMULPD/PS to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287970
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Tom Stellard [Sat, 26 Nov 2016 02:26:04 +0000 (02:26 +0000)]
AMDGPU/SI: Use float as the operand type for amdgcn.interp intrinsics
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287962
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Craig Topper [Sat, 26 Nov 2016 02:14:00 +0000 (02:14 +0000)]
[X86][XOP] Add a reversed reg/reg form for VPROT instructions.
The W bit distinquishes which operand is the memory operand. But if the mod bits are 3 then the memory operand is a register and there are two possible encodings. We already did this correctly for several other XOP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287961
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Craig Topper [Sat, 26 Nov 2016 02:13:58 +0000 (02:13 +0000)]
[X86] Add SSE, AVX, and AVX2 version of MOVDQU to the load/store folding tables for consistency.
Not sure this is truly needed but we had the floating point equivalents, the aligned equivalents, and the EVEX equivalents. So this just makes it complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287960
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Dylan McKay [Sat, 26 Nov 2016 01:07:32 +0000 (01:07 +0000)]
Un-XFAIL an AVR CodeGen test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287958
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Craig Topper [Fri, 25 Nov 2016 23:21:34 +0000 (23:21 +0000)]
[AVX-512] Put the AVX-512 sections of the load folding tables into mostly alphabetical order. This is consistent with the older sections of the table. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287956
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David Majnemer [Fri, 25 Nov 2016 22:35:09 +0000 (22:35 +0000)]
Replace some callers of setTailCall with setTailCallKind
We were a little sloppy with adding tailcall markers. Be more
consistent by using setTailCallKind instead of setTailCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287955
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Sanjay Patel [Fri, 25 Nov 2016 21:12:39 +0000 (21:12 +0000)]
[SimplifyCFG] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287954
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Sanjay Patel [Fri, 25 Nov 2016 21:07:13 +0000 (21:07 +0000)]
[SimplifyCFG] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287953
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Marek Olsak [Fri, 25 Nov 2016 17:37:09 +0000 (17:37 +0000)]
AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
suggested as a better solution by Matt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287942
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Simon Pilgrim [Fri, 25 Nov 2016 17:25:21 +0000 (17:25 +0000)]
Use SDValue helpers instead of explicitly going via SDValue::getNode(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287941
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Simon Pilgrim [Fri, 25 Nov 2016 17:19:53 +0000 (17:19 +0000)]
Use SDValue helper instead of explicitly going via SDValue::getNode(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287940
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Craig Topper [Fri, 25 Nov 2016 16:48:05 +0000 (16:48 +0000)]
[AVX-512] Add support for changing VSHUFF64x2 to VSHUFF32x4 when its feeding a vselect with 32-bit element size.
Summary:
Shuffle lowering may have widened the element size of a i32 shuffle to i64 before selecting X86ISD::SHUF128. If this shuffle was used by a vselect this can prevent us from selecting masked operations.
This patch detects this and changes the element size to match the vselect.
I don't handle changing integer to floating point or vice versa as its not clear if its better to push such a bitcast to the inputs of the shuffle or to the user of the vselect. So I'm ignoring that case for now.
Reviewers: delena, zvi, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287939
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Craig Topper [Fri, 25 Nov 2016 16:33:53 +0000 (16:33 +0000)]
[AVX-512] Add VPERMT2* and VPERMI2* instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287937
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Marek Olsak [Fri, 25 Nov 2016 16:03:34 +0000 (16:03 +0000)]
Revert "AMDGPU: Implement SGPR spilling with scalar stores"
This reverts commit
4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287936
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Marek Olsak [Fri, 25 Nov 2016 16:03:27 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix MMO when splitting spill"
This reverts commit
79d4f8b8b1ce430c3d5dac4fc72a9eebaed24fe1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287935
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Marek Olsak [Fri, 25 Nov 2016 16:03:22 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix adding extra implicit def of register"
This reverts commit
e834ce5976567575621901fb967b8018b9916d71.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287934
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Marek Olsak [Fri, 25 Nov 2016 16:03:19 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix not setting kill flag on temp reg when spilling"
This reverts commit
057bbbe4ae170247ba37f08f2e70ef185267d1bb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287933
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Marek Olsak [Fri, 25 Nov 2016 16:03:15 +0000 (16:03 +0000)]
Revert "AMDGPU: Make m0 unallocatable"
This reverts commit
124ad83dae04514f943902446520c859adee0e96.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287932
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Marek Olsak [Fri, 25 Nov 2016 16:03:06 +0000 (16:03 +0000)]
Revert "AMDGPU: Remove m0 spilling code"
This reverts commit
f18de36554eb22416f8ba58e094e0272523a4301.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287931
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Marek Olsak [Fri, 25 Nov 2016 16:03:02 +0000 (16:03 +0000)]
Revert "AMDGPU: Preserve m0 value when spilling"
This reverts commit
a5a179ffd94fd4136df461ec76fb30f04afa87ce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287930
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Simon Pilgrim [Fri, 25 Nov 2016 15:07:15 +0000 (15:07 +0000)]
[X86][SSE] Added knownbits through bitcast test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287928
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Abhilash Bhandari [Fri, 25 Nov 2016 14:07:44 +0000 (14:07 +0000)]
[Loop Unswitch] Patch to selective unswitch only the reachable branch instructions.
Summary:
The iterative algorithm for Loop Unswitching may render some of the branches unreachable in the unswitched loops.
Given the exponential nature of the algorithm, this is quite an overhead.
This patch fixes this problem by selectively unswitching only those branches within a loop that are reachable from the loop header.
Reviewers: Michael Zolothukin, Anna Thomas, Weiming Zhao.
Subscribers: llvm-commits.
Differential Revision: http://reviews.llvm.org/D26299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287925
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Simon Pilgrim [Fri, 25 Nov 2016 11:10:43 +0000 (11:10 +0000)]
[X86][SSE] Added v16i8 shuffle test case from PR31151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287919
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Simon Dardis [Fri, 25 Nov 2016 11:06:43 +0000 (11:06 +0000)]
[mips] Correct jal expansion for local symbols in .local directives.
This patch corrects the behaviour of code such as:
.local foo
jal foo
foo:
to use the correct jal expansion when writing ELF files.
Patch by: Daniel Sanders
Reviewers: zoran.jovanovic, seanbruno, vkalintiris
Differential Revision: https://reviews.llvm.org/D24722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287918
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Craig Topper [Fri, 25 Nov 2016 02:29:24 +0000 (02:29 +0000)]
[X86] Invert an 'if' and early out to fix a weird indentation. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287909
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Craig Topper [Fri, 25 Nov 2016 02:29:21 +0000 (02:29 +0000)]
[X86] Size a SmallVector to the worst case mask size for a 512-bit shuffle. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287908
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Kuba Mracek [Thu, 24 Nov 2016 22:50:22 +0000 (22:50 +0000)]
Add "compiler-rt", "libcxx" and "libcxxabi" to svn:ignore under projects/
Differential Revision: https://reviews.llvm.org/D27069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287905
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Craig Topper [Thu, 24 Nov 2016 21:48:52 +0000 (21:48 +0000)]
[DAGCombine] Teach DAG combine that if both inputs of a vselect are the same, then the condition doesn't matter and the vselect can be removed.
Selects with scalar condition already handle this correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287904
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Craig Topper [Thu, 24 Nov 2016 21:48:50 +0000 (21:48 +0000)]
[X86] Modify two tests that passed undef to both sides of a vselect to instead pass unique values.
I'd like to teach DAG combine to remove vselects where both sides are identical and these tests were in the way of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287903
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Serge Rogatch [Thu, 24 Nov 2016 18:51:47 +0000 (18:51 +0000)]
Test commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287898
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Craig Topper [Thu, 24 Nov 2016 18:24:46 +0000 (18:24 +0000)]
[AVX-512] Add tests demonstrating failure to generated masked instructions for VSHUFF32x4 and VSHUFI32x4 due to shuffle lowering widening elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287897
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Abhilash Bhandari [Thu, 24 Nov 2016 15:40:19 +0000 (15:40 +0000)]
Test Commit, removing a blank line in CREDITS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287891
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Simon Pilgrim [Thu, 24 Nov 2016 15:24:47 +0000 (15:24 +0000)]
Fix unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287889
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Benjamin Kramer [Thu, 24 Nov 2016 15:17:39 +0000 (15:17 +0000)]
[X86] Don't round trip a unique_ptr through a raw pointer for assignment.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287888
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Simon Pilgrim [Thu, 24 Nov 2016 15:12:56 +0000 (15:12 +0000)]
[X86][SSE] Improve UINT_TO_FP v2i32 -> v2f64
Vectorize UINT_TO_FP v2i32 -> v2f64 instead of scalarization (albeit still on the SIMD unit).
The codegen matches that generated by legalization (and is in fact used by AVX for UINT_TO_FP v4i32 -> v4f64), but has to be done in the x86 backend to account for legalization via 4i32.
Differential Revision: https://reviews.llvm.org/D26938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287886
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Simon Pilgrim [Thu, 24 Nov 2016 14:46:55 +0000 (14:46 +0000)]
[X86][AVX512] Add support for v2i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets
Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287882
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Simon Pilgrim [Thu, 24 Nov 2016 14:02:30 +0000 (14:02 +0000)]
[X86][AVX512DQVL] Add awareness of vcvtqq2ps and vcvtuqq2ps implicit zeroing of upper 64-bits of xmm result
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287878
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Simon Pilgrim [Thu, 24 Nov 2016 13:38:59 +0000 (13:38 +0000)]
[X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287877
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Simon Pilgrim [Thu, 24 Nov 2016 13:26:51 +0000 (13:26 +0000)]
[X86][AVX512DQVL] Add v2i64 -> v2f32 + zero codegen tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287876
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Nikolai Bozhenov [Thu, 24 Nov 2016 13:23:35 +0000 (13:23 +0000)]
[x86] Fixing PR28755 by precomputing the address used in CMPXCHG8B
The bug arises during register allocation on i686 for
CMPXCHG8B instruction when base pointer is needed. CMPXCHG8B
needs 4 implicit registers (EAX, EBX, ECX, EDX) and a memory address,
plus ESI is reserved as the base pointer. With such constraints the only
way register allocator would do its job successfully is when the addressing
mode of the instruction requires only one register. If that is not the case
- we are emitting additional LEA instruction to compute the address.
It fixes PR28755.
Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>
Differential Revision: https://reviews.llvm.org/D25088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287875
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Nikolai Bozhenov [Thu, 24 Nov 2016 13:15:49 +0000 (13:15 +0000)]
[x86] Minor refactoring of X86TargetLowering::EmitInstrWithCustomInserter
Move the definitions of three variables out of the switch.
Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>
Differential Revision: https://reviews.llvm.org/D25192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287874
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Nikolai Bozhenov [Thu, 24 Nov 2016 13:05:43 +0000 (13:05 +0000)]
[x86] Rewrite getAddressFromInstr helper function
- It does not modify the input instruction
- Second operand of any address is always an Index Register,
make sure we actually check for that, instead of a check for
an immediate value
Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>
Differential Revision: https://reviews.llvm.org/D24938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287873
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Dylan McKay [Thu, 24 Nov 2016 12:38:54 +0000 (12:38 +0000)]
[AVR] Mark the 'select-must-add-unconditional-jump' test as 'XFAIL'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287871
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Simon Pilgrim [Thu, 24 Nov 2016 12:13:46 +0000 (12:13 +0000)]
[X86] Generalize CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes. NFCI
Replace the CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes with general versions.
This is an initial step towards similar FP_TO_SINT/FP_TO_UINT and SINT_TO_FP/UINT_TO_FP lowering to AVX512 CVTTPS2QQ/CVTTPS2UQQ and CVTQQ2PS/CVTUQQ2PS with illegal types.
Differential Revision: https://reviews.llvm.org/D27072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287870
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Malcolm Parsons [Thu, 24 Nov 2016 08:54:05 +0000 (08:54 +0000)]
[CommandLine] Remove redundant initializers for StringRef members
Summary: The default constructor for a StringRef stores an empty string.
Reviewers: beanz, zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287857
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Jacob Baungard Hansen [Thu, 24 Nov 2016 08:53:28 +0000 (08:53 +0000)]
TableGen: Allow signed immediates for instruction aliases
Patch by Daniel Cederman.
Reviewers: stoklund, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D27046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287856
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Craig Topper [Thu, 24 Nov 2016 05:36:50 +0000 (05:36 +0000)]
[AVX-512] Fix some mask shuffle tests to actually test the case they were supposed to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287854
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Craig Topper [Thu, 24 Nov 2016 05:36:47 +0000 (05:36 +0000)]
[AVX-512] Move a 16 x float shuffle test to the v16 test file and add an integer variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287853
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Peter Collingbourne [Thu, 24 Nov 2016 01:13:09 +0000 (01:13 +0000)]
Object: Add IRObjectFile::getTargetTriple().
This lets us remove a use of IRObjectFile::getModule() in llvm-nm.
Differential Revision: https://reviews.llvm.org/D27074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287846
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Peter Collingbourne [Thu, 24 Nov 2016 00:41:05 +0000 (00:41 +0000)]
Object: Simplify the IRObjectFile symbol iterator implementation.
Change the IRObjectFile symbol iterator to be a pointer into a vector of
PointerUnions representing either IR symbols or asm symbols.
This change is in preparation for a future change for supporting multiple
modules in an IRObjectFile. Although it causes an increase in memory
consumption, we can deal with that issue separately by introducing a bitcode
symbol table.
Differential Revision: https://reviews.llvm.org/D26928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287845
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Matt Arsenault [Thu, 24 Nov 2016 00:26:50 +0000 (00:26 +0000)]
AMDGPU: Preserve m0 value when spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287844
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Matt Arsenault [Thu, 24 Nov 2016 00:26:47 +0000 (00:26 +0000)]
TRI: Add hook to pass scavenger during frame elimination
The scavenger was not passed if requiresFrameIndexScavenging was
enabled. I need to be able to test for the availability of an
unallocatable register here, so I can't create a virtual register for
it.
It might be better to just always use the scavenger and stop
creating virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287843
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Matt Arsenault [Thu, 24 Nov 2016 00:26:44 +0000 (00:26 +0000)]
AMDGPU: Remove m0 spilling code
Since m0 isn't allocatable it should never be spilled anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287842
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Matt Arsenault [Thu, 24 Nov 2016 00:26:40 +0000 (00:26 +0000)]
AMDGPU: Make m0 unallocatable
m0 may need to be written for spill code, so
we don't want general code uses relying on the
value stored in it.
This introduces a few code quality regressions where copies
from m0 are not coalesced into copies of a copy of m0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287841
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Davide Italiano [Thu, 24 Nov 2016 00:23:09 +0000 (00:23 +0000)]
[lib/LTO] Rename few instances of Lto to LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287840
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Greg Clayton [Wed, 23 Nov 2016 23:30:37 +0000 (23:30 +0000)]
Rely on a single DWARF version instead of having two copies
This patch makes AsmPrinter less reliant on DwarfDebug by relying on the DWARF version in the AsmPrinter's MCStreamer's MCContext. This allows us to remove the redundant DWARF version from DwarfDebug. It also lets us change code that used to access the AsmPrinter's DwarfDebug just to get to the DWARF version by changing the DWARF version accessor on AsmPrinter so that it grabs the version from its MCStreamer's MCContext.
Differential Revision: https://reviews.llvm.org/D27032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287839
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Eugene Zelenko [Wed, 23 Nov 2016 23:16:32 +0000 (23:16 +0000)]
[DebugInfo] Fix some Clang-tidy modernize-use-default and Include What You Use warnings; other minor fixes (NFC).
Per Zachary Turner and Mehdi Amini suggestion to make only post-commit reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287838
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Simon Pilgrim [Wed, 23 Nov 2016 22:35:06 +0000 (22:35 +0000)]
[X86][SSE] Add awareness of (v)cvtpd2dq and vcvtpd2udq implicit zeroing of upper 64-bits of xmm result
We've already added the equivalent for (v)cvttpd2dq (rL284459) and vcvttpd2udq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287835
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Eugene Zelenko [Wed, 23 Nov 2016 22:25:16 +0000 (22:25 +0000)]
[IR] Fix some Clang-tidy modernize-use-default, modernize-use-equal-delete and Include What You Use warnings; other minor fixes (NFC).
Per Zachary Turner and Mehdi Amini suggestion to make only post-commit reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287834
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Nicolai Haehnle [Wed, 23 Nov 2016 22:14:20 +0000 (22:14 +0000)]
[SelectionDAG] Early-out in TargetLowering::expandMUL (NFC)
Summary: Reduce indentation level; preparation for D24956.
Reviewers: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287831
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Simon Pilgrim [Wed, 23 Nov 2016 22:01:50 +0000 (22:01 +0000)]
[X86][AVX512VL] Add v2f64 -> v2i32/v2f32 + zero codegen tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287821
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Matt Arsenault [Wed, 23 Nov 2016 21:51:07 +0000 (21:51 +0000)]
AMDGPU: Cleanup immediate folding code
Move code down to use, reorder to avoid hard to follow
immediate folding logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287818
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Matt Arsenault [Wed, 23 Nov 2016 21:51:05 +0000 (21:51 +0000)]
AMDGPU: Fix debug printing
The uint8_t was printed as a char which didn't really work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287817
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Simon Pilgrim [Wed, 23 Nov 2016 21:19:57 +0000 (21:19 +0000)]
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287813
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Matt Arsenault [Wed, 23 Nov 2016 21:00:12 +0000 (21:00 +0000)]
AMDGPU: Fix not setting kill flag on temp reg when spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287808
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Matt Arsenault [Wed, 23 Nov 2016 21:00:10 +0000 (21:00 +0000)]
AMDGPU: Fix adding extra implicit def of register
In the scalar case, there's no reason to add an additional
def of the same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287807
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Matt Arsenault [Wed, 23 Nov 2016 20:52:53 +0000 (20:52 +0000)]
AMDGPU: Fix MMO when splitting spill
The size and offset were wrong. The size of the object was
being used for the size of the access, when here it is really
being split into 4-byte accesses. The underlying object size
is set in the MachinePointerInfo, which also didn't have the
offset set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287806
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Vedant Kumar [Wed, 23 Nov 2016 20:51:09 +0000 (20:51 +0000)]
Revert "[lit] When setting SDKROOT on Darwin, use '--sdk macosx' to find the right SDK path."
This reverts commit r287403. It breaks an internal asan bot. According
to Kuba, a fix is up for review here: https://reviews.llvm.org/D26929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287804
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Meador Inge [Wed, 23 Nov 2016 20:17:20 +0000 (20:17 +0000)]
llvm-nm: Print correct symbol types for init and fini sections
This patch fixes a small bug where symbols defined in the INIT
and FINI sections were incorrectly getting a type of 'n'.
Differential Revision: https://reviews.llvm.org/D26937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287803
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Meador Inge [Wed, 23 Nov 2016 20:17:15 +0000 (20:17 +0000)]
llvm-nm: Don't print value or size for undefined or weak symbols
Undefined and weak symbols don't have a meaningful size or value.
As such, nothing should be printed for those attributes (this is
already done for the address with 'U') with the BSD format. This
matches what GNU nm does.
Note that for the POSIX.2 format [1] zero values are still
printed for the size and value. This seems in spirit with
the format strings in that specification, but is debatable.
[1] http://pubs.opengroup.org/onlinepubs/
9699919799/
Differential Revision: https://reviews.llvm.org/D26936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287802
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Alexey Bataev [Wed, 23 Nov 2016 20:10:32 +0000 (20:10 +0000)]
[SLP] Add more tests for SLP Vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287801
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Haicheng Wu [Wed, 23 Nov 2016 19:39:26 +0000 (19:39 +0000)]
[LoopUnroll] Move code to exit early. NFC.
Just to save some compilation time.
Differential Revision: https://reviews.llvm.org/D26784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287800
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Daniel Berlin [Wed, 23 Nov 2016 19:03:54 +0000 (19:03 +0000)]
Revert "[Triple] Add Facebook vendor"
This reverts commit r287684
Objections on the review thread had not been addressed to
prior to commit. I asked the committer to revert, but i expect they
are gone for the US holiday or something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287798
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Michael Kuperstein [Wed, 23 Nov 2016 18:33:49 +0000 (18:33 +0000)]
[X86] Allow folding of stack reloads when loading a subreg of the spilled reg
We did not support subregs in InlineSpiller:foldMemoryOperand() because targets
may not deal with them correctly.
This adds a target hook to let the spiller know that a target can handle
subregs, and actually enables it for x86 for the case of stack slot reloads.
This fixes PR30832.
Differential Revision: https://reviews.llvm.org/D26521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287792
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Hemant Kulkarni [Wed, 23 Nov 2016 18:04:23 +0000 (18:04 +0000)]
llvm-readobj: Use hash tables to print dynamic symbols.
-symbols prints both .symtab and .dynsym symbols for GNU style in ELF.
-dyn-symbols prints symbols looking up through hash tables. This helps validate hash tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287786
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Chandler Carruth [Wed, 23 Nov 2016 17:53:26 +0000 (17:53 +0000)]
[PM] Change the static object whose address is used to uniquely identify
analyses to have a common type which is enforced rather than using
a char object and a `void *` type when used as an identifier.
This has a number of advantages. First, it at least helps some of the
confusion raised in Justin Lebar's code review of why `void *` was being
used everywhere by having a stronger type that connects to documentation
about this.
However, perhaps more importantly, it addresses a serious issue where
the alignment of these pointer-like identifiers was unknown. This made
it hard to use them in pointer-like data structures. We were already
dodging this in dangerous ways to create the "all analyses" entry. In
a subsequent patch I attempted to use these with TinyPtrVector and
things fell apart in a very bad way.
And it isn't just a compile time or type system issue. Worse than that,
the actual alignment of these pointer-like opaque identifiers wasn't
guaranteed to be a useful alignment as they were just characters.
This change introduces a type to use as the "key" object whose address
forms the opaque identifier. This both forces the objects to have proper
alignment, and provides type checking that we get it right everywhere.
It also makes the types somewhat less mysterious than `void *`.
We could go one step further and introduce a truly opaque pointer-like
type to return from the `ID()` static function rather than returning
`AnalysisKey *`, but that didn't seem to be a clear win so this is just
the initial change to get to a reliably typed and aligned object serving
is a key for all the analyses.
Thanks to Richard Smith and Justin Lebar for helping pick plausible
names and avoid making this refactoring many times. =] And thanks to
Sean for the super fast review!
While here, I've tried to move away from the "PassID" nomenclature
entirely as it wasn't really helping and is overloaded with old pass
manager constructs. Now we have IDs for analyses, and key objects whose
address can be used as IDs. Where possible and clear I've shortened this
to just "ID". In a few places I kept "AnalysisID" to make it clear what
was being identified.
Differential Revision: https://reviews.llvm.org/D27031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287783
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Alina Sbirlea [Wed, 23 Nov 2016 17:43:15 +0000 (17:43 +0000)]
[LoadStoreVectorizer] Enable vectorization of stores in the presence of an aliasing load
Summary:
The "getVectorizablePrefix" method would give up if it found an aliasing load for a store chain.
In practice, the aliasing load can be treated as a memory barrier and all stores that precede it
are a valid vectorizable prefix.
Issue found by volkan in D26962. Testcase is a pruned version of the one in the original patch.
Reviewers: jlebar, arsenm, tstellarAMD
Subscribers: mzolotukhin, wdng, nhaehnle, anna, volkan, llvm-commits
Differential Revision: https://reviews.llvm.org/D27008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287781
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Nirav Dave [Wed, 23 Nov 2016 16:48:35 +0000 (16:48 +0000)]
[DAG] Improve loads-from-store forwarding to handle TokenFactor
Forward store values to matching loads down through token
factors. Factored from D14834.
Reviewers: jyknight, hfinkel
Subscribers: hfinkel, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D26080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287773
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Yichao Yu [Wed, 23 Nov 2016 16:25:31 +0000 (16:25 +0000)]
Fix doc of `llvm.bitreverse.iN`
Summary:
The return type is `iN` rather than always `i16`
Seems to be a typo in https://reviews.llvm.org/rL252878 .
Reviewers: jmolloy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287769
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John Brawn [Wed, 23 Nov 2016 16:05:51 +0000 (16:05 +0000)]
[DAGCombiner] Fix infinite loop in vector mul/shl combining
We have the following DAGCombiner transformations:
(mul (shl X, c1), c2) -> (mul X, c2 << c1)
(mul (shl X, C), Y) -> (shl (mul X, Y), C)
(shl (mul x, c1), c2) -> (mul x, c1 << c2)
Usually the constant shift is optimised by SelectionDAG::getNode when it is
constructed, by SelectionDAG::FoldConstantArithmetic, but when we're dealing
with vectors and one of those vector constants contains an undef element
FoldConstantArithmetic does not fold and we enter an infinite loop.
Fix this by making FoldConstantArithmetic use getNode to decide how to fold each
vector element, the same as FoldConstantVectorArithmetic does, and rather than
adding the constant shift to the work list instead only apply the transformation
if it's already been folded into a constant, as if it's not we're going to loop
endlessly. Additionally add missing NoOpaques to one of those transformations,
which I noticed when writing the tests for this.
Differential Revision: https://reviews.llvm.org/D26605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287766
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Nemanja Ivanovic [Wed, 23 Nov 2016 15:51:52 +0000 (15:51 +0000)]
[PowerPC] Remove InstAlias definitions that cause incorrect assembly
In rL283190, I added some InstAlias definitions to generate extended mnemonics
for some uses of the XXPERMDI instruction. However, when the assembler matches
these extended mnemonics, it matches the new instruction in situations where it
should match the old one.
This patch removes these definitions and accomplishes that by defining these
mnemonics with additional instructions that are isCodeGenOnly.
Fixes PR31127.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287765
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Simon Pilgrim [Wed, 23 Nov 2016 14:01:18 +0000 (14:01 +0000)]
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets
Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287762
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Elena Demikhovsky [Wed, 23 Nov 2016 13:58:24 +0000 (13:58 +0000)]
Type legalization for compressstore and expandload intrinsics.
Implemented widening (v2f32) and splitting (v16f64).
On splitting, I use "popcnt" to calculate memory increment.
More type legalization work will come in the next patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287761
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Simon Pilgrim [Wed, 23 Nov 2016 13:42:09 +0000 (13:42 +0000)]
[CostModel][X86] Add missing AVX512DQ v8i64 fptosi/sitofp costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287760
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Benjamin Kramer [Wed, 23 Nov 2016 11:49:28 +0000 (11:49 +0000)]
[MD5] Use write32le instead of spelling it out with shifts.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287757
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Simon Pilgrim [Wed, 23 Nov 2016 11:43:00 +0000 (11:43 +0000)]
[CostModel][X86] Add v2f32 -> v2i64 fptosi/fptoui cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287756
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Craig Topper [Wed, 23 Nov 2016 06:54:55 +0000 (06:54 +0000)]
[AVX-512] Remove intrinsics for valignd/q and autoupgrade them to native shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287744
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Zvi Rackover [Wed, 23 Nov 2016 06:45:25 +0000 (06:45 +0000)]
[X86] Simplify lowerVectorShuffleAsBitMask to handle only integer VT's
Summary: This function is only called with integer VT arguments, so remove code that handles FP vectors.
Reviewers: RKSimon, craig.topper, delena, andreadb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287743
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Rui Ueyama [Wed, 23 Nov 2016 03:58:12 +0000 (03:58 +0000)]
Fix builbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287735
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Kuba Mracek [Wed, 23 Nov 2016 02:07:04 +0000 (02:07 +0000)]
[xray] Add XRay support for Mach-O in CodeGen
Currently, XRay only supports emitting the XRay table (xray_instr_map) on ELF binaries. Let's add Mach-O support.
Differential Revision: https://reviews.llvm.org/D26983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287734
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Davide Italiano [Wed, 23 Nov 2016 01:42:39 +0000 (01:42 +0000)]
[SCCP] Add a test for switches on undef.
Without this test, you can just remove the code fixing the
switch to the first constant in ResolvedUndefs in and everything
pass. This test, instead, fails with an assertion if the code
is removed. Found while refactoring SCCP to integrate undef in
the solver.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287731
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Rui Ueyama [Wed, 23 Nov 2016 00:46:09 +0000 (00:46 +0000)]
Add convenient functions to compute hashes of byte vectors.
In many sitautions, you just want to compute a hash for one chunk
of data. This patch adds convenient functions for that purpose.
Differential Revision: https://reviews.llvm.org/D26988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287726
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Eugene Zelenko [Wed, 23 Nov 2016 00:30:24 +0000 (00:30 +0000)]
[ADT] Fix some Clang-tidy modernize-use-default and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D27001
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287725
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Zachary Turner [Wed, 23 Nov 2016 00:27:23 +0000 (00:27 +0000)]
Make STL range adapter naming consistent.
Differential Revision: https://reviews.llvm.org/D27009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287724
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