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Andreas Gampe [Sat, 12 Jul 2014 08:47:46 +0000 (08:47 +0000)]
Merge "Aarch64: easy division and remainder for long ints."
Matteo Franchin [Tue, 1 Jul 2014 17:03:08 +0000 (18:03 +0100)]
Aarch64: easy division and remainder for long ints.
Also adding test 701 to test easy division and remainder for int and
long integers.
Change-Id: I8212c84e4d9eb3e9f3f4f1f1c3418537bb13dc55
Andreas Gampe [Sat, 12 Jul 2014 07:58:26 +0000 (07:58 +0000)]
Merge "ART: Fuse compare-with-0-and-branch in Arm64 utils-assembler"
Serban Constantinescu [Thu, 8 May 2014 13:31:41 +0000 (14:31 +0100)]
ART: Fuse compare-with-0-and-branch in Arm64 utils-assembler
This patch squashes the use of cmp + b to cbz.
Change-Id: I3d146a9921c471f08ba7304f1ca1b427d8e7dcf9
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Andreas Gampe [Sat, 12 Jul 2014 06:47:30 +0000 (06:47 +0000)]
Merge "Update counting VR for promotion"
Serguei Katkov [Fri, 4 Jul 2014 17:55:46 +0000 (00:55 +0700)]
Update counting VR for promotion
For 64-bit it makes sense to compute VR uses together for
int and long because core reg is shared.
Change-Id: Ie8676ece12c928d090da2465dfb4de4e91411920
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Andreas Gampe [Sat, 12 Jul 2014 03:16:32 +0000 (03:16 +0000)]
Merge "AArch64: Fix def use."
Zheng Xu [Fri, 11 Jul 2014 09:33:59 +0000 (17:33 +0800)]
AArch64: Fix def use.
Add comment to GenPCUseDefEncoding(). Fix def-use flags for several
instruction encodings.
Change-Id: Ifc5a2484395486c01a64307a4acddc794026d46a
Andreas Gampe [Sat, 12 Jul 2014 03:08:24 +0000 (03:08 +0000)]
Merge "Revert "Revert "ART: Key-Value Store in Oat header"""
Andreas Gampe [Wed, 9 Jul 2014 18:38:21 +0000 (11:38 -0700)]
Revert "Revert "ART: Key-Value Store in Oat header""
This reverts commit
452bee5da9811f62123978e142bd67b385e9ff82.
Heap-allocate a couple of objects in dex2oat to avoid large frame
size.
Includes fixes originally in 100596 and 100605.
Change-Id: Id51a44198c973c91f0a3f87b9d992a5dc110c6f8
Mathieu Chartier [Sat, 12 Jul 2014 01:32:58 +0000 (01:32 +0000)]
Merge "ART: Compacting ROS/DlMalloc spaces with semispace copy GC"
Zuo Wang [Thu, 10 Jul 2014 11:26:41 +0000 (04:26 -0700)]
ART: Compacting ROS/DlMalloc spaces with semispace copy GC
Current semispace copy GC is mainly associated with bump pointer
spaces. Though it squeezes fragmentation most aggressively, an extra
copy is required to re-establish the data in the ROS/DlMalloc space to allow
CMS GCs to happen afterwards. As semispace copy GC is still stop-the-world,
this not only introduces unnecessary overheads but also longer response time.
Response time indicates the time duration between the start of transition
request and the start of transition animation, which may impact the user
experience.
Using semispace copy GC to compact the data in a ROS space to another ROS(or
DlMalloc space to another DlMalloc) space solves this problem. Although it
squeezes less fragmentation, CMS GCs can run immediately after the compaction.
We apply this algorithm in two cases:
1) Right before throwing an OOM if -XX:EnableHSpaceCompactForOOM is passed in
as true.
2) When app is switched to background if the -XX:BackgroundGC option has value
HSpaceCompact.
For case 1), OOMs are significantly delayed in the harmony GC stress test,
with compaction ratio up to 0.87. For case 2), compaction ratio around 0.5 is
observed in both built-in SMS and browser. Similar results have been obtained
on other apps as well.
Change-Id: Iad9eabc6d046659fda3535ae20f21bc31f89ded3
Signed-off-by: Wang, Zuo <zuo.wang@intel.com>
Signed-off-by: Chang, Yang <yang.chang@intel.com>
Signed-off-by: Lei Li <lei.l.li@intel.com>
Signed-off-by: Lin Zang <lin.zang@intel.com>
Hans Boehm [Sat, 12 Jul 2014 01:07:25 +0000 (01:07 +0000)]
Merge "Call strong CAS from unsafe. Add more CAS versions."
Hans Boehm [Fri, 11 Jul 2014 16:56:07 +0000 (09:56 -0700)]
Call strong CAS from unsafe. Add more CAS versions.
Adds a number of additional CAS versions. Calls the correct
one from sun.misc.unsafe, fixing a recently introduced bug.
Avoid unnecessary ordering constraint when installing hash code.
Change-Id: I7c09d0c95ceb2a549ec28ee34084198ab3107946
Andreas Gampe [Fri, 11 Jul 2014 23:48:20 +0000 (23:48 +0000)]
Merge "ART: Change GenPCUseDefEncoding(), turn on Load Hoisting for ARM64"
Andreas Gampe [Fri, 11 Jul 2014 23:40:54 +0000 (16:40 -0700)]
ART: Change GenPCUseDefEncoding(), turn on Load Hoisting for ARM64
This defines the PC resource mask as empty, as the PC is not
accessible on ARM64.
Unify code paths with x86 in LoadStoreElimination and LoadHoisting.
Change-Id: Iea8b9e666f306c7a6ff52b6c5bf7e05b35346b2c
Ian Rogers [Sat, 12 Jul 2014 00:43:18 +0000 (00:43 +0000)]
Merge "Improve performance of invokevirtual/invokeinterface with embedded imt/vtable"
Mingyao Yang [Fri, 16 May 2014 00:02:16 +0000 (17:02 -0700)]
Improve performance of invokevirtual/invokeinterface with embedded imt/vtable
Add an embedded version of imt/vtable into class object. Both tables start at
fixed offset within class object so method/entry point can be loaded directly
from class object for invokeinterface/invokevirtual.
Bug:
8142917
Change-Id: I4240d58cfbe9250107c95c0708c036854c455968
Hans Boehm [Fri, 11 Jul 2014 23:08:14 +0000 (23:08 +0000)]
Merge "Replace memory barriers to better reflect Java needs."
Hans Boehm [Fri, 27 Jun 2014 21:50:10 +0000 (14:50 -0700)]
Replace memory barriers to better reflect Java needs.
Replaces barriers that enforce ordering of one access type
(e.g. Load) with respect to another (e.g. store) with more general
ones that better reflect both Java requirements and actual hardware
barrier/fence instructions. The old code was inconsistent and
unclear about which barriers implied which others. Sometimes
multiple barriers were generated and then eliminated;
sometimes it was assumed that certain barriers implied others.
The new barriers closely parallel those in C++11, though, for now,
we use something closer to the old naming.
Bug:
14685856
Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
Mathieu Chartier [Fri, 11 Jul 2014 22:31:50 +0000 (22:31 +0000)]
Merge "Faster TLAB allocator."
Mathieu Chartier [Fri, 11 Jul 2014 17:26:37 +0000 (10:26 -0700)]
Faster TLAB allocator.
New TLAB allocator doesn't increment bytes allocated until we allocate
a new TLAB. This increases allocation performance by avoiding a CAS.
MemAllocTest:
Before GSS TLAB: 3400ms.
After GSS TLAB: 2750ms.
Bug:
9986565
Change-Id: I1673c27555330ee90d353b98498fa0e67bd57fad
Christopher Ferris [Fri, 11 Jul 2014 20:07:45 +0000 (20:07 +0000)]
Merge "Make jemalloc the default choice."
Christopher Ferris [Fri, 11 Jul 2014 01:53:22 +0000 (18:53 -0700)]
Make jemalloc the default choice.
Change-Id: Iadf29d28758bc17904098b4eeb9bc14a0a51299e
Christopher Ferris [Fri, 11 Jul 2014 21:26:01 +0000 (21:26 +0000)]
Merge "Fix mac build."
Christopher Ferris [Fri, 11 Jul 2014 20:08:40 +0000 (13:08 -0700)]
Fix mac build.
Change-Id: I34a330ee038c7216eb3c4bcecbff2eb0cfa08589
Andreas Gampe [Fri, 11 Jul 2014 18:14:53 +0000 (18:14 +0000)]
Merge "ART: Fix GenSelect for ARM64"
Stuart Monteith [Fri, 11 Jul 2014 15:31:28 +0000 (16:31 +0100)]
ART: Fix GenSelect for ARM64
Add CSINV and replace CSNEG in GenSelect.
Some tests were failing in 083-complier-regression as CSNEG
was used instead of CSINV. CSNEG on xzr yields 0, whereas
CSINV negates the bits and yields -1, which was the intention.
Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
Sebastien Hertz [Fri, 11 Jul 2014 14:52:06 +0000 (14:52 +0000)]
Merge "Add missing class initialization during compilation and tests"
Sebastien Hertz [Fri, 11 Jul 2014 13:36:05 +0000 (13:36 +0000)]
Merge "Fix missing single-step event"
Sebastien Hertz [Fri, 11 Jul 2014 10:11:12 +0000 (10:11 +0000)]
Merge "Revert "Revert "Revert "Add intrinsic for Reference.get()""""
Sebastien Hertz [Fri, 11 Jul 2014 10:09:13 +0000 (10:09 +0000)]
Revert "Revert "Revert "Add intrinsic for Reference.get()"""
This reverts commit
d4415e8bd04c4a9367744ff0149597b4f37a0e0a.
Change-Id: I34553ccbdcfea35c7742d21be2a74dc7085ab2a0
Christopher Ferris [Fri, 11 Jul 2014 06:44:39 +0000 (06:44 +0000)]
Revert "Revert "Add intrinsic for Reference.get()""
This reverts commit
a9b870b73a155ce70c867d5b3f9758fab0b45f07.
Change-Id: Ic2a9b47f2b911bef4b764d10bc33cf000e4b4211
Christopher Ferris [Fri, 11 Jul 2014 04:18:58 +0000 (04:18 +0000)]
Revert "Add intrinsic for Reference.get()"
This reverts commit
460503b13bc894828a2d2d47d09e5534b3e91aa1.
Change-Id: Ie63f43049307e02e3b90f4e034abc9ea54ca4e24
Nicolas Geoffray [Fri, 11 Jul 2014 08:27:55 +0000 (08:27 +0000)]
Merge "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
Nicolas Geoffray [Fri, 11 Jul 2014 08:26:40 +0000 (08:26 +0000)]
Revert "Revert "Revert "Add implicit null and stack checks for x86"""
Broke the build.
This reverts commit
7fb36ded9cd5b1d254b63b3091f35c1e6471b90e.
Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
Dave Allison [Thu, 10 Jul 2014 02:05:10 +0000 (02:05 +0000)]
Revert "Revert "Add implicit null and stack checks for x86""
Fixes x86_64 cross compile issue. Removes command line options
and property to set implicit checks - this is hard coded now.
This reverts commit
3d14eb620716e92c21c4d2c2d11a95be53319791.
Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
Ian Rogers [Thu, 10 Jul 2014 21:20:14 +0000 (21:20 +0000)]
Merge "ART: Do not dump hidden basic blocks and add a counter to file naming"
Andreas Gampe [Thu, 10 Jul 2014 21:12:02 +0000 (21:12 +0000)]
Merge "x86_64: Enable fp-reg promotion"
Serguei Katkov [Tue, 8 Jul 2014 10:21:53 +0000 (17:21 +0700)]
x86_64: Enable fp-reg promotion
Patch introduces 4 register XMM12-15 available for promotion of
fp virtual registers.
Change-Id: I3f89ad07fc8ae98b70f550eada09be7b693ffb67
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Nicolas Geoffray [Fri, 11 Jul 2014 08:26:20 +0000 (08:26 +0000)]
Merge "Revert "Fix mac build""
Christopher Ferris [Fri, 11 Jul 2014 05:43:02 +0000 (05:43 +0000)]
Revert "Fix mac build"
This reverts commit
e9343344d9bd268a05d1eae1ce80a3278ec19c89.
Change-Id: I43d1717af9c3b1237dcacec66f55a4e4b8e1f0fe
Dave Allison [Thu, 10 Jul 2014 22:29:28 +0000 (15:29 -0700)]
Fix mac build
Fixes x86 fault handler, sigchain and quick_entrypoints for x86_64.
Bug:
16215218
Change-Id: I5e58660ea815042968444e6352c57a5f53314cfd
Ian Rogers [Thu, 10 Jul 2014 22:00:23 +0000 (22:00 +0000)]
Merge "Updates to help classes derived from X86Mir2Lir"
Mark Mendell [Fri, 4 Jul 2014 01:34:41 +0000 (21:34 -0400)]
Updates to help classes derived from X86Mir2Lir
Just a couple of extra changes to help me out. These changes won't
affect anyone else.
Change-Id: I0e0985a4f16822d5cbfabbf81c9902d34ebdb5da
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Dave Allison [Thu, 10 Jul 2014 21:25:05 +0000 (21:25 +0000)]
Merge "Revert "Revert "Add implicit null and stack checks for x86"""
Christopher Ferris [Fri, 11 Jul 2014 07:09:25 +0000 (07:09 +0000)]
Merge "Revert "Revert "Add intrinsic for Reference.get()"""
Andreas Gampe [Fri, 11 Jul 2014 06:12:08 +0000 (06:12 +0000)]
Merge "ART: Fix GenSelect and GenFusedLongCmpBranch for ARM64"
Andreas Gampe [Thu, 10 Jul 2014 10:23:41 +0000 (03:23 -0700)]
ART: Fix GenSelect and GenFusedLongCmpBranch for ARM64
Depending on the result, we need to issue a wide csel. Also need
to handle constants, and src and dest being the same.
In GenFusedLongCmpBranch there is an ordering issue. If we swap
the inputs, we did not Load the second one.
Change-Id: Icb9876ca1288602d078b9fb89ea964ec2c910e0c
Christopher Ferris [Fri, 11 Jul 2014 04:45:03 +0000 (04:45 +0000)]
Merge "Revert "Add intrinsic for Reference.get()""
Dave Allison [Fri, 11 Jul 2014 03:42:17 +0000 (03:42 +0000)]
Merge "Fix mac build"
Mathieu Chartier [Fri, 11 Jul 2014 01:54:07 +0000 (01:54 +0000)]
Merge "Add intrinsic for Reference.get()"
Mathieu Chartier [Fri, 11 Jul 2014 01:47:39 +0000 (01:47 +0000)]
Merge "Change default heap maximum size to be 256m."
Mathieu Chartier [Fri, 11 Jul 2014 00:50:34 +0000 (17:50 -0700)]
Change default heap maximum size to be 256m.
Useful for command line benchmarks.
Change-Id: Ie525863cd8eff93c64ce76639b1108fbdad91633
Mathieu Chartier [Fri, 11 Jul 2014 00:31:37 +0000 (00:31 +0000)]
Merge "Fix race condition in release pages."
Mathieu Chartier [Thu, 10 Jul 2014 17:16:44 +0000 (10:16 -0700)]
Fix race condition in release pages.
There was a race condition where another thread could coalesce the
free page run before we acquired the lock. In that case
free_page_runs_.find will not find a run starting at fpr. Added a
condition to handle this case. Also added handling for free page
runs with begin with released pages but end with empty pages.
Bug:
16191993
Change-Id: Ib12fdac8c246eae29c36f6a6728eb11d85553bbb
Jean Christophe Beyler [Thu, 19 Jun 2014 16:34:51 +0000 (09:34 -0700)]
ART: Do not dump hidden basic blocks and add a counter to file naming
Currently, if the system dumps the CFG, it dumps the hidden BasicBlocks.
Also, the patch adds a counter that gets incremented to make the file naming
unique, using AtomicInteger.
Change-Id: I55b489c2c2bded73b62d64a94a4a8a54d2ebed2b
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Fred Shih [Wed, 18 Jun 2014 18:26:11 +0000 (11:26 -0700)]
Add intrinsic for Reference.get()
Added an intrinsic function for Reference.get(). Return immediately
without going through JNI if the slow path is not currently in use.
Otherwise, branch off to the the existing JNI function.
Approximately 47x speedup for cases where slow path is not enabled.
Change-Id: I13ad65a356fe4e104d8d83980694dc2740d7d039
Ian Rogers [Thu, 10 Jul 2014 19:15:04 +0000 (19:15 +0000)]
Merge "ART: Add Invokes to DecodedInstruction"
Jean Christophe Beyler [Mon, 2 Jun 2014 16:03:14 +0000 (09:03 -0700)]
ART: Add Invokes to DecodedInstruction
Add a method Invokes to test for the kInvoke flag.
Also moved IsPseudoMirOp to DecodedInstruction to use it for the various
querry methods.
Change-Id: I59a2056b7b802b8393fa2b0d977304d252b38c89
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Ian Rogers [Thu, 10 Jul 2014 18:56:00 +0000 (18:56 +0000)]
Merge "ART: Handle Extended MIRs in a uniform manner"
Ian Rogers [Thu, 10 Jul 2014 18:40:06 +0000 (18:40 +0000)]
Merge "ART: Detached blocks should not be processed by compiler"
Ian Rogers [Thu, 10 Jul 2014 17:35:57 +0000 (17:35 +0000)]
Merge "Make CAS operations in Object use art::Atomic."
Sebastien Hertz [Tue, 24 Jun 2014 12:35:40 +0000 (14:35 +0200)]
Add missing class initialization during compilation and tests
Adds missing class initialization during compilation and tests, especially
java.lang.Class. Otherwise, we'd be able to execute code while the referring
class is not initialized or initializing.
Also adds mirror::Class::AssertInitializedOrInitializingInThread method to
check class initialization when entering the interpreter: the called method's
declaring class must either be initialized or be initializing by the current
thread (other threads must be waiting for the class initialization to complete
holding its lock). Note we only do this check in debug build.
Bump oat version to force compilation.
Bug:
15899971
Change-Id: I9a4edd3739a3ca4cf1c4929dcbb44cdf7a1ca1fe
Sebastien Hertz [Wed, 11 Jun 2014 17:45:05 +0000 (19:45 +0200)]
Fix missing single-step event
During debugging, we used to suspend too lately after a step. It occurred when
we were stepping out of an interpreted method into a compiled "caller" method.
The issue is we did not deoptimize when returning from the interpreted method
but only did it when returning from the compiled method. Therefore we were not
executing the rest of the compiled method's code with interpreter which
prevents from debugging it.
This CL fixes this issue by using instrumentation entry/exit stubs when calling
interpreted method from compiled code. Therefore, we execute instrumentation
exit stub when returning from interpreter and are able to deoptimize from this
point. This allows to execute compiled method's code with interpreter and to
debug it.
We now also prevent from reporting method entry/exit twice while instrumenting
interpreted methods. We report method entry/exit events only from interpreter.
Bug:
14422182
Bug:
11705760
Change-Id: Ia1175d36202239273083c4e9733c7e9290244090
Ian Rogers [Thu, 10 Jul 2014 09:07:54 +0000 (02:07 -0700)]
Make CAS operations in Object use art::Atomic.
Make naming consistent with art::Atomic.
Change-Id: If3abdb019ef8b53bd809e3fef3fd5248aeb27e9a
Ian Rogers [Thu, 10 Jul 2014 07:56:36 +0000 (00:56 -0700)]
Fix GC to use art::Atomic rather than compiler intrinsics.
Changes to SpaceBitmap::AtomicTestAndSet and Space::end_. Space::end_ is made
atomic rather than volatile to fully capture all its uses multi-threaded or not
uses.
Change-Id: I3058964b8ad90a8c253b3d7f75585f63ca2fb5e3
Udayan Banerji [Thu, 10 Jul 2014 02:14:53 +0000 (19:14 -0700)]
ART: Handle Extended MIRs in a uniform manner
The special handling is needed since some extended MIRs can hold values in
args array, and we might want to handle the dataflow for those in a
specialized manner. Current dataflow attributes may not be able to describe
it for the extended MIRs.
Change-Id: I8b64f3142a4304282bb31f1d4686eba72284d97d
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Andreas Gampe [Thu, 10 Jul 2014 09:29:20 +0000 (09:29 +0000)]
Merge "Slow path for iget should expect return in core reg"
Serguei Katkov [Mon, 7 Jul 2014 17:45:45 +0000 (00:45 +0700)]
Slow path for iget should expect return in core reg
Slow path for iget invokes the C implementation.
In all cases the C function returns the result in core reg.
So implementation should expect the result in core reg
independent on whether it is fp or not.
Change-Id: I57fb0e684c38af22316398d8071f087bd4bd253c
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Hiroshi Yamauchi [Thu, 10 Jul 2014 19:56:12 +0000 (19:56 +0000)]
Merge "Improve the OOME fragmentation message."
Hiroshi Yamauchi [Wed, 9 Jul 2014 19:54:32 +0000 (12:54 -0700)]
Improve the OOME fragmentation message.
Change-Id: I390d3622f8d572ec7e34ea6dff9e1e0936e81ac1
Ian Rogers [Thu, 10 Jul 2014 04:38:36 +0000 (04:38 +0000)]
Merge "Move thread state to art::Atomic."
Ian Rogers [Thu, 10 Jul 2014 04:12:06 +0000 (21:12 -0700)]
Move thread state to art::Atomic.
Leaves the CAS operations as relaxed although art::Atomic treats relaxed CAS
as a strong CAS when not compiling with clang.
Change-Id: I6d37c22173540d166b624385e52e4ad05e592adc
Vladimir Marko [Thu, 10 Jul 2014 18:14:31 +0000 (18:14 +0000)]
Merge "ART: Rename CallInlining to SpecialMethodInliner"
Razvan A Lupusoru [Wed, 9 Jul 2014 23:42:19 +0000 (16:42 -0700)]
ART: Rename CallInlining to SpecialMethodInliner
The CallInlining pass is used to inline just a set of pre-categorized methods.
This set of methods includes empty, instance getters, instance setters, argument
return, and constant return. Since it inlines only "special methods", it makes
sense to name it to reflect that.
Change-Id: Iea2c1820080b0c212c99e977f6b5d34ee0774868
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Vladimir Marko [Thu, 10 Jul 2014 09:12:40 +0000 (09:12 +0000)]
Merge "Global Value Numbering."
Vladimir Marko [Fri, 30 May 2014 09:01:32 +0000 (10:01 +0100)]
Global Value Numbering.
Implement the Global Value Numbering for optimization
purposes. Use it for the null check and range check
elimination as the LVN used to do.
The order of evaluation of basic blocks needs improving as
we currently fail to recognize some obviously identical
values in methods with more than one loop. (There are three
disabled tests that check this. This is just a missed
optimization, not a correctness issue.)
Change-Id: I0d0ce16b2495b5a3b17ad1b2b32931cd69f5a25a
Vladimir Marko [Thu, 10 Jul 2014 08:22:12 +0000 (08:22 +0000)]
Merge "Handle potential <clinit>() correctly in LVN."
Vladimir Marko [Thu, 10 Jul 2014 08:21:49 +0000 (08:21 +0000)]
Merge "Faster deduplication in OatWriter."
Ian Rogers [Thu, 10 Jul 2014 08:14:55 +0000 (08:14 +0000)]
Merge "Fix GC to use art::Atomic rather than compiler intrinsics."
Vladimir Marko [Wed, 9 Jul 2014 15:06:40 +0000 (16:06 +0100)]
Faster deduplication in OatWriter.
Use lower_bound() to look for duplicates and use it as
a hint for insertion of new entries. Add a few useful
functions to SafeMap<>.
Change-Id: If7eab3f5d153be6e0d7ae040929849f1a636ee29
Niranjan Kumar [Thu, 12 Jun 2014 19:15:48 +0000 (12:15 -0700)]
ART: Detached blocks should not be processed by compiler
It is possible for blocks to be detached. This means that 'successor_block_info->block'
may evaluate to 'NullBasicBlockId' The code should detect this case and handle it
appropriately.
Signed-off-by: vladimir.a.ivanov <vladimir.a.ivanov@intel.com
Signed-off-by: Niranjan Kumar <niranjan.kumar@intel.com
Change-Id: I410059cd2cbda342cc1380050c0972fcaa2b7a8e
Vladimir Marko [Wed, 9 Jul 2014 13:45:36 +0000 (14:45 +0100)]
Handle potential <clinit>() correctly in LVN.
Bug:
16177324
Change-Id: I727ab6ce9aa9a608fe570cf391a6b732a12a8655
Andreas Gampe [Thu, 10 Jul 2014 10:03:29 +0000 (10:03 +0000)]
Merge "ART: Enable some ARM64 optimizations."
Andreas Gampe [Thu, 10 Jul 2014 09:04:01 +0000 (02:04 -0700)]
ART: Enable some ARM64 optimizations.
Enables kSuppressLoads, kTrackLiveTemps, kSafeOptimizations,
kPromoteCompilerTemps, kClassInitCheckElimination,
kSuppressExceptionEdges and kMatch.
Change-Id: Id3650adce7140dde8d667cd3f1b4a1c2598f156e
Andreas Gampe [Thu, 10 Jul 2014 07:54:06 +0000 (07:54 +0000)]
Merge "Use memory chunks for monitors on LP64"
Andreas Gampe [Thu, 17 Apr 2014 17:35:09 +0000 (10:35 -0700)]
Use memory chunks for monitors on LP64
Monitor IDs in lock words are only 30b. On a 32b system that works
fine, as memory is usually aligned enough that shifting works out.
On 64b systems, the virtual memory space is too large for that.
This adds memory chunks into which we allocate the monitors so that
we have base_addr + offset and can use the offset as the monitor ID.
To allow for relatively compact but growable storage, we use a list
of chunks.
Added a global lock for the monitor pool.
Change-Id: I0e290c4914a2556e0b2eef9902422d7c4dcf536d
Ian Rogers [Thu, 10 Jul 2014 06:49:02 +0000 (06:49 +0000)]
Merge "Missed use of android_atomic and thread state_."
Ian Rogers [Thu, 10 Jul 2014 05:02:36 +0000 (22:02 -0700)]
Missed use of android_atomic and thread state_.
Move to using art::Atomic, add necessary FetchAnd... operations to art::Atomic.
Change-Id: I32f1cdc4e0a2037b73f459bf4bb4d544f357f41b
Ian Rogers [Thu, 10 Jul 2014 06:37:47 +0000 (06:37 +0000)]
Merge "Fix tracing."
Ian Rogers [Thu, 10 Jul 2014 06:16:06 +0000 (23:16 -0700)]
Fix tracing.
Change-Id: If6837270baec694c00cc1884bae0f1842d49da75
Ian Rogers [Wed, 9 Jul 2014 15:26:09 +0000 (15:26 +0000)]
Merge "x86_64: enable Peek and Poke intrinsics"
Ian Rogers [Thu, 10 Jul 2014 03:36:51 +0000 (03:36 +0000)]
Merge "Move another field away from android_atomic_cas."
Ian Rogers [Thu, 10 Jul 2014 01:00:50 +0000 (18:00 -0700)]
Move another field away from android_atomic_cas.
Change-Id: If63aa2811e06ec401a601286a3bacb62a0da96ad
Ian Rogers [Wed, 9 Jul 2014 18:58:43 +0000 (18:58 +0000)]
Merge "Allow method tracing for run-test"
Ian Rogers [Wed, 9 Jul 2014 18:52:43 +0000 (18:52 +0000)]
Merge "Fix method tracing from command-line"
Andreas Gampe [Thu, 10 Jul 2014 08:50:46 +0000 (08:50 +0000)]
Merge "ART: Refactor frontend.cc"
Andreas Gampe [Thu, 10 Jul 2014 08:43:08 +0000 (01:43 -0700)]
ART: Refactor frontend.cc
Refactor frontend.cc. Pull out flags, merge them in arrays keyed by
the instruction set. Simplify the checks and application of flags.
Change-Id: I12d5216df8d1f12e7fbe39d8132e4725c55bc8e7
Colin Cross [Thu, 10 Jul 2014 06:10:48 +0000 (06:10 +0000)]
Merge "art: fix host dex2oat runtime args"