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7 years ago[sancov] skip duplicated points
Mike Aizatsky [Wed, 21 Dec 2016 22:10:01 +0000 (22:10 +0000)]
[sancov] skip duplicated points

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290278 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[sancov] hash prefix results in huge merge files, use shorter prefix
Mike Aizatsky [Wed, 21 Dec 2016 22:09:57 +0000 (22:09 +0000)]
[sancov] hash prefix results in huge merge files, use shorter prefix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290277 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Remove a redundant check. NFC.
Haicheng Wu [Wed, 21 Dec 2016 21:40:47 +0000 (21:40 +0000)]
[AArch64] Remove a redundant check. NFC.

The case AM.Scale == 0 is already handled by the code right above.

Differential Revision: https://reviews.llvm.org/D28003

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290275 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd the ability for DWARFDie objects to get the parent DWARFDie.
Greg Clayton [Wed, 21 Dec 2016 21:37:06 +0000 (21:37 +0000)]
Add the ability for DWARFDie objects to get the parent DWARFDie.

In order for the llvm DWARF parser to be used in LLDB we will need to be able to get the parent of a DIE. This patch adds that functionality by changing the DWARFDebugInfoEntry class to store a depth field instead of a sibling index. Using a depth field allows us to easily calculate the sibling and the parent without increasing the size of DWARFDebugInfoEntry.

I tested llvm-dsymutil on a debug version of clang where this fully parses DWARF in over 1200 .o files to verify there was no serious regression in performance.

Added a full suite of unit tests to test this functionality.

Differential Revision: https://reviews.llvm.org/D27995

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290274 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agocmake: Don't build llvm-config and tblgen concurrently in cross builds
Justin Bogner [Wed, 21 Dec 2016 21:19:00 +0000 (21:19 +0000)]
cmake: Don't build llvm-config and tblgen concurrently in cross builds

This sets USES_TERMINAL for the native llvm-config build, so that it
doesn't run at the same time as builds of other native tools (namely,
tablegen). Without this, if you're very unlucky with the timing it's
possible to be relinking libSupport as one of the tools is linking,
causing a spurious failure.

The tablegen build adopted USES_TERMINAL for this same reason in
r280748.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290271 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate mailing list post URL and add libunwind reference
Ed Maste [Wed, 21 Dec 2016 20:51:42 +0000 (20:51 +0000)]
Update mailing list post URL and add libunwind reference

RTDyldMemoryManager.cpp describes the differing __register_frame
API between libunwind and libgcc, with a mailing list posting URL.

The original link was 404; replace it with what I believe is the
intended post, as well as a reference to the "OS X" implementation in
libunwind.

Differential Revision: https://reviews.llvm.org/D27965

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290269 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Improve lowering of vXi64 multiplies
Simon Pilgrim [Wed, 21 Dec 2016 20:00:10 +0000 (20:00 +0000)]
[X86][SSE] Improve lowering of vXi64 multiplies

As mentioned on PR30845, we were performing our vXi64 multiplication as:

AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi, 32)+ psllqi(AhiBlo, 32);

when we could avoid one of the upper shifts with:

AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi + AhiBlo, 32);

This matches the lowering on gcc/icc.

Differential Revision: https://reviews.llvm.org/D27756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290267 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp"
David Majnemer [Wed, 21 Dec 2016 19:21:59 +0000 (19:21 +0000)]
Revert "[InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp"

This reverts commit r289813, it caused PR31449.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290266 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix file header
Tom Stellard [Wed, 21 Dec 2016 19:06:24 +0000 (19:06 +0000)]
AMDGPU/SI: Fix file header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290265 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTypeMetadataUtils: Simplify; spotted by Mehdi.
Peter Collingbourne [Wed, 21 Dec 2016 19:00:47 +0000 (19:00 +0000)]
TypeMetadataUtils: Simplify; spotted by Mehdi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290264 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd missing includes on Windows.
Zachary Turner [Wed, 21 Dec 2016 18:50:52 +0000 (18:50 +0000)]
Add missing includes on Windows.

Patch by Andrey Khalyavin
Differential Revision: https://reviews.llvm.org/D27915

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290263 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LLParser] Parse vector GEP constant expression correctly
Michael Kuperstein [Wed, 21 Dec 2016 18:29:47 +0000 (18:29 +0000)]
[LLParser] Parse vector GEP constant expression correctly

The constantexpr parsing was too constrained and rejected legal vector GEPs.
This relaxes it to be similar to the ones for instruction parsing.

This fixes PR30816.

Differential Revision: https://reviews.llvm.org/D28013

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290261 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ConstantFolding] Fix vector GEPs harder
Michael Kuperstein [Wed, 21 Dec 2016 17:34:21 +0000 (17:34 +0000)]
[ConstantFolding] Fix vector GEPs harder

For vector GEPs, CastGEPIndices can end up in an infinite recursion, because
we compare the vector type to the scalar pointer type, find them different,
and then try to cast a type to itself.

Differential Revision: https://reviews.llvm.org/D28009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290260 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CostModel] Pass shuffle mask args with ArrayRef. NFCI.
Simon Pilgrim [Wed, 21 Dec 2016 15:49:01 +0000 (15:49 +0000)]
[CostModel] Pass shuffle mask args with ArrayRef. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290257 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agorevert first commit . removing empty line in X86.h
Michael Zuckerman [Wed, 21 Dec 2016 12:48:01 +0000 (12:48 +0000)]
revert first commit . removing empty line in X86.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290255 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFirst commit adding new line to X86.h
Michael Zuckerman [Wed, 21 Dec 2016 12:44:47 +0000 (12:44 +0000)]
First commit adding new line to X86.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290254 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded a template for building target specific memory node in DAG.
Elena Demikhovsky [Wed, 21 Dec 2016 10:43:36 +0000 (10:43 +0000)]
Added a template for building target specific memory node in DAG.

I added API for creation a target specific memory node in DAG. Today, all memory nodes are common for all targets and their constructors are located in SelectionDAG.cpp.
There are some cases in X86 where we need to create a special node - truncation-with-saturation store, float-to-half-store.
In the current patch I added truncation-with-saturation nodes and I'm using them for intrinsics. In the future I plan to implement DAG lowering for truncation-with-saturation pattern.

Differential Revision: https://reviews.llvm.org/D27899

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290250 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AMDGPU] Garbage collect dead code. NFCI.
Davide Italiano [Wed, 21 Dec 2016 10:19:00 +0000 (10:19 +0000)]
[AMDGPU] Garbage collect dead code. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290249 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Oren Ben Simhon [Wed, 21 Dec 2016 09:47:31 +0000 (09:47 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support

Fixing a warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290248 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Oren Ben Simhon [Wed, 21 Dec 2016 09:18:37 +0000 (09:18 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support

Fixing failing test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290246 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Oren Ben Simhon [Wed, 21 Dec 2016 08:59:42 +0000 (08:59 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support

Fixing build issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290244 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Oren Ben Simhon [Wed, 21 Dec 2016 08:31:45 +0000 (08:31 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support

The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible.
vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use.
The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above.

The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it.
This aubmit also includes additional lit tests to cover better HVAs corner cases.

Differential Revision: https://reviews.llvm.org/D27392

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290240 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LDist] Match behavior between invoking via optimization pipeline or opt -loop-distribute
Adam Nemet [Wed, 21 Dec 2016 04:07:40 +0000 (04:07 +0000)]
[LDist] Match behavior between invoking via optimization pipeline or opt -loop-distribute

In r267672, where the loop distribution pragma was introduced, I tried
it hard to keep the old behavior for opt: when opt is invoked
with -loop-distribute, it should distribute the loop (it's off by
default when ran via the optimization pipeline).

As MichaelZ has discovered this has the unintended consequence of
breaking a very common developer work-flow to reproduce compilations
using opt: First you print the pass pipeline of clang
with -debug-pass=Arguments and then invoking opt with the returned
arguments.

clang -debug-pass will include -loop-distribute but the pass is invoked
with default=off so nothing happens unless the loop carries the pragma.
While through opt (default=on) we will try to distribute all loops.

This changes opt's default to off as well to match clang.  The tests are
modified to explicitly enable the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290235 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoremove pretty-print test that requires debug
Sebastian Pop [Wed, 21 Dec 2016 03:37:39 +0000 (03:37 +0000)]
remove pretty-print test that requires debug

There is no need to test the pretty printer. Remove the boggus test to make the
build bots happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290234 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APFloat] Remove 'else' after return. NFC
Tim Shen [Wed, 21 Dec 2016 02:39:21 +0000 (02:39 +0000)]
[APFloat] Remove 'else' after return. NFC

Reviewers: kbarton, iteratee, hfinkel, echristo

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D27934

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290232 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc][RPC] Actually specialize SerializationTraits and RPCTypeName in the right
Lang Hames [Wed, 21 Dec 2016 02:08:23 +0000 (02:08 +0000)]
[Orc][RPC] Actually specialize SerializationTraits and RPCTypeName in the right
namespace.

r290226 was a think-o - just qualifying the name doesn't count.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290230 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agomachine combiner: fix pretty printer
Sebastian Pop [Wed, 21 Dec 2016 01:41:12 +0000 (01:41 +0000)]
machine combiner: fix pretty printer

we used to print UNKNOWN instructions when the instruction to be printer was not
yet inserted in any BB: in that case the pretty printer would not be able to
compute a TII as the instruction does not belong to any BB or function yet.
This patch explicitly passes the TII to the pretty-printer.

Differential Revision: https://reviews.llvm.org/D27645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290228 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc][RPC] Specialize RPCTypeName and SerializationTraits in the right namespace.
Lang Hames [Wed, 21 Dec 2016 01:17:19 +0000 (01:17 +0000)]
[Orc][RPC] Specialize RPCTypeName and SerializationTraits in the right namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290226 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove natvis for llvm::SmallString so that it correctly displays only the valid...
Antonio Maiorano [Wed, 21 Dec 2016 01:05:29 +0000 (01:05 +0000)]
Improve natvis for llvm::SmallString so that it correctly displays only the valid portion of the string

The usual method, and the one employed before my change, of displaying strings in natvis is to make use of the "<variable>,s" format specifier; however, this method only works for null-terminated strings. My fix here is to use the "<pointer>,[size]" format specifier to display a bounded array, and then cast it to "const char*", which in the MSVC debugger has the desired effect of rendering the character array as a string.

Differential Revision: https://reviews.llvm.org/D27972

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290224 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Add some static-assert checks to improve the error messages for RPC calls
Lang Hames [Wed, 21 Dec 2016 00:59:33 +0000 (00:59 +0000)]
[Orc] Add some static-assert checks to improve the error messages for RPC calls
and handler registrations.

Also add a unit test for alternate-type serialization/deserialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290223 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIPO: Remove the ModuleSummary argument to the FunctionImport pass. NFCI.
Peter Collingbourne [Wed, 21 Dec 2016 00:50:12 +0000 (00:50 +0000)]
IPO: Remove the ModuleSummary argument to the FunctionImport pass. NFCI.

No existing client is passing a non-null value here. This will come back
in a slightly different form as part of the type identifier summary work.

Differential Revision: https://reviews.llvm.org/D28006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290222 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Analysis] Centralize objectsize lowering logic.
George Burgess IV [Tue, 20 Dec 2016 23:46:36 +0000 (23:46 +0000)]
[Analysis] Centralize objectsize lowering logic.

We're currently doing nearly the same thing for @llvm.objectsize in
three different places: two of them are missing checks for overflow,
and one of them could subtly break if InstCombine gets much smarter
about removing alloc sites. Seems like a good idea to not do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290214 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove GlobPattern class from LLD to llvm/Support.
Rui Ueyama [Tue, 20 Dec 2016 23:09:09 +0000 (23:09 +0000)]
Move GlobPattern class from LLD to llvm/Support.

GlobPattern is a class to handle glob pattern matching. Currently
only LLD is using that, but technically that feature is not specific
to linkers, so in this patch I move that file to LLVM.

Differential Revision: https://reviews.llvm.org/D27969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290212 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Be less conservative when extending bitwidths for computing ranges.
Michael Zolotukhin [Tue, 20 Dec 2016 23:03:42 +0000 (23:03 +0000)]
[SCEV] Be less conservative when extending bitwidths for computing ranges.

Summary:
In getRangeForAffineAR we compute ranges for affine exprs E = A + B*C,
where ranges for A, B, and C are known. To avoid overflow, we need to
operate on a bigger bitwidth, and originally we chose 2*x+1 for this
(x being the original bitwidth). However, it is safe to use just 2*x:

A+B*C <= (2^x - 1) + (2^x - 1)*(2^x - 1) =
       =  2^x - 1 + 2^2x - 2^x - 2^x + 1 =
       = 2^2x - 2^x <= 2^2x - 1

Unnecessary extending of bitwidths results in noticeable slowdowns: ranges
perform arithmetic operations using APInt, which are much slower when bitwidths
are bigger than 64.

Reviewers: sanjoy, majnemer, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D27795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290211 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[ObjectYAML] Support for DWARF debug_info section"
Chris Bieneman [Tue, 20 Dec 2016 22:36:42 +0000 (22:36 +0000)]
Revert "[ObjectYAML] Support for DWARF debug_info section"

This reverts commit r290204.

Still breaking bots... In a meeting now, so I can't fix it immediately.

Bot URL:
http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/2415

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290209 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ObjectYAML] Support for DWARF debug_info section
Chris Bieneman [Tue, 20 Dec 2016 21:35:31 +0000 (21:35 +0000)]
[ObjectYAML] Support for DWARF debug_info section

This patch adds support for YAML<->DWARF for debug_info sections.

This re-lands r290147, after fixing the issue that caused bots to fail (thank you UBSan!).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290204 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Eliminate non-determinism in the module summary analysis.
Peter Collingbourne [Tue, 20 Dec 2016 21:12:28 +0000 (21:12 +0000)]
IR: Eliminate non-determinism in the module summary analysis.

Also make the summary ref and call graph vectors immutable. This means
a smaller API surface and fewer places to audit for non-determinism.

Differential Revision: https://reviews.llvm.org/D27875

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290200 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopUnroll] Modify a comment to clarify the usage of TripCount. NFC.
Haicheng Wu [Tue, 20 Dec 2016 20:23:48 +0000 (20:23 +0000)]
[LoopUnroll] Modify a comment to clarify the usage of TripCount. NFC.

Make it clear that TripCount is the upper bound of the iteration on which
control exits LatchBlock.

Differential Revision: https://reviews.llvm.org/D26675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290199 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Implement isExtractSubvectorCheap.
Eli Friedman [Tue, 20 Dec 2016 20:05:07 +0000 (20:05 +0000)]
[ARM] Implement isExtractSubvectorCheap.

See https://reviews.llvm.org/D6678 for the history of
isExtractSubvectorCheap. Essentially the same considerations apply
to ARM.

This temporarily breaks the formation of vpadd/vpaddl in certain cases;
AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles.
See https://reviews.llvm.org/D27779 for followup fix.

Differential Revision: https://reviews.llvm.org/D27774

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290198 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Generate checks for shuffle tests using update_llc_test_checks.py.
Eli Friedman [Tue, 20 Dec 2016 19:33:24 +0000 (19:33 +0000)]
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290196 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse MaxDepth instead of repeating its value
Matt Arsenault [Tue, 20 Dec 2016 19:06:15 +0000 (19:06 +0000)]
Use MaxDepth instead of repeating its value

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290194 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Allow 16-bit types in inline asm constraints
Matt Arsenault [Tue, 20 Dec 2016 19:06:12 +0000 (19:06 +0000)]
AMDGPU: Allow 16-bit types in inline asm constraints

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290193 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Run fp combine tests on VI
Matt Arsenault [Tue, 20 Dec 2016 18:55:11 +0000 (18:55 +0000)]
AMDGPU: Run fp combine tests on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290192 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Don't add same instruction multiple times to worklist
Matt Arsenault [Tue, 20 Dec 2016 18:55:06 +0000 (18:55 +0000)]
AMDGPU: Don't add same instruction multiple times to worklist

When the instruction is processed the first time, it may be
deleted resulting in crashes. While the new test adds the same
user to the worklist twice, this particular case doesn't crash
but I'm not sure why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290191 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReplace std::find_if with llvm::find_if. NFC.
George Burgess IV [Tue, 20 Dec 2016 18:46:27 +0000 (18:46 +0000)]
Replace std::find_if with llvm::find_if. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290190 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Re-add the assert to StringRef's const char *, length constructor."
Zachary Turner [Tue, 20 Dec 2016 18:05:47 +0000 (18:05 +0000)]
Revert "Re-add the assert to StringRef's const char *, length constructor."

This reverts commit r290188, which is causing internal compiler errors
on GCC 4.8

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290189 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-add the assert to StringRef's const char *, length constructor.
Zachary Turner [Tue, 20 Dec 2016 17:57:56 +0000 (17:57 +0000)]
Re-add the assert to StringRef's const char *, length constructor.

By putting the assert behind a conditional in the initializer list
we can ensure that it will still work in a constexpr context as
the else branch of the ternary operator won't be examined unless
the condition fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290188 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix missing '>' in docs (hopefully fixes bot error... )
David Blaikie [Tue, 20 Dec 2016 17:43:48 +0000 (17:43 +0000)]
Fix missing '>' in docs (hopefully fixes bot error... )

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290187 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd some brief documentation about GDB pretty printers
David Blaikie [Tue, 20 Dec 2016 17:33:58 +0000 (17:33 +0000)]
Add some brief documentation about GDB pretty printers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290186 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Make a function const
Tom Stellard [Tue, 20 Dec 2016 17:26:34 +0000 (17:26 +0000)]
AMDGPU/SI: Make a function const

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290185 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.*
Tom Stellard [Tue, 20 Dec 2016 17:19:44 +0000 (17:19 +0000)]
AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.*

Reviewers: arsenm, nhaehnle, mareko

Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D27834

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290184 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Ensure we're only combining shuffles with legal mask types.
Simon Pilgrim [Tue, 20 Dec 2016 17:09:52 +0000 (17:09 +0000)]
[X86][SSE] Ensure we're only combining shuffles with legal mask types.

I haven't managed to get this to fail yet but its technically possible for the AND -> shuffle decomposition to result in illegal types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290183 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add a MachineMemOperand to MIMG instructions
Tom Stellard [Tue, 20 Dec 2016 15:52:17 +0000 (15:52 +0000)]
AMDGPU/SI: Add a MachineMemOperand to MIMG instructions

Summary:
Without a MachineMemOperand, the scheduler was assuming MIMG instructions
were ordered memory references, so no loads or stores could be reordered
across them.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27536

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290179 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix build with expensive checks enabled
Serge Pavlov [Tue, 20 Dec 2016 08:48:51 +0000 (08:48 +0000)]
Fix build with expensive checks enabled

Include of llvm/IR/Verifier.h was removed from HexagonCommonGEP.cpp in r289604
as unused. In fact it is required when expensive checks are enabled, because
it declared function `verifyFunction`, which is called in conditionally compiled
part of the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290170 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove extraneous space.
Rui Ueyama [Tue, 20 Dec 2016 05:49:56 +0000 (05:49 +0000)]
Remove extraneous space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290165 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM] Rework a loop in the CGSCC update logic to be more conservative and
Chandler Carruth [Tue, 20 Dec 2016 03:32:17 +0000 (03:32 +0000)]
[PM] Rework a loop in the CGSCC update logic to be more conservative and
clear. The current RefSCC can occur in exactly one position so we should
just enforce that and leverage the property rather than checking for it
anywhere.

This addresses review comments made on another patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290162 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM] Provide an initial, minimal port of the inliner to the new pass manager.
Chandler Carruth [Tue, 20 Dec 2016 03:15:32 +0000 (03:15 +0000)]
[PM] Provide an initial, minimal port of the inliner to the new pass manager.

This doesn't implement *every* feature of the existing inliner, but
tries to implement the most important ones for building a functional
optimization pipeline and beginning to sort out bugs, regressions, and
other problems.

Notable, but intentional omissions:
- No alloca merging support. Why? Because it isn't clear we want to do
  this at all. Active discussion and investigation is going on to remove
  it, so for simplicity I omitted it.
- No support for trying to iterate on "internally" devirtualized calls.
  Why? Because it adds what I suspect is inappropriate coupling for
  little or no benefit. We will have an outer iteration system that
  tracks devirtualization including that from function passes and
  iterates already. We should improve that rather than approximate it
  here.
- Optimization remarks. Why? Purely to make the patch smaller, no other
  reason at all.

The last one I'll probably work on almost immediately. But I wanted to
skip it in the initial patch to try to focus the change as much as
possible as there is already a lot of code moving around and both of
these *could* be skipped without really disrupting the core logic.

A summary of the different things happening here:

1) Adding the usual new PM class and rigging.

2) Fixing minor underlying assumptions in the inline cost analysis or
   inline logic that don't generally hold in the new PM world.

3) Adding the core pass logic which is in essence a loop over the calls
   in the nodes in the call graph. This is a bit duplicated from the old
   inliner, but only a handful of lines could realistically be shared.
   (I tried at first, and it really didn't help anything.) All told,
   this is only about 100 lines of code, and most of that is the
   mechanics of wiring up analyses from the new PM world.

4) Updating the LazyCallGraph (in the new PM) based on the *newly
   inlined* calls and references. This is very minimal because we cannot
   form cycles.

5) When inlining removes the last use of a function, eagerly nuking the
   body of the function so that any "one use remaining" inline cost
   heuristics are immediately refined, and queuing these functions to be
   completely deleted once inlining is complete and the call graph
   updated to reflect that they have become dead.

6) After all the inlining for a particular function, updating the
   LazyCallGraph and the CGSCC pass manager to reflect the
   function-local simplifications that are done immediately and
   internally by the inline utilties. These are the exact same
   fundamental set of CG updates done by arbitrary function passes.

7) Adding a bunch of test cases to specifically target CGSCC and other
   subtle aspects in the new PM world.

Many thanks to the careful review from Easwaran and Sanjoy and others!

Differential Revision: https://reviews.llvm.org/D24226

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290161 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReapply r289926: attempt to fix windows build
Adrian Prantl [Tue, 20 Dec 2016 02:33:30 +0000 (02:33 +0000)]
Reapply r289926: attempt to fix windows build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290158 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IR] Remove the DIExpression field from DIGlobalVariable.
Adrian Prantl [Tue, 20 Dec 2016 02:09:43 +0000 (02:09 +0000)]
[IR] Remove the DIExpression field from DIGlobalVariable.

This patch implements PR31013 by introducing a
DIGlobalVariableExpression that holds a pair of DIGlobalVariable and
DIExpression.

Currently, DIGlobalVariables holds a DIExpression. This is not the
best way to model this:

(1) The DIGlobalVariable should describe the source level variable,
    not how to get to its location.

(2) It makes it unsafe/hard to update the expressions when we call
    replaceExpression on the DIGLobalVariable.

(3) It makes it impossible to represent a global variable that is in
    more than one location (e.g., a variable with multiple
    DW_OP_LLVM_fragment-s).  We also moved away from attaching the
    DIExpression to DILocalVariable for the same reasons.

This reapplies r289902 with additional testcase upgrades and a change
to the Bitcode record for DIGlobalVariable, that makes upgrading the
old format unambiguous also for variables without DIExpressions.

<rdar://problem/29250149>
https://llvm.org/bugs/show_bug.cgi?id=31013
Differential Revision: https://reviews.llvm.org/D26769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290153 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[ObjectYAML] Support for DWARF debug_info section"
Chris Bieneman [Tue, 20 Dec 2016 00:42:06 +0000 (00:42 +0000)]
Revert "[ObjectYAML] Support for DWARF debug_info section"

This reverts commit r290147.

This commit is breaking a bot (http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/621). I don't have time to investigate at the moment, so I'll revert for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290148 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ObjectYAML] Support for DWARF debug_info section
Chris Bieneman [Tue, 20 Dec 2016 00:26:24 +0000 (00:26 +0000)]
[ObjectYAML] Support for DWARF debug_info section

This patch adds support for YAML<->DWARF for debug_info sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290147 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd ARM support to update_llc_test_checks.py
Eli Friedman [Mon, 19 Dec 2016 23:09:51 +0000 (23:09 +0000)]
Add ARM support to update_llc_test_checks.py

Just the minimal support to get it working at the moment.

Includes checks for test/CodeGen/ARM/vzip.ll as an example.

Differential Revision: https://reviews.llvm.org/D27829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290144 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LV] Sink tripcount query to where it's actually used. NFC.
Michael Kuperstein [Mon, 19 Dec 2016 22:47:52 +0000 (22:47 +0000)]
[LV] Sink tripcount query to where it's actually used. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290142 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ObjectYAML] Support for DWARF Pub Sections
Chris Bieneman [Mon, 19 Dec 2016 22:22:12 +0000 (22:22 +0000)]
[ObjectYAML] Support for DWARF Pub Sections

This patch adds support for YAML<->DWARF round tripping for pub* section data. The patch supports both GNU and non-GNU style entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290139 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libfuzzer] dump_coverage command line flag
Mike Aizatsky [Mon, 19 Dec 2016 22:18:08 +0000 (22:18 +0000)]
[libfuzzer] dump_coverage command line flag

Reviewers: kcc, vitalybuka

Differential Revision: https://reviews.llvm.org/D27942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290138 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TargetInstrInfo] replace redundant expression in getMemOpBaseRegImmOfs
Michael LeMay [Mon, 19 Dec 2016 21:02:41 +0000 (21:02 +0000)]
[TargetInstrInfo] replace redundant expression in getMemOpBaseRegImmOfs

Summary:
The expression for computing the return value of getMemOpBaseRegImmOfs has only
one possible value. The other value would result in a return earlier in the
function. This patch replaces the expression with its only possible value.

Reviewers: sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D27437

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290133 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake a function to correctly extract the DW_AT_high_pc given the low pc value.
Greg Clayton [Mon, 19 Dec 2016 20:36:41 +0000 (20:36 +0000)]
Make a function to correctly extract the DW_AT_high_pc given the low pc value.

DWARF 4 and later supports encoding the PC as an address or as as offset from the low PC. Clients using DWARFDie should be insulated from how to extract the high PC value. This function takes care of extracting the form value and looking for the correct form.

Differential Revision: https://reviews.llvm.org/D27885

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290131 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] use commutative matcher for pattern with commutative operators
Sanjay Patel [Mon, 19 Dec 2016 18:35:37 +0000 (18:35 +0000)]
[InstCombine] use commutative matcher for pattern with commutative operators

This is a case that was missed in:
https://reviews.llvm.org/rL290067
...and it would regress if we fix operand complexity (PR28296).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290127 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] add folds for icmp (umin|umax X, Y), X
Sanjay Patel [Mon, 19 Dec 2016 17:32:37 +0000 (17:32 +0000)]
[InstCombine] add folds for icmp (umin|umax X, Y), X

This is a follow-up to:
https://reviews.llvm.org/rL289855 (https://reviews.llvm.org/D27531)
https://reviews.llvm.org/rL290111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290118 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago [LoopVersioning] Require loop-simplify form for loop versioning.
Florian Hahn [Mon, 19 Dec 2016 17:13:37 +0000 (17:13 +0000)]
 [LoopVersioning] Require loop-simplify form for loop versioning.

Summary:
Requiring loop-simplify form for loop versioning ensures that the
runtime check block always dominates the exit block.

This patch closes #30958 (https://llvm.org/bugs/show_bug.cgi?id=30958).

Reviewers: silviu.baranga, hfinkel, anemet, ashutosh.nema

Subscribers: ashutosh.nema, mzolotukhin, efriedma, hfinkel, llvm-commits

Differential Revision: https://reviews.llvm.org/D27469

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290116 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AMDGPU] When unifying metadata, add operands to named metadata individually
Konstantin Zhuravlyov [Mon, 19 Dec 2016 16:54:24 +0000 (16:54 +0000)]
[AMDGPU] When unifying metadata, add operands to named metadata individually

Differential Revision: https://reviews.llvm.org/D27725

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290114 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] add folds for icmp (smax X, Y), X
Sanjay Patel [Mon, 19 Dec 2016 16:28:53 +0000 (16:28 +0000)]
[InstCombine] add folds for icmp (smax X, Y), X

This is a follow-up to:
https://reviews.llvm.org/rL289855 (D27531)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290111 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilence unused warning.
Daniel Jasper [Mon, 19 Dec 2016 14:24:22 +0000 (14:24 +0000)]
Silence unused warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290109 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Add more checks to test
Diana Picus [Mon, 19 Dec 2016 14:08:11 +0000 (14:08 +0000)]
[ARM] GlobalISel: Add more checks to test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290108 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Minor style fixup in test
Diana Picus [Mon, 19 Dec 2016 14:08:06 +0000 (14:08 +0000)]
[ARM] GlobalISel: Minor style fixup in test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290107 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Lower i8 and i16 register args
Diana Picus [Mon, 19 Dec 2016 14:08:02 +0000 (14:08 +0000)]
[ARM] GlobalISel: Lower i8 and i16 register args

This allows lowering i8 and i16 arguments if they can fit in the registers. Note
that the lowering is incomplete - ABI extensions are handled in a subsequent
patch.

(Last part of)
Differential Revision: https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290106 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Allow i8 and i16 adds
Diana Picus [Mon, 19 Dec 2016 14:07:56 +0000 (14:07 +0000)]
[ARM] GlobalISel: Allow i8 and i16 adds

Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290105 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Select i8 and i16 copies
Diana Picus [Mon, 19 Dec 2016 14:07:50 +0000 (14:07 +0000)]
[ARM] GlobalISel: Select i8 and i16 copies

Teach the instruction selector that it's ok to copy small values from physical
registers.

First part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290104 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Power9] Processor Model for Scheduling
Ehsan Amiri [Mon, 19 Dec 2016 13:35:45 +0000 (13:35 +0000)]
[Power9] Processor Model for Scheduling

PWR9 processor model for instruction scheduling. A subsequent patch will migrate
PWR9 to Post RA MIScheduler.
https://reviews.llvm.org/D24525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290102 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Restore minimum profit check accidentally changed in r290024
Malcolm Parsons [Mon, 19 Dec 2016 12:37:26 +0000 (12:37 +0000)]
[Hexagon] Restore minimum profit check accidentally changed in r290024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290100 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Lower more than 4 arguments
Diana Picus [Mon, 19 Dec 2016 11:55:41 +0000 (11:55 +0000)]
[ARM] GlobalISel: Lower more than 4 arguments

This adds support for lowering more than 4 arguments (although still i32 only).
It uses the handleAssignments / ValueHandler infrastructure extracted from
the AArch64 backend in r288658.

Differential Revision: https://reviews.llvm.org/D27195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290098 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for functime...
Sam Kolton [Mon, 19 Dec 2016 11:43:15 +0000 (11:43 +0000)]
AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for functime metadata V2.0

Summary:
Added pair of directives .hsa_code_object_metadata/.end_hsa_code_object_metadata.
Between them user can put YAML string that would be directly put to the generated note. E.g.:
'''
.hsa_code_object_metadata
    {
        amd.MDVersion: [ 2, 0 ]
    }
.end_hsa_code_object_metadata
'''
Based on D25046

Reviewers: vpykhtin, nhaustov, yaxunl, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, mgorny, tony-tye

Differential Revision: https://reviews.llvm.org/D27619

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290097 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] GlobalISel: Support loading from the stack
Diana Picus [Mon, 19 Dec 2016 11:26:31 +0000 (11:26 +0000)]
[ARM] GlobalISel: Support loading from the stack

Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290096 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Make MachineInstr::isIdenticalTo() symmetric.
Bjorn Pettersson [Mon, 19 Dec 2016 11:20:57 +0000 (11:20 +0000)]
[CodeGen] Make MachineInstr::isIdenticalTo() symmetric.

Summary:
MachineInstr::isIdenticalTo() is for some reason not
symmetric when comparing bundles, which gives us the
property:

  I1->isIdenticalTo(*I2) != I2->isIdenticalTo(*I1)

when comparing bundles where one bundle is longer than
the other.

This patch makes sure that bundles of different length
always are considered as not being identical. Thus, the
result of the comparison will be the same regardless of
which side that happens to be to the left.

Reviewers: dexonsmith, jonpa, andrew.w.kaylor

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D27508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290095 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[XRay] Fix assertion failure on empty machine basic blocks (PR 31424)
Dean Michael Berris [Mon, 19 Dec 2016 09:20:38 +0000 (09:20 +0000)]
[XRay] Fix assertion failure on empty machine basic blocks (PR 31424)

The original version of the code in XRayInstrumentation.cpp assumed that
functions may not have empty machine basic blocks (or that the first one
couldn't be). This change addresses that by special-casing that specific
situation.

We provide two .mir test-cases to make sure we're handling this
appropriately.

Fixes llvm.org/PR31424.

Reviewers: chandlerc

Subscribers: varno, llvm-commits

Differential Revision: https://reviews.llvm.org/D27913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290091 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] When recognizing vector loads or VZEXT_LOAD in selectScalarSSELoad make sure...
Craig Topper [Mon, 19 Dec 2016 08:35:56 +0000 (08:35 +0000)]
[X86] When recognizing vector loads or VZEXT_LOAD in selectScalarSSELoad make sure we pass the load's user rather than load itself to the second operand of IsLegalToFold.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290089 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TableGen] Use 'unsigned' instead of 'bool' in a place where the code conditionally...
Craig Topper [Mon, 19 Dec 2016 08:35:08 +0000 (08:35 +0000)]
[TableGen] Use 'unsigned' instead of 'bool' in a place where the code conditionally assigns numeric values. They happen to be 0 and 1 so this is NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290088 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd files I seem to have dropped in my revert (r290086).
Daniel Jasper [Mon, 19 Dec 2016 08:32:13 +0000 (08:32 +0000)]
Add files I seem to have dropped in my revert (r290086).

Sorry!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290087 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert @llvm.assume with operator bundles (r289755-r289757)
Daniel Jasper [Mon, 19 Dec 2016 08:22:17 +0000 (08:22 +0000)]
Revert @llvm.assume with operator bundles (r289755-r289757)

This creates non-linear behavior in the inliner (see more details in
r289755's commit thread).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Remove all of the patterns that use X86ISD:FAND/FXOR/FOR/FANDN except for the...
Craig Topper [Mon, 19 Dec 2016 00:42:28 +0000 (00:42 +0000)]
[X86] Remove all of the patterns that use X86ISD:FAND/FXOR/FOR/FANDN except for the ones needed for SSE1. Anything SSE2 or above uses the integer ISD opcode.

This removes 11721 bytes from the DAG isel table or 2.2%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290073 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FileCheck] Fix --strict-whitespace --match-full-lines -- add test-case
Tom de Vries [Sun, 18 Dec 2016 21:04:47 +0000 (21:04 +0000)]
[FileCheck] Fix --strict-whitespace --match-full-lines -- add test-case

Add test-case that was missing in "[FileCheck] Fix --strict-whitespace
--match-full-lines" commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290070 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FileCheck] Fix --strict-whitespace --match-full-lines
Tom de Vries [Sun, 18 Dec 2016 20:45:59 +0000 (20:45 +0000)]
[FileCheck] Fix --strict-whitespace --match-full-lines

Make sure FileCheck --strict-whitespace --match-full-lines translates
'CHECK: bla ' into pattern '^ bla $' instead of pattern '^bla$'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290069 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PDB] Don't use the long type
David Majnemer [Sun, 18 Dec 2016 20:10:50 +0000 (20:10 +0000)]
[PDB] Don't use the long type

Long is not the same size across a number of the platforms we support.
Use unsigned int here instead, it is more appropriate because
overflow/wrap-around is possible and, in this case, expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290068 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] use commutative matchers for patterns with commutative operators
Sanjay Patel [Sun, 18 Dec 2016 18:49:48 +0000 (18:49 +0000)]
[InstCombine] use commutative matchers for patterns with commutative operators

Background/motivation - I was circling back around to:
https://llvm.org/bugs/show_bug.cgi?id=28296

I made a simple patch for that and noticed some regressions, so added test cases for
those with rL281055, and this is hopefully the minimal fix for just those cases.

But as you can see from the surrounding untouched folds, we are missing commuted patterns
all over the place, and of course there are no regression tests to cover any of those cases.

We could sprinkle "m_c_" dust all over this file and catch most of the missing folds, but
then we still wouldn't have test coverage, and we'd still miss some fraction of commuted
patterns because they require adjustments to the match order.

I'm aware of the concern about the potential compile-time performance impact of adding
matches like this (currently being discussed on llvm-dev), but I don't think there's any
evidence yet to suggest that handling commutative pattern matching more thoroughly is not
a worthwhile goal of InstCombine.

Differential Revision: https://reviews.llvm.org/D24419

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290067 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r289955 and r289962. This is causing lots of ASAN failures for us.
Daniel Jasper [Sun, 18 Dec 2016 14:36:38 +0000 (14:36 +0000)]
Revert r289955 and r289962. This is causing lots of ASAN failures for us.

Not sure whether it causes and ASAN false positive or whether it
actually leads to incorrect code or whether it even exposes bad code.
Hans, I'll get you instructions to reproduce this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290066 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.
Michael Zuckerman [Sun, 18 Dec 2016 14:29:00 +0000 (14:29 +0000)]
[X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.

Commit on behalf of Gadi Haber

Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified.
The changed encodings are validated with XED.
Rviewers: delena, igorb

Differential revision: https://reviews.llvm.org/D27802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290065 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Add support for combining target shuffles to SHUFPS.
Simon Pilgrim [Sun, 18 Dec 2016 14:26:02 +0000 (14:26 +0000)]
[X86][SSE] Add support for combining target shuffles to SHUFPS.

As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290064 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FileCheck] Fix comment in ReadCheckFile
Tom de Vries [Sun, 18 Dec 2016 09:41:20 +0000 (09:41 +0000)]
[FileCheck] Fix comment in ReadCheckFile

The comment in ReadCheckFile claims that both leading and trailing whitespace
are removed, but the associated statement only removes leading whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290061 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations if they...
Craig Topper [Sun, 18 Dec 2016 07:54:23 +0000 (07:54 +0000)]
[X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations if they are available. This will allow a bunch of patterns to be removed.

These nodes are only emitted for lowering FABS/FNEG/FNABS/FCOPYSIGN. Ideally we just wouldn't create these nodes if SSE2 or higher is available, but it was simple to just convert them in DAG combine.

For SSE2, AVX, and AVX512 with DQI this is no functional change as the execution domain fixing pass ensures the right domain is selected regardless of the ISD opcode.

For AVX-512 without DQI we end up using integer instructions since the floating point versions aren't available. But we were already doing that for any logical operations in code that didn't come from FABS/FNEG/FNABS/FCOPYSIGN so this seems no worse. And we get the benefit of being able to fold broadcasts now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290060 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when DQI...
Craig Topper [Sun, 18 Dec 2016 06:23:14 +0000 (06:23 +0000)]
[AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when DQI and VLX instructions are available.

This can give the register allocator more registers to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290057 91177308-0d34-0410-b5e6-96231b3b80d8