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Sam Clegg [Wed, 21 Jun 2017 20:58:17 +0000 (20:58 +0000)]
Rename WinCOFFStreamer.cpp -> MCWinCOFFStreamer.cpp
For consistency with other MC*Streamer.cpp files and
the header file.
Differential Revision: https://reviews.llvm.org/D34466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305952
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Nirav Dave [Wed, 21 Jun 2017 20:50:07 +0000 (20:50 +0000)]
Add Aarch64 ldst-opt test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305951
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Davide Italiano [Wed, 21 Jun 2017 20:42:34 +0000 (20:42 +0000)]
[Target/Mips] Add test associated with r305949.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305950
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Davide Italiano [Wed, 21 Jun 2017 20:40:27 +0000 (20:40 +0000)]
[Target] Implement the ".rdata" MIPS assembly directive.
Patch by John Baldwin < jhb at freebsd dot org >!
Differential Revision: https://reviews.llvm.org/D34452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305949
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Davide Italiano [Wed, 21 Jun 2017 20:36:32 +0000 (20:36 +0000)]
[Solaris] emit .init_array instead of .ctors on Solaris (Sparc/x86)
Patch by Fedor Sergeev.
Differential Revision: https://reviews.llvm.org/D33868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305948
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Craig Topper [Wed, 21 Jun 2017 19:39:35 +0000 (19:39 +0000)]
[Reassociate] Use early returns in a couple places to reduce indentation and improve readability. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305946
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Craig Topper [Wed, 21 Jun 2017 19:39:33 +0000 (19:39 +0000)]
[Reassociate] Const correct a helper function. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305945
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Wolfgang Pieb [Wed, 21 Jun 2017 19:37:44 +0000 (19:37 +0000)]
[DWARF] Support for DW_FORM_strx3 and complete support for DW_FORM_strx{1,2,4}
(consumer).
Reviewer: aprantl
Differential Revision: https://reviews.llvm.org/D34418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305944
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Krzysztof Parzyszek [Wed, 21 Jun 2017 19:21:30 +0000 (19:21 +0000)]
[Hexagon] Handle more types of immediate operands in expand-condsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305943
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Craig Topper [Wed, 21 Jun 2017 18:57:00 +0000 (18:57 +0000)]
[InstCombine] Cleanup using commutable matchers. Make a couple helper methods standalone static functions. Put 'if' around variable declaration instead of after. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305941
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whitequark [Wed, 21 Jun 2017 18:46:50 +0000 (18:46 +0000)]
Add a "probe-stack" attribute
This attribute is used to ensure the guard page is triggered on stack
overflow. Stack frames larger than the guard page size will generate
a call to __probestack to touch each page so the guard page won't
be skipped.
Reviewed By: majnemer
Differential Revision: https://reviews.llvm.org/D34386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305939
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Michael Kruse [Wed, 21 Jun 2017 18:25:37 +0000 (18:25 +0000)]
[BasicAA] Use MayAlias instead of PartialAlias for fallback.
Using various methods, BasicAA tries to determine whether two
GetElementPtr memory locations alias when its base pointers are known
to be equal. When none of its heuristics are applicable, it falls back
to PartialAlias to, according to a comment, protect TBAA making a wrong
decision in case of unions and malloc. PartialAlias is not correct,
because a PartialAlias result implies that some, but not all, bytes
overlap which is not necessarily the case here.
AAResults returns the first analysis result that is not MayAlias.
BasicAA is always the first alias analysis. When it returns
PartialAlias, no other analysis is queried to give a more exact result
(which was the intention of returning PartialAlias instead of MayAlias).
For instance, ScopedAA could return a more accurate result.
The PartialAlias hack was introduced in r131781 (and re-applied in
r132632 after some reverts) to fix llvm.org/PR9971 where TBAA returns a
wrong NoAlias result due to a union. A test case for the malloc case
mentioned in the comment was not provided and I don't think it is
affected since it returns an omnipotent char anyway.
Since r303851 (https://reviews.llvm.org/D33328) clang does emit specific
TBAA for unions anymore (but "omnipotent char" instead). Hence, the
PartialAlias workaround is not required anymore.
This patch passes the test-suite and check-llvm/check-clang of a
self-hoisted build on x64.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D34318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305938
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Peter Collingbourne [Wed, 21 Jun 2017 18:23:19 +0000 (18:23 +0000)]
Object: Have the irsymtab builder take a string table builder. NFCI.
This will be needed in order to share the irsymtab string table with
the bitcode string table.
Differential Revision: https://reviews.llvm.org/D33971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305937
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Sanjay Patel [Wed, 21 Jun 2017 18:20:52 +0000 (18:20 +0000)]
[CGP, memcmp] replace CreateZextOrTrunc with CreateZext because it can never trunc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305936
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Sanjay Patel [Wed, 21 Jun 2017 18:06:13 +0000 (18:06 +0000)]
[CGP] fix variables to be unsigned in memcmp expansion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305935
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Dehao Chen [Wed, 21 Jun 2017 17:57:43 +0000 (17:57 +0000)]
Do not inline recursive direct calls in sample loader pass.
Summary: r305009 disables recursive inlining for indirect calls in sample loader pass. The same logic applies to direct recursive calls.
Reviewers: iteratee, davidxl
Reviewed By: iteratee
Subscribers: sanjoy, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D34456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305934
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Reid Kleckner [Wed, 21 Jun 2017 17:25:56 +0000 (17:25 +0000)]
[PDB] Add symbols to the PDB
Summary:
The main complexity in adding symbol records is that we need to
"relocate" all the type indices. Type indices do not have anything like
relocations, an opaque data structure describing where to find existing
type indices for fixups. The linker just has to "know" where the type
references are in the symbol records. I added an overload of
`discoverTypeIndices` that works on symbol records, and it seems to be
able to link the standard library.
Reviewers: zturner, ruiu
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D34432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305933
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Lei Huang [Wed, 21 Jun 2017 17:17:56 +0000 (17:17 +0000)]
[PowerPC] define target hook isReallyTriviallyReMaterializable()
Define target hook isReallyTriviallyReMaterializable() to explicitly specify
PowerPC instructions that are trivially rematerializable. This will allow
the MachineLICM pass to accurately identify PPC instructions that should always
be hoisted.
Differential Revision: https://reviews.llvm.org/D34255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305932
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Sanjay Patel [Wed, 21 Jun 2017 17:06:24 +0000 (17:06 +0000)]
[x86] set the datalayout to match the RUN line triple; NFC
I don't think there's any visible difference from having the wrong layout
for the 32-bit case at this point, but that could change in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305931
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Craig Topper [Wed, 21 Jun 2017 16:32:35 +0000 (16:32 +0000)]
[InstCombine] Add range metadata to cttz/ctlz/ctpop intrinsic calls based on known bits
Summary:
I noticed that passing known bits across these intrinsics isn't great at capturing the information we really know. Turning known bits of the input into known bits of a count output isn't able to convey a lot of what we really know.
This patch adds range metadata to these intrinsics based on the known bits.
Currently the patch punts if we already have range metadata present.
Reviewers: spatel, RKSimon, davide, majnemer
Reviewed By: RKSimon
Subscribers: sanjoy, hfinkel, llvm-commits
Differential Revision: https://reviews.llvm.org/D32582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305927
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Craig Topper [Wed, 21 Jun 2017 16:07:13 +0000 (16:07 +0000)]
[InstCombine] Don't let folding (select (icmp eq (and X, C1), 0), Y, (or Y, C2)) create more instructions than it removes
Summary:
Previously this folding had no checks to see if it was going to result in less instructions. This was pointed out during the review of D34184
This patch adds code to count how many instructions its going to create vs how many its going to remove so we can make a proper decision.
Reviewers: spatel, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305926
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Craig Topper [Wed, 21 Jun 2017 16:07:09 +0000 (16:07 +0000)]
[Reassociate] Support xor reassociating for splat vectors
Summary: This patch adds support for xors of splat vectors.
Reviewers: mcrosier
Reviewed By: mcrosier
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305925
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Dmitry Preobrazhensky [Wed, 21 Jun 2017 16:00:54 +0000 (16:00 +0000)]
[AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failures
See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509
Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin
Differential Revision: https://reviews.llvm.org/D34360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305923
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Nirav Dave [Wed, 21 Jun 2017 15:40:43 +0000 (15:40 +0000)]
[DAG] Move BaseIndexOffset into separate Libarary. NFC.
Move BaseIndexOffset analysis out of DAGCombiner for use in other
files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305921
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David Blaikie [Wed, 21 Jun 2017 15:20:46 +0000 (15:20 +0000)]
ClangFormat some changes from r305226
Post commit review feedback from Justin Bogner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305919
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Christof Douma [Wed, 21 Jun 2017 15:18:39 +0000 (15:18 +0000)]
[AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.
Added test file for ARMv8.1 LSE Atomics that I forgot to include in
commit r305893.
Patch by Ananth Jasty.
Differential Revision: https://reviews.llvm.org/D33586
Change-Id: Ic1ad8ed87c1b584c4c791b459a686c866a3c3087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305918
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Nirav Dave [Wed, 21 Jun 2017 15:07:30 +0000 (15:07 +0000)]
[DAG] Remove Node csonstruction from BaseIndexOffset match. NFCI.
Move GlobalAddress Offset decomposition from initial match into
comparision check and removing the possibility of constructing a new
offseted global address when examining addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305917
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Simon Pilgrim [Wed, 21 Jun 2017 14:51:23 +0000 (14:51 +0000)]
[X86][SSE] Dropped -mcpu from 256-bit vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305916
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Dmitry Preobrazhensky [Wed, 21 Jun 2017 14:41:34 +0000 (14:41 +0000)]
[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src
See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D34003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305915
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Sanjay Patel [Wed, 21 Jun 2017 14:27:11 +0000 (14:27 +0000)]
[x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305914
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Simon Pilgrim [Wed, 21 Jun 2017 14:23:02 +0000 (14:23 +0000)]
[X86][SSE] Dropped -mcpu from 128-bit vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305913
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Simon Pilgrim [Wed, 21 Jun 2017 13:46:42 +0000 (13:46 +0000)]
[X86][SSE] Regenerate merge store tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305910
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Simon Pilgrim [Wed, 21 Jun 2017 13:45:33 +0000 (13:45 +0000)]
[X86][SSE] Dropped -mcpu from vector blend shuffle tests and regenerate
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305909
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Simon Pilgrim [Wed, 21 Jun 2017 13:26:52 +0000 (13:26 +0000)]
[X86][SSE] Dropped -mcpu from vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305908
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Simon Pilgrim [Wed, 21 Jun 2017 13:17:14 +0000 (13:17 +0000)]
[X86][SSE] Dropped -mcpu from vector zero extend tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305907
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Simon Pilgrim [Wed, 21 Jun 2017 13:15:41 +0000 (13:15 +0000)]
[X86][SSE] Dropped -mcpu from variable shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305906
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:56 +0000 (12:58 +0000)]
[X86][AVX] Add AVX1 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305905
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:19 +0000 (12:58 +0000)]
[X86][SSE] Add SSE2/SSE42 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305904
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Zvi Rackover [Wed, 21 Jun 2017 11:21:43 +0000 (11:21 +0000)]
[X86] Rerun the update_llc_test_checks tool on test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305897
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Pavel Labath [Wed, 21 Jun 2017 11:10:02 +0000 (11:10 +0000)]
Fix build after r305892
Make sure to #include <cerrno> in Support/Errno.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305895
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Christof Douma [Wed, 21 Jun 2017 10:58:31 +0000 (10:58 +0000)]
[AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.
Implemented support to AArch64 codegen for ARMv8.1 Large System
Extensions atomic instructions. Where supported, these instructions can
provide atomic operations with higher performance.
Currently supported operations include: fetch_add, fetch_or, fetch_xor,
fetch_smin, fetch_min/max (signed and unsigned), swap, and
compare_exchange.
This implementation implies sequential-consistency ordering, more
relaxed ordering is under development.
Subtarget->hasLSE is currently supported for Cavium ThunderX2T99.
Patch by Ananth Jasty.
Differential Revision: https://reviews.llvm.org/D33586
Change-Id: I82f6d3d64255622791ceb0715b7ab9f4dc4d4b2c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305893
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Pavel Labath [Wed, 21 Jun 2017 10:55:34 +0000 (10:55 +0000)]
[Support] Add RetryAfterSignal helper function
Summary:
This function retries an operation if it was interrupted by a signal
(failed with EINTR). It's inspired by the TEMP_FAILURE_RETRY macro in
glibc, but I've turned that into a template function. I've also added a
fail-value argument, to enable the function to be used with e.g.
fopen(3), which is documented to fail for any reason that open(2) can
fail (which includes EINTR).
The main user of this function will be lldb, but there were also a
couple of uses within llvm that I could simplify using this function.
Reviewers: zturner, silvas, joerg
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D33895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305892
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Florian Hahn [Wed, 21 Jun 2017 09:51:52 +0000 (09:51 +0000)]
[AArch64] Add early exit to promoteLoadFromStore.
There should be at most a single kill flag for the
promoted operand between the store/load pair.
Discussed in https://reviews.llvm.org/D34402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305889
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Strahinja Petrovic [Wed, 21 Jun 2017 09:25:51 +0000 (09:25 +0000)]
[MIPS] Fix for selecting of DINS/INS instruction
This patch adds one more condition in selection DINS/INS
instruction, which fixes MultiSource/Applications/JM/ldecod/
for mips32r2 (and mips64r2 n32 abi).
Differential Revision: https://reviews.llvm.org/D33725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305888
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Javed Absar [Wed, 21 Jun 2017 09:10:10 +0000 (09:10 +0000)]
Use range-loop in machine-scheduler. NFCI.
Converts to range-loop usage in machine scheduler.
This makes the code neater and easier to read,
and also keeps pace of the machine scheduler
implementation with C++11 features.
Reviewed by: Matthias Braun
Differential Revision: https://reviews.llvm.org/D34320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305887
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Sam Kolton [Wed, 21 Jun 2017 08:53:38 +0000 (08:53 +0000)]
[AMDGPU] SDWA: merge VI and GFX9 pseudo instructions
Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9.
Reviewers: dp, arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov
Differential Revision: https://reviews.llvm.org/D34026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305886
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Florian Hahn [Wed, 21 Jun 2017 08:47:23 +0000 (08:47 +0000)]
[AArch64] Preserve register flags when promoting a load from store.
Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved.
This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).
Reviewers: MatzeB, t.p.northover, junbuml
Reviewed By: MatzeB
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305885
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Guy Blank [Wed, 21 Jun 2017 07:38:41 +0000 (07:38 +0000)]
[DAGCombiner] Add another combine from build vector to shuffle
Add support for combining a build vector to a shuffle.
When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305883
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Max Kazantsev [Wed, 21 Jun 2017 07:28:13 +0000 (07:28 +0000)]
[SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation time
MulOpsInlineThreshold option of SCEV is defaulted to 1000, which is inadequately high.
When constructing SCEVs of expressions like:
x1 = a * a
x2 = x1 * x1
x3 = x2 * x2
...
We actually have huge SCEVs with max allowed amount of operands inlined.
Such expressions are easy to get from unrolling of loops looking like
x = a
for (i = 0; i < n; i++)
x = x * x
Or more tricky cases where big powers are involved. If some non-linear analysis
tries to work with a SCEV that has 1000 operands, it may lead to excessively long
compilation. The attached test does not pass within 1 minute with default threshold.
This patch decreases its default value to 32, which looks much more reasonable if we
use analyzes with complexity O(N^2) or O(N^3) working with SCEV.
Differential Revision: https://reviews.llvm.org/D34397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305882
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Rafael Espindola [Wed, 21 Jun 2017 06:42:56 +0000 (06:42 +0000)]
Simplify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305881
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Dean Michael Berris [Wed, 21 Jun 2017 06:39:42 +0000 (06:39 +0000)]
[XRay] Reduce synthetic references emitted by XRay
Summary:
When we're building with XRay instrumentation, we use a trick that
preserves references from the function to a function sled index. This
index table lives in a separate section, and without this trick the
linker is free to garbage-collect this section and all the segments it
refers to. Until we're able to tell the linkers to preserve these
sections, we use this reference trick to keep around both the index and
the entries in the instrumentation map.
Before this change we emitted both a synthetic reference to the label in
the instrumentation map, and to the entry in the function map index.
This change removes the first synthetic reference and only emits one
synthetic reference to the index -- the index entry has the references
to the labels in the instrumentation map, so the linker will still
preserve those if the function itself is preserved.
This reduces the amount of synthetic references we emit from 16 bytes to
just 8 bytes in x86_64, and similarly to other platforms.
Reviewers: dblaikie
Subscribers: javed.absar, kpw, pelikan, llvm-commits
Differential Revision: https://reviews.llvm.org/D34340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305880
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Serguei Katkov [Wed, 21 Jun 2017 06:38:23 +0000 (06:38 +0000)]
[ImplicitNullChecks] Uphold an invariant in areMemoryOpsAliased
Right now areMemoryOpsAliased has an assertion justified as:
MMO1 should have a value due it comes from operation we'd like to use
as implicit null check.
assert(MMO1->getValue() && "MMO1 should have a Value!");
However, it is possible for that invariant to not be upheld in the
following situation (conceptually):
Null check %RAX
NotNullSucc:
%RAX = LEA %RSP, 16 // I0
%RDX = MOV64rm %RAX // I1
With the current code, we will have an early exit from
ImplicitNullChecks::isSuitableMemoryOp on I0 with SR_Unsuitable.
However, I1 will look plausible (since it loads from %RAX) and
will go ahead and call areMemoryOpsAliased(I1, I0). This will cause
us to fail the assert mentioned above since I1 does not load from an
IR level value and thus is allowed to have a non-Value base address.
The fix is to bail out earlier whenever we see an unsuitable
instruction overwrite PointerReg. This would guarantee that when we
call areMemoryOpsAliased, we're guaranteed to be looking at an
instruction that loads from or stores to an IR level value.
Original Patch Author: sanjoy
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305879
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Davide Italiano [Tue, 20 Jun 2017 22:57:40 +0000 (22:57 +0000)]
[NewGVN] Fix a bug that made the store verifier less effective.
We weren't actually checking for duplicated stores, as the condition
was always actually false. This was found by Coverity, and I have
no clue how to trigger this in real-world code (although I
tried for a bit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305867
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Kevin Enderby [Tue, 20 Jun 2017 22:55:11 +0000 (22:55 +0000)]
Updated llvm-objdump with Mach-O files and the -objc-meta-data option so
that it symbolically prints the superclass when it has dyld bind info for it.
rdar://
7638823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305866
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Rafael Espindola [Tue, 20 Jun 2017 22:53:29 +0000 (22:53 +0000)]
clang-format a region.
It will make a followup patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305865
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Lang Hames [Tue, 20 Jun 2017 22:18:02 +0000 (22:18 +0000)]
Add a cantFail overload for Expected-reference (Expected<T&>) types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305863
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Reid Kleckner [Tue, 20 Jun 2017 21:19:22 +0000 (21:19 +0000)]
[codeview] YAMLize all section offsets and indices in symbol records
We forgot to serialize these because llvm-readobj didn't dump them. They
are typically all zeros in an object file. The linker fills them in with
relocations before adding them to the PDB. Now we can properly round
trip these symbols through pdb2yaml -> yaml2pdb.
I made these fields optional with a zero default so that we can elide
them from our test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305857
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Adrian Prantl [Tue, 20 Jun 2017 21:14:29 +0000 (21:14 +0000)]
Revert "Add previously accidentally uncommitted testcase for r305599."
This reverts commit r305852.
The testcase already exists but I moved it to the X86 directory on a
using a different machine and got confused...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305856
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Rafael Espindola [Tue, 20 Jun 2017 21:11:58 +0000 (21:11 +0000)]
Make this test a bit more strict. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305855
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Adrian Prantl [Tue, 20 Jun 2017 21:08:52 +0000 (21:08 +0000)]
Fix a crash in DwarfDebug::validThroughout.
The instruction it falls over on is an IMPLICT_DEF that also happens
to be the only instruction in its lexical scope. That LexicalScope has
never been created because its range is empty. This patch skips over
all meta-instructions instead of just DBG_VALUEs.
Thanks to David Blaikie for providing a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305853
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Adrian Prantl [Tue, 20 Jun 2017 21:08:19 +0000 (21:08 +0000)]
Add previously accidentally uncommitted testcase for r305599.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305852
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Kevin Enderby [Tue, 20 Jun 2017 21:00:25 +0000 (21:00 +0000)]
Change llvm-objdump with Mach-O files and the -info-plist option with the
-no-leading-headers option so that it does not print the leading header.
rdar://
27378808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305849
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Anna Thomas [Tue, 20 Jun 2017 20:54:57 +0000 (20:54 +0000)]
[Statepoint] Add helper functions for GCRelocate and GCResult
These functions isGCRelocate and isGCResult are
similar to isStatepoint(const Value*).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305847
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Saleem Abdulrasool [Tue, 20 Jun 2017 20:51:51 +0000 (20:51 +0000)]
Support: chunk writing on Linux
This is a workaround for large file writes. It has been witnessed that
write(2) failing with EINVAL (22) due to a large value (>2G). Thanks to
James Knight for the help with coming up with a sane test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305846
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Matt Arsenault [Tue, 20 Jun 2017 20:38:06 +0000 (20:38 +0000)]
AMDGPU: Allow vectorization of packed types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305844
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Reid Kleckner [Tue, 20 Jun 2017 20:34:37 +0000 (20:34 +0000)]
[codeview] Fully initialize DataSym when mapping from YAML
In the object file, the section index and relative offset are typically
zero, so make these YAML fields optional with a default.
It looks like there may be more partially initialized symbol records,
but this should fix the msan bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305842
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Stanislav Mekhanoshin [Tue, 20 Jun 2017 20:33:44 +0000 (20:33 +0000)]
[AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32
If there is an immediate operand we shall not shrink V_SUBB_U32
and V_ADDC_U32, it does not fit e32 encoding.
Differential Revison: https://reviews.llvm.org/D34291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305840
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Michael Gottesman [Tue, 20 Jun 2017 20:28:07 +0000 (20:28 +0000)]
[cmake] Add support for using the standalone leaks sanitizer with LLVM.
This commit causes LLVM_USE_SANITIZER to now accept the "Leaks" option. This
will cause cmake to pass in -fsanitize=leak in all of the appropriate places.
I am making this change so that I can setup a linux bot that only detects
leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305839
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Matt Arsenault [Tue, 20 Jun 2017 19:54:14 +0000 (19:54 +0000)]
AMDGPU: Start adding global_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305838
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Aditya Nandakumar [Tue, 20 Jun 2017 19:52:29 +0000 (19:52 +0000)]
[GISel]: NFC. Add comment to G_FMA opcode as requested in rL305824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305837
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Aditya Nandakumar [Tue, 20 Jun 2017 19:25:23 +0000 (19:25 +0000)]
[GISel]: Add G_FMA opcode for fused multiply adds
https://reviews.llvm.org/D34372
Reviewed by dsanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305824
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Matt Arsenault [Tue, 20 Jun 2017 18:56:32 +0000 (18:56 +0000)]
AMDGPU: Do operand folding in program order
Before it was possible to partially fold use instructions
before the defs. After the xor is folded into a copy, the same
mov can end up in the fold list twice, so on the second attempt
it will fail expecting to see a register to fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305821
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Zachary Turner [Tue, 20 Jun 2017 18:50:55 +0000 (18:50 +0000)]
[PDB] Don't write uninitialized bytes to a PDB file.
There were certain fields that we didn't know how to write, as
well as various padding bytes that we would ignore. This leads
to garbage data in the PDB. While not strictly necessary, we
should initialize these bytes to something meaningful, as it
makes for easier binary comparison between PDBs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305819
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Zachary Turner [Tue, 20 Jun 2017 18:50:30 +0000 (18:50 +0000)]
Remove diff pedantic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305818
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Matthias Braun [Tue, 20 Jun 2017 18:43:14 +0000 (18:43 +0000)]
RegisterScavenging: Followup to r305625
This does some improvements/cleanup to the recently introduced
scavengeRegisterBackwards() functionality:
- Rewrite findSurvivorBackwards algorithm to use the existing
LiveRegUnit::accumulateBackward() code. This also avoids the Available
and Candidates bitset and just need 1 LiveRegUnit instance
(= 1 bitset).
- Pick registers in allocation order instead of register number order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305817
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Matt Arsenault [Tue, 20 Jun 2017 18:41:31 +0000 (18:41 +0000)]
AMDGPU: Preserve undef when folding register operands
If the source was a copy of an undef register, this would
produce a read of an undefined register which is a verifier
error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305816
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Stanislav Mekhanoshin [Tue, 20 Jun 2017 18:32:42 +0000 (18:32 +0000)]
[AMDGPU] Eliminate SGPR to VGPR copy when possible
SGPRs are generally cheaper, so try to use them over VGPRs.
Differential Revision: https://reviews.llvm.org/D34130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305815
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Matt Arsenault [Tue, 20 Jun 2017 18:28:02 +0000 (18:28 +0000)]
AMDGPU: Fix crash with undef vreg input operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305814
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Hiroshi Inoue [Tue, 20 Jun 2017 17:53:33 +0000 (17:53 +0000)]
[PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305813
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Simon Pilgrim [Tue, 20 Jun 2017 17:10:27 +0000 (17:10 +0000)]
[CostModel][X86] Add scalar arithmetic cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305810
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Simon Pilgrim [Tue, 20 Jun 2017 17:04:46 +0000 (17:04 +0000)]
[CostModel][X86] Declare costs variables based on type
The alphabetical progression isn't that useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305808
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Craig Topper [Tue, 20 Jun 2017 16:34:37 +0000 (16:34 +0000)]
[TableGen] Take a parameter by reference instead of pointer so we don't have to add & on both callers. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305807
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Craig Topper [Tue, 20 Jun 2017 16:34:35 +0000 (16:34 +0000)]
[TableGen] Use range based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305806
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Yuka Takahashi [Tue, 20 Jun 2017 16:31:31 +0000 (16:31 +0000)]
[GSoC] Flag value completion for clang
This is patch for GSoC project, bash-completion for clang.
To use this on bash, please run `source clang/utils/bash-autocomplete.sh`.
bash-autocomplete.sh is code for bash-completion.
In this patch, Options.td was mainly changed in order to add value class
in Options.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305805
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Sanjay Patel [Tue, 20 Jun 2017 15:58:30 +0000 (15:58 +0000)]
[x86] enable CGP memcmp() expansion for 2/4/8 byte sizes
There are a couple of potential improvements as seen in the IR and asm:
1. We're unnecessarily extending to a larger type to compare values.
2. The codegen for (select cond, 1, -1) could avoid a cmov.
(or we could change the order of the compares, so we have a select with 0 operand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305802
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Simon Pilgrim [Tue, 20 Jun 2017 15:19:02 +0000 (15:19 +0000)]
[X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=16bit elements
Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305801
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Tim Northover [Tue, 20 Jun 2017 15:01:38 +0000 (15:01 +0000)]
DAG: correctly legalize UMULO.
We were incorrectly sign extending into the high word (as you would for
SMULO) when legalizing UMULO in terms of a wider full multiplication.
Patch by James Duley.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305800
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Vassil Vassilev [Tue, 20 Jun 2017 14:20:48 +0000 (14:20 +0000)]
D33466: Make file non-executable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305795
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Sanjay Patel [Tue, 20 Jun 2017 12:45:46 +0000 (12:45 +0000)]
[InstCombine] fix code/test comments for r305792; NFC
These diffs were in the last version of the patch in D33342,
but I accidentally committed the previous rev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305793
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Sanjay Patel [Tue, 20 Jun 2017 12:40:55 +0000 (12:40 +0000)]
[InstCombine] try to canonicalize xor-of-icmps to and-of-icmps
We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine,
but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds,
we can use the truth table definition of xor:
X ^ Y --> (X | Y) & !(X & Y)
...to see if we can convert the xor to and/or and then use the existing folds.
http://rise4fun.com/Alive/J9v
Differential Revision: https://reviews.llvm.org/D33342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305792
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Daniel Sanders [Tue, 20 Jun 2017 12:36:34 +0000 (12:36 +0000)]
[globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
with them. This isn't particularly important yet but it's a small step
towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
an alternate constraint mechanism ConstrainOperandToRegClassAction() which
supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.
Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar
Reviewed By: ab
Subscribers: javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D33590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305791
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Simon Pilgrim [Tue, 20 Jun 2017 12:28:33 +0000 (12:28 +0000)]
Fix Wdocumentation warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305790
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Simon Pilgrim [Tue, 20 Jun 2017 10:33:34 +0000 (10:33 +0000)]
[X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODO
Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305788
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Simon Pilgrim [Tue, 20 Jun 2017 10:24:06 +0000 (10:24 +0000)]
Fixed test name. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305787
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Igor Breger [Tue, 20 Jun 2017 09:40:57 +0000 (09:40 +0000)]
[GlobalISel][X86] fix compilation error ( -Werror=unused-function )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305786
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Haojian Wu [Tue, 20 Jun 2017 09:29:43 +0000 (09:29 +0000)]
[SelectionDAG] Fix an use-after-free issue introduced in r305775.
vector.back() will be invalidated when memory reallocation happens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305785
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Igor Breger [Tue, 20 Jun 2017 09:15:10 +0000 (09:15 +0000)]
[GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665
Reviewers: qcolombet, t.p.northover, zvi, guyblank
Reviewed By: t.p.northover, guyblank
Subscribers: guyblank, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D33952
Conflicts:
test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305784
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Igor Breger [Tue, 20 Jun 2017 08:54:17 +0000 (08:54 +0000)]
[GlobalISel] combine not symmetric merge/unmerge nodes.
Summary:
In some cases legalization ends up with not symmetric merge/unmerge nodes.
Transform it to merge/unmerge nodes.
Reviewers: t.p.northover, qcolombet, zvi
Reviewed By: t.p.northover
Subscribers: rovka, kristof.beyls, guyblank, llvm-commits
Differential Revision: https://reviews.llvm.org/D33626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305783
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Max Kazantsev [Tue, 20 Jun 2017 08:37:31 +0000 (08:37 +0000)]
[SCEV][NFC] Fix a misleading description of AddOpsInlineThreshold
The description of this option was copy-pasted from another one and does not
correspond to reality.
Differential Revision: https://reviews.llvm.org/D34390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305782
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Igor Breger [Tue, 20 Jun 2017 08:30:48 +0000 (08:30 +0000)]
[GlobalISel][X86] add legalizer mir tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305781
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