OSDN Git Service
Aditya Nandakumar [Mon, 23 Oct 2017 22:53:04 +0000 (22:53 +0000)]
[GISel][AArch64]: Fix illegal Generic copies in tests
This is in preparation for a verifier check that makes sure copies are
of the same size (when generic virtual registers are involved).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316387
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Reid Kleckner [Mon, 23 Oct 2017 22:44:24 +0000 (22:44 +0000)]
[codeview] Recognize two records with no type index fields
Thunk records do not have types and frame cookies do not have types.
These were found while linking libconcrt.lib from MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316385
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Rong Xu [Mon, 23 Oct 2017 22:21:29 +0000 (22:21 +0000)]
[PM] Add pgo-memop-opt pass to the new pass manager
This pass adds pgo-memop-opt pass to the new pass manager.
It is in the old pass manager but somehow left out in the new pass manager.
Differential Revision: http://reviews.llvm.org/D39145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316384
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Simon Pilgrim [Mon, 23 Oct 2017 22:05:02 +0000 (22:05 +0000)]
[X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8
Avoid difficulties determining the number of sign bits later on in shuffle lowering to lower to PACKSS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316383
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Bob Wilson [Mon, 23 Oct 2017 21:51:50 +0000 (21:51 +0000)]
Add a new Simulator entry for the target triple environment.
Apple's iOS, tvOS and watchOS simulator platforms have never been clearly
distinguished in the target triples. Even though they are intended to
behave similarly to the corresponding device platforms, they have separate
SDKs and are really separate platforms from the compiler's perspective.
Clang now defines a macro when building for one of these simulator platforms
(r297866) but that relies on the very indirect mechanism of checking to see
which option was used to specify the minimum deployment target. That is not
so great. Swift would also like to distinguish these simulator platforms in
a similar way, but unlike Clang, Swift does not use a separate option to
specify the minimum deployment target -- it uses a -target option to
specify the target triple directly, including the OS version number.
Using a different target triple for the simulator platforms is a much
more direct and obvious way to specify this. Putting the "simulator" in
the environment component of the triple means the OS values can stay the
same and existing code the looks at the OS field will not be affected.
https://reviews.llvm.org/D39143
rdar://problem/
34729432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316380
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George Burgess IV [Mon, 23 Oct 2017 21:08:02 +0000 (21:08 +0000)]
Fix buildbot breakage
SP is only used in an assert. Caused by r316374.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316377
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Mitch Phillips [Mon, 23 Oct 2017 20:54:01 +0000 (20:54 +0000)]
Made llvm-cfi-verify not execute unit tests on non-x86 builds.
Patched out from D38427.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, kcc, pcc, mgorny
Differential Revision: https://reviews.llvm.org/D39197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316375
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George Burgess IV [Mon, 23 Oct 2017 20:46:36 +0000 (20:46 +0000)]
Don't crash when we see unallocatable registers in clobbers
This fixes a bug where we'd crash given code like the test-case from
https://bugs.llvm.org/show_bug.cgi?id=30792 . Instead, we let the
offending clobber silently slide through.
This doesn't fully fix said bug, since the assembler will still complain
the moment it sees a crypto/fp/vector op, and we still don't diagnose
calls that require vector regs.
Differential Revision: https://reviews.llvm.org/D39030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316374
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Mitch Phillips [Mon, 23 Oct 2017 20:25:19 +0000 (20:25 +0000)]
Graph builder implementation.
Implement a localised graph builder for indirect control flow
instructions. Main interface is through GraphBuilder::buildFlowGraph,
which will build a flow graph around an indirect CF instruction. Various
modifications to FileVerifier are also made to const-expose some members
needed for machine code analysis done by the graph builder.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, kcc, pcc
Differential Revision: https://reviews.llvm.org/D38427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316372
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Stefan Pintilie [Mon, 23 Oct 2017 20:22:23 +0000 (20:22 +0000)]
Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"
Revert commit r316366.
Previous commit causes p8-scalar_vector_conversions.ll to fail.
This reverts commit
990e764ad8a2eec206ce5dda6aefab059ccd4e92.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316371
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Mandeep Singh Grang [Mon, 23 Oct 2017 19:56:52 +0000 (19:56 +0000)]
[GVNSink] Fix failing GVNSink tests in the reverse iteration bot
Summary:
The elts of ActivePreds which is defined as a SmallPtrSet are copied
into Blocks using std::copy. This makes the resultant order of Blocks
non-deterministic. We cannot simply sort Blocks as they need to match
the corresponding Values. So a better approach is to define ActivePreds
as SmallSetVector.
This fixes the following failures in
http://lab.llvm.org:8011/builders/reverse-iteration:
LLVM :: Transforms/GVNSink/indirect-call.ll
LLVM :: Transforms/GVNSink/sink-common-code.ll
LLVM :: Transforms/GVNSink/struct.ll
Reviewers: dberlin, jmolloy, bkramer, efriedma
Reviewed By: dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316369
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Krzysztof Parzyszek [Mon, 23 Oct 2017 19:35:25 +0000 (19:35 +0000)]
[Hexagon] Return the correct chain edge for i1 function calls
In HexagonISelLowering, there is code to handle the case when
a function returns an i1 type. In this case, we need to generate
extra nodes to copy the result from R0 to a predicate register.
The code was returning the wrong value for the chain edge which
caused an assert "Wrong topological sorting" when converting the
instructions to MIs.
This patch fixes the problem by returning the chain for the final
copy.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316367
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Stefan Pintilie [Mon, 23 Oct 2017 19:33:31 +0000 (19:33 +0000)]
[PowerPC] Try to simplify a Swap if it feeds a Splat
If we have the situation where a Swap feeds a Splat we can sometimes change the
index on the Splat and then remove the Swap instruction.
Differential Revision: https://reviews.llvm.org/D39009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316366
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Krzysztof Parzyszek [Mon, 23 Oct 2017 19:07:50 +0000 (19:07 +0000)]
[Hexagon] Add extra pattern for S4_addaddi
One combination was missing: add(add(x,y),c).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316363
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Jonas Hahnfeld [Mon, 23 Oct 2017 18:41:22 +0000 (18:41 +0000)]
Fix FormatVariadicTest with GCC
Looks like GCC didn't like the original specialization, try within namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316361
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Daniel Sanders [Mon, 23 Oct 2017 18:19:24 +0000 (18:19 +0000)]
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.
This patch enables the import of stores. Unfortunately, doing so by itself,
loses an optimization where storing 0 to memory makes use of WZR/XZR.
To mitigate this, this patch also introduces a new feature that allows register
operands to nominate a zero register. When this is done, GlobalISel will
substitute (G_CONSTANT 0) with the nominated register automatically. This
is currently configured to only apply to the stores.
Applying it to GPR32/GPR64 register classes in general will be done after
review see (https://reviews.llvm.org/D39150).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316360
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Mitch Phillips [Mon, 23 Oct 2017 18:17:56 +0000 (18:17 +0000)]
Accidently merged an incomplete upstream patch in
10e6ee563a6b5ca498f27972ca6dbe6c308f1ac2 - reverting the changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316359
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Mitch Phillips [Mon, 23 Oct 2017 18:11:31 +0000 (18:11 +0000)]
Patch in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316358
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Vedant Kumar [Mon, 23 Oct 2017 18:04:34 +0000 (18:04 +0000)]
[wasm] readSection: Avoid reading past eof (fixes oss-fuzz #3219)
A wasm file crafted with a bogus section size can trigger an ASan issue
in the DWARFObjInMemory constructor. Nip the problem in the bud when we
read the wasm section.
Found by OSS-Fuzz:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3219
Differential Revision: https://reviews.llvm.org/D38777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316357
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Simon Pilgrim [Mon, 23 Oct 2017 17:50:40 +0000 (17:50 +0000)]
[X86][SSE] Regenerate PACKSS tests on 32 + 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316354
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Mitch Phillips [Mon, 23 Oct 2017 17:37:41 +0000 (17:37 +0000)]
Updated 'Getting Started' to use valid git links (added trailing slashes)
Reviewers: pcc, asl, tonic
Reviewed By: pcc
Subscribers: llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D38516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316352
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Sanjay Patel [Mon, 23 Oct 2017 17:30:17 +0000 (17:30 +0000)]
[PassManager] add test to show the new PM uses -latesimplifycfg early; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316351
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Daniel Sanders [Mon, 23 Oct 2017 17:18:44 +0000 (17:18 +0000)]
[globalisel] Add very brief docs summarizing the ISel part of the LLVMDev tutorial.
Also added links to the talks available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316350
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Matt Arsenault [Mon, 23 Oct 2017 17:16:43 +0000 (17:16 +0000)]
AMDGPU: Cleanup local atomic node names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316349
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Matt Arsenault [Mon, 23 Oct 2017 17:09:35 +0000 (17:09 +0000)]
AMDGPU: Fix default range in non-kernel functions
The range should be assumed to be the hardware maximum
if a workitem intrinsic is used in a callable function
which does not know the restricted limit of the calling
kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316346
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Craig Topper [Mon, 23 Oct 2017 16:49:26 +0000 (16:49 +0000)]
[X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316345
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Jessica Paquette [Mon, 23 Oct 2017 16:25:53 +0000 (16:25 +0000)]
[MachineOutliner] NFC: Rename getters/setters to fit coding style
Rename endIdx, startIdx, and length to getEndIdx, getStartIdx, and getLength
in Candidate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316341
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Craig Topper [Mon, 23 Oct 2017 16:22:40 +0000 (16:22 +0000)]
[X86] Change VMPTRST to use PS instead of TB to match VMPTRLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316340
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Craig Topper [Mon, 23 Oct 2017 16:22:38 +0000 (16:22 +0000)]
[X86] Change RDRAND to use PS instead of TB.
Should be no functional change for now. A future disassembler change will prevent disassembling with 0xf2/0xf3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316339
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Craig Topper [Mon, 23 Oct 2017 16:11:33 +0000 (16:11 +0000)]
[X86] Change XRSTOR to use PS instead of TB to match XSAVE.
I don't think this changes anything functionally yet, but I plan to fix the disassembler to use this to disable matching certain instructions with 0xf3/0xf2/0x66 prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316337
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Simon Pilgrim [Mon, 23 Oct 2017 16:00:57 +0000 (16:00 +0000)]
[X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.
Remove AssertZext and instead add PEXTRW/PEXTRB support to computeKnownBitsForTargetNode to simplify instruction selection.
Differential Revision: https://reviews.llvm.org/D39169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316336
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Andrew V. Tischenko [Mon, 23 Oct 2017 15:53:30 +0000 (15:53 +0000)]
Update DPPD/DPPS instruction scheduling on btver2.
Differential Revision: https://reviews.llvm.org/D39046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316334
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Craig Topper [Mon, 23 Oct 2017 15:53:21 +0000 (15:53 +0000)]
[X86] Add PTWRITE instruction for assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316333
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Craig Topper [Mon, 23 Oct 2017 15:53:16 +0000 (15:53 +0000)]
[X86] Add RDPID instruction for assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316332
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Simon Pilgrim [Mon, 23 Oct 2017 15:48:08 +0000 (15:48 +0000)]
[DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORs
combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together.
This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask.
Differential Revision: https://reviews.llvm.org/D38696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316331
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Sam McCall [Mon, 23 Oct 2017 15:40:44 +0000 (15:40 +0000)]
Support formatting formatv_objects.
Summary:
Support formatting formatv_objects.
While here, fix documentation about member-formatters, and attempted
perfect-forwarding (I think).
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316330
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Simon Pilgrim [Mon, 23 Oct 2017 14:47:49 +0000 (14:47 +0000)]
[X86][SSE] Regenerate bitcast-and-setcc tests
Avoid the retl/retq changes in an upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316328
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Simon Pilgrim [Mon, 23 Oct 2017 14:19:46 +0000 (14:19 +0000)]
[X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316326
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Simon Pilgrim [Mon, 23 Oct 2017 14:17:59 +0000 (14:17 +0000)]
[X86][AVX] Regenerate AVX intrinsics tests on 32 + 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316325
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Simon Pilgrim [Mon, 23 Oct 2017 14:15:24 +0000 (14:15 +0000)]
[X86][F16C] Regenerate F16C schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316324
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Artur Gainullin [Mon, 23 Oct 2017 13:25:49 +0000 (13:25 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316322
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George Rimar [Mon, 23 Oct 2017 11:24:14 +0000 (11:24 +0000)]
[llvm-dwarfdump] - Teach tool about few GNU call_sites constants.
This teaches tool about following consants:
DW_TAG_GNU_call_site,
DW_TAG_GNU_call_site_parameter,
DW_AT_GNU_call_site_value,
DW_AT_GNU_all_call_sites.
Constants documented here: https://sourceware.org/elfutils/DwarfExtensions
Differential revision: https://reviews.llvm.org/D39119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316321
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Ayman Musa [Mon, 23 Oct 2017 10:24:19 +0000 (10:24 +0000)]
[X86] Add test for opportunity to use bzhi X86 instruction instead of load+and instructions.
Transformation uploaded for CR in https://reviews.llvm.org/D34141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316320
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Andrew V. Tischenko [Mon, 23 Oct 2017 09:36:33 +0000 (09:36 +0000)]
Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue was in illegal segment register index.
Differential Revision: https://reviews.llvm.org/D38786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316319
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Martin Storsjo [Mon, 23 Oct 2017 09:08:13 +0000 (09:08 +0000)]
[COFF] Improve the check for functions that should get an extra underscore
This fixes exporting functions starting with an underscore, and
fully decorated fastcall/vectorcall functions.
Tests will be added in the lld repo.
Differential Revision: https://reviews.llvm.org/D39168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316316
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Haojian Wu [Mon, 23 Oct 2017 09:02:59 +0000 (09:02 +0000)]
Fix a -Wpedantic warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316315
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Sam Parker [Mon, 23 Oct 2017 08:05:14 +0000 (08:05 +0000)]
[ARM] Allow unrolling of multi-block loops.
Before, loop unrolling was only enabled for loops with a single
block. This restriction has been removed and replaced by:
- allow a maximum of two exiting blocks,
- a four basic block limit for cores with a branch predictor.
Differential Revision: https://reviews.llvm.org/D38952
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316313
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Craig Topper [Mon, 23 Oct 2017 03:42:35 +0000 (03:42 +0000)]
[X86] Update a doxygen comment in the disassembler tablegen code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316309
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Craig Topper [Mon, 23 Oct 2017 02:26:24 +0000 (02:26 +0000)]
[X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316308
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Saleem Abdulrasool [Sun, 22 Oct 2017 20:51:25 +0000 (20:51 +0000)]
ExecutionEngine: make COFF Thumb2 assertions non-tautological
The overflow detection assertions were tautological due to truncation.
Adjust them to no longer be tautological.
Patch by Alex Langford!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316303
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Yichao Yu [Sun, 22 Oct 2017 20:28:17 +0000 (20:28 +0000)]
Fix invalid ptrtoint in InstCombine
Summary:
It's unclear if this is the only thing we can do but at least this is consistent with the check
of address space agreement in `isBitCastable`.
The code is used at least in both instcombine and jumpthreading though
I could only find a way to trigger the invalid cast in instcombine.
Reviewers: loladiro, sanjoy, majnemer
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316302
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Benjamin Kramer [Sun, 22 Oct 2017 20:16:28 +0000 (20:16 +0000)]
Create fewer copies of StringMaps. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316301
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Benjamin Kramer [Sun, 22 Oct 2017 19:16:31 +0000 (19:16 +0000)]
[X86] Add missing override. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316299
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Sanjay Patel [Sun, 22 Oct 2017 19:10:07 +0000 (19:10 +0000)]
[SimplifyCFG] delay switch condition forwarding to -latesimplifycfg
As discussed in D39011:
https://reviews.llvm.org/D39011
...replacing constants with a variable is inverting the transform done
by other IR passes, so we definitely don't want to do this early.
In fact, it's questionable whether this transform belongs in SimplifyCFG
at all. I'll look at moving this to codegen as a follow-up step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316298
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Fangrui Song [Sun, 22 Oct 2017 18:43:23 +0000 (18:43 +0000)]
[utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D39164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316297
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Simon Pilgrim [Sun, 22 Oct 2017 18:38:57 +0000 (18:38 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316296
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Marina Yatsina [Sun, 22 Oct 2017 17:59:38 +0000 (17:59 +0000)]
Add logic to greedy reg alloc to avoid bad eviction chains
This fixes bugzilla 26810
https://bugs.llvm.org/show_bug.cgi?id=26810
This is intended to prevent sequences like:
movl %ebp, 8(%esp) # 4-byte Spill
movl %ecx, %ebp
movl %ebx, %ecx
movl %edi, %ebx
movl %edx, %edi
cltd
idivl %esi
movl %edi, %edx
movl %ebx, %edi
movl %ecx, %ebx
movl %ebp, %ecx
movl 16(%esp), %ebp # 4 - byte Reload
Such sequences are created in 2 scenarios:
Scenario #1:
vreg0 is evicted from physreg0 by vreg1
Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from)
Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.)
one of the split intervals ends up evicting vreg2 from physreg1
Evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
Scenario #2
vreg0 is evicted from physreg0 by vreg1
vreg2 is evicted from physreg2 by vreg3 etc
Evictee vreg0 is intended for region splitting with split candidate physreg1
Region splitting creates a local interval because of interference with the evictor vreg1
one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from)
Another evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest).
Differential Revision: https://reviews.llvm.org/D35816
Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316295
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Craig Topper [Sun, 22 Oct 2017 17:22:29 +0000 (17:22 +0000)]
[X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.
More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316294
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Sanjay Patel [Sun, 22 Oct 2017 16:51:03 +0000 (16:51 +0000)]
[SimplifyCFG] try harder to forward switch condition to phi (PR34471)
The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen:
int switcher(int x) {
switch(x) {
case 17: return 17;
case 19: return 19;
case 42: return 42;
default: break;
}
return 0;
}
int comparator(int x) {
if (x == 17) return 17;
if (x == 19) return 19;
if (x == 42) return 42;
return 0;
}
For the first example, we use a bit-test optimization to avoid a series of compare-and-branch:
https://godbolt.org/g/BivDsw
Differential Revision: https://reviews.llvm.org/D39011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316293
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Momchil Velikov [Sun, 22 Oct 2017 11:56:35 +0000 (11:56 +0000)]
[ARM] Dynamic stack alignment for 16-bit Thumb
This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When
targeting processors, which support only the 16-bit Thumb instruction set
the compiler ignores the alignment attributes of automatic variables and may
silently generate incorrect code.
Differential revision: https://reviews.llvm.org/D38143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316289
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Guy Blank [Sun, 22 Oct 2017 11:43:08 +0000 (11:43 +0000)]
[X86] Add a pass to convert instruction chains between domains.
The pass scans the function to find instruction chains that define
registers in the same domain (closures).
It then calculates the cost of converting the closure to another domain.
If found profitable, the instructions are converted to instructions in
the other domain and the register classes are changed accordingly.
This commit adds the pass infrastructure and a simple conversion from
the GPR domain to the Mask domain.
Differential Revision:
https://reviews.llvm.org/D37251
Change-Id: Ic2cf1d76598110401168326d411128ae2580a604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316288
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Nitesh Jain [Sun, 22 Oct 2017 09:47:41 +0000 (09:47 +0000)]
[mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.
Reviewers: sdardis
Subscribers: jaydeep, bhushan, llvm-commits
Differential Revision: https://reviews.llvm.org/D38314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316287
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Craig Topper [Sun, 22 Oct 2017 06:18:26 +0000 (06:18 +0000)]
[X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316285
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Craig Topper [Sun, 22 Oct 2017 06:18:23 +0000 (06:18 +0000)]
[X86] Add VEX_WIG to applicable AVX512 instructions.
This should be NFC. Will be used in future patches to fix disassembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316284
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Craig Topper [Sun, 22 Oct 2017 06:18:20 +0000 (06:18 +0000)]
[X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316283
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Craig Topper [Sun, 22 Oct 2017 04:32:30 +0000 (04:32 +0000)]
[X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte.
Fixes PR34998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316282
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Simon Pilgrim [Sat, 21 Oct 2017 20:40:49 +0000 (20:40 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316277
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Aaron Ballman [Sat, 21 Oct 2017 20:38:15 +0000 (20:38 +0000)]
Reverting r316270 due to failing build bots.
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316276
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Simon Pilgrim [Sat, 21 Oct 2017 20:19:48 +0000 (20:19 +0000)]
[X86][SSE] Add extractps/pextrd equivalence to domain tables
Differential Revision: https://reviews.llvm.org/D39135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316274
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Craig Topper [Sat, 21 Oct 2017 20:03:20 +0000 (20:03 +0000)]
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.
This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB.
This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type.
This fixes PR32807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316273
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Simon Pilgrim [Sat, 21 Oct 2017 17:23:04 +0000 (17:23 +0000)]
Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316271
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Fangrui Song [Sat, 21 Oct 2017 16:59:40 +0000 (16:59 +0000)]
[PPC CodeGen] Fix the bitreverse.i64 intrinsic.
Summary: The two 32-bit words were swapped.
Subscribers: nemanjai, kbarton
Differential Revision: https://reviews.llvm.org/D38705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316270
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Craig Topper [Sat, 21 Oct 2017 16:35:41 +0000 (16:35 +0000)]
[ValueTracking] Remove unnecessary temporary APInt from computeNumSignBitsVectorConstant.
We can just use getNumSignBits instead of inverting negative numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316266
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Craig Topper [Sat, 21 Oct 2017 16:35:39 +0000 (16:35 +0000)]
[ValueTracking] Simplify the known bits code for constant vectors a little.
Neither of these cases really require a temporary APInt outside the loop. For the ConstantDataSequential case the APInt will never be larger than 64-bits so its fine to just call getElementAsAPInt. For ConstantVector we can get the APInt by reference and only make a copy where the inversion is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316265
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Simon Pilgrim [Sat, 21 Oct 2017 14:35:09 +0000 (14:35 +0000)]
[X86][SSE] Add missing extractps scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316262
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David Green [Sat, 21 Oct 2017 13:58:37 +0000 (13:58 +0000)]
[LoopInterchange] Fix phi node ordering miscompile.
The way that splitInnerLoopHeader splits blocks requires that
the induction PHI will be the first PHI in the inner loop
header. This makes sure that is actually the case when there
are both IV and reduction phis.
Differential Revision: https://reviews.llvm.org/D38682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316261
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Florian Hahn [Sat, 21 Oct 2017 05:37:10 +0000 (05:37 +0000)]
[SelectionDAG] Use dyn_cast without cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316258
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Florian Hahn [Sat, 21 Oct 2017 04:57:03 +0000 (04:57 +0000)]
[SelectionDAG] Use isa to silence unused variable warning (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316257
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Craig Topper [Sat, 21 Oct 2017 03:22:13 +0000 (03:22 +0000)]
[SelectionDAG] Don't subject ConstantSDNodes to the depth limit in computeKnownBits and ComputeNumSignBits.
We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316256
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Craig Topper [Sat, 21 Oct 2017 02:27:19 +0000 (02:27 +0000)]
[SelectionDAG] Don't subject ISD:Constant to the depth limit in TargetLowering::SimplifyDemandedBits.
Summary:
We shouldn't recurse any further but it doesn't mean we shouldn't be able to give the known bits for a constant. The caller would probably like that we always return the right answer for a constant RHS. This matches what InstCombine does in this case.
I don't have a test case because this showed up while trying to revive D31724.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D38967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316255
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Craig Topper [Sat, 21 Oct 2017 02:26:00 +0000 (02:26 +0000)]
[X86] Do not generate __multi3 for mul i128 on X86
Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test.
Patch by Riyaz V Puthiyapurayil
Reviewers: craig.topper, schweitz
Reviewed By: craig.topper, schweitz
Subscribers: RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D38668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316254
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Eugene Zelenko [Sat, 21 Oct 2017 00:57:46 +0000 (00:57 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316253
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Krzysztof Parzyszek [Fri, 20 Oct 2017 22:08:40 +0000 (22:08 +0000)]
[Packetizer] Add function to check for aliasing between instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316243
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Sanjay Patel [Fri, 20 Oct 2017 21:55:23 +0000 (21:55 +0000)]
[utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316242
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Eugene Zelenko [Fri, 20 Oct 2017 21:47:29 +0000 (21:47 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316241
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Sam Clegg [Fri, 20 Oct 2017 21:28:38 +0000 (21:28 +0000)]
[WebAssembly] MC: Fix crash when -g specified.
At this point we don't output any debug sections or thier
relocations.
Differential Revision: https://reviews.llvm.org/D39076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316240
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Daniel Sanders [Fri, 20 Oct 2017 20:55:29 +0000 (20:55 +0000)]
[globalisel][tablegen] Fix small spelling nits. NFC
ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237
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Krzysztof Parzyszek [Fri, 20 Oct 2017 20:24:44 +0000 (20:24 +0000)]
[Hexagon] Report error instead of crashing on wrong inline-asm constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316236
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Peter Collingbourne [Fri, 20 Oct 2017 19:48:26 +0000 (19:48 +0000)]
COFF: Add type server pdb files to linkrepro tar file.
Differential Revision: https://reviews.llvm.org/D38977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316233
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Krzysztof Parzyszek [Fri, 20 Oct 2017 19:33:12 +0000 (19:33 +0000)]
[Hexagon] Reorganize and update instruction patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316228
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Simon Pilgrim [Fri, 20 Oct 2017 19:29:01 +0000 (19:29 +0000)]
[X86][SSE] Add missing _mm_extract_ps fast-isel test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316226
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Sanjay Patel [Fri, 20 Oct 2017 18:35:32 +0000 (18:35 +0000)]
[x86] avoid FileCheck assert duplication with retl/retq regex; NFC
This was suggested in PR35003:
https://bugs.llvm.org/show_bug.cgi?id=35003
32-bit checks may be identical to 64-bit (if we avoid those pesky scalar params!).
I'll check in the script change shortly assuming this doesn't anger any bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316223
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Simon Pilgrim [Fri, 20 Oct 2017 18:07:50 +0000 (18:07 +0000)]
[X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.
To help identify shuffle combine issues
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316222
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Sam Clegg [Fri, 20 Oct 2017 17:41:12 +0000 (17:41 +0000)]
[WebAssembly] MC: Handle (ignore) MCSA_Protected symbol attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316220
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Dave Lee [Fri, 20 Oct 2017 17:04:43 +0000 (17:04 +0000)]
Make x86 __ehhandler comdat if parent function is
Summary:
This change comes from using lld for i686-windows-msvc. Before this change, lld
emits an error of:
error: relocation against symbol in discarded section: .xdata
It's possible that this could be addressed in lld, but I think this change is
reasonable on its own.
At a high level, this is being generated:
A (.text comdat) -> B (.text) -> C (.xdata comdat)
Where A is a C++ inline function, which references B, an exception handler
thunk, which references C, the exception handling info.
With this structure, lld will error when applying relocations to B if the C it
references has been discarded (some other C has been selected).
This change checks if A is comdat, and if so places the exception registration
thunk (B) in the comdata group of A (and B).
It appears that MSVC makes the __ehhandler function comdat.
Is it possible that duplicate thunks are being emitted into the final binary
with other linkers, or are they stripping the unused thunks?
Reviewers: rnk, majnemer, compnerd, smeenai
Reviewed By: rnk, compnerd
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316219
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Krzysztof Parzyszek [Fri, 20 Oct 2017 16:56:33 +0000 (16:56 +0000)]
[Hexagon] Allow redefinition with immediates for hw loop conversion
Normally, if the registers holding the induction variable's bounds
are redefined inside of the loop's body, the loop cannot be converted
to a hardware loop. However, if the redefining instruction is actually
loading an immediate value into the register, this conversion is both
possible and legal (since the immediate itself will be used in the
loop setup in the preheader).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316218
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Simon Pilgrim [Fri, 20 Oct 2017 16:55:51 +0000 (16:55 +0000)]
[X86] Check all CPU target names.
We ignore the 32-bit/64-bit triple but I've tried to use i686 triples for CPUs that don't support x86_64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316217
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Zvi Rackover [Fri, 20 Oct 2017 15:32:14 +0000 (15:32 +0000)]
X86 Tests: Add tests for vector permutes with variable indices. NFC.
Basic tests which are the equivalent of single-source shufflevector with variable mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316216
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Aleksandar Beserminji [Fri, 20 Oct 2017 14:35:41 +0000 (14:35 +0000)]
Revert "[mips] Reordering callseq* nodes to be linear"
This reverts commit r314507, because the original patch is causing test
failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316215
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Eugene Leviant [Fri, 20 Oct 2017 14:29:17 +0000 (14:29 +0000)]
[ARM] Use post-RA MI scheduler when +use-misched is set
Differential revision: https://reviews.llvm.org/D39100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316214
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