OSDN Git Service

android-x86/external-llvm.git
6 years ago[docs] Scudo documentation minor update
Kostya Kortchinsky [Fri, 18 May 2018 17:02:35 +0000 (17:02 +0000)]
[docs] Scudo documentation minor update

Summary:
Minor changes to reflect changes to the code that were not documented:
- `SCUDO_DEFAULT_OPTIONS` compile time way of defining options;
- MIPS added as a supported architecture;
- clarification on how to fully disable the Quarantine;
- rewording in a few places.

Reviewers: alekseyshl, flowerhack

Reviewed By: alekseyshl

Subscribers: sdardis, arichardson, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D47071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332736 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] update coding standard links to HTTPS
JF Bastien [Fri, 18 May 2018 16:44:13 +0000 (16:44 +0000)]
[NFC] update coding standard links to HTTPS

Update one link which redirected, and remove an Amazon ref.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332735 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMCSchedModel: Add comments to IssueWidth.
Andrew Trick [Fri, 18 May 2018 15:57:54 +0000 (15:57 +0000)]
MCSchedModel: Add comments to IssueWidth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332729 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] add tests for lack of abs/nabs canonicalization; NFC
Sanjay Patel [Fri, 18 May 2018 15:26:38 +0000 (15:26 +0000)]
[InstCombine] add tests for lack of abs/nabs canonicalization; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332726 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] regenerate checks; NFC
Sanjay Patel [Fri, 18 May 2018 15:22:19 +0000 (15:22 +0000)]
[InstCombine] regenerate checks; NFC

There were a combination of auto-generated styles in use
here because the scripts have evolved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332725 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency
Simon Pilgrim [Fri, 18 May 2018 14:22:22 +0000 (14:22 +0000)]
[X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332722 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore sched...
Simon Pilgrim [Fri, 18 May 2018 14:08:01 +0000 (14:08 +0000)]
[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes

Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.

Fixes BtVer2/SLM which have different behaviours for GPR stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332718 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX] VEXTRACTF128mr store is a WriteFStoreX not WriteFStore
Simon Pilgrim [Fri, 18 May 2018 13:17:51 +0000 (13:17 +0000)]
[X86][AVX] VEXTRACTF128mr store is a WriteFStoreX not WriteFStore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332715 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SSE] Ensure float load/stores use the WriteFLoad/WriteFStore scheduler classes
Simon Pilgrim [Fri, 18 May 2018 13:13:59 +0000 (13:13 +0000)]
[X86][SSE] Ensure float load/stores use the WriteFLoad/WriteFStore scheduler classes

Retag some instructions that were missed when we split off vector load/store/moves - MOVSS/MOVSD/MOVHPD/MOVHPD/MOVLPD/MOVLPS etc.

Fixes BtVer2/SLM which have different behaviours for GPR stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332714 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ExynosM3] Fix scheduling info.
Clement Courbet [Fri, 18 May 2018 13:10:41 +0000 (13:10 +0000)]
[ExynosM3] Fix scheduling info.

Differential Revision: https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332713 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][ZnVer1] Cleanup more single match instregexs
Simon Pilgrim [Fri, 18 May 2018 13:05:26 +0000 (13:05 +0000)]
[X86][ZnVer1] Cleanup more single match instregexs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332712 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd Script to match open Phabricator reviews with potential reviewers.
Kristof Beyls [Fri, 18 May 2018 13:02:32 +0000 (13:02 +0000)]
Add Script to match open Phabricator reviews with potential reviewers.

At the last EuroLLVM, I gave a lightning talk about code review
statistics on Phabricator reviews and what we could derive from that
to try and reduce waiting-for-review bottlenecks. (see
https://llvm.org/devmtg/2018-04/talks.html#Lightning_2).

One of the items I pointed to is a script we've been using internally
for a little while to try and match open Phabricator reviews to people
who might be able to review them well. I received quite a few requests
to share that script, so here it is.

Warning: this is prototype quality!

The script uses 2 similar heuristics to try and match open reviews with
potential reviewers:

If there is overlap between the lines of code touched by the
patch-under-review and lines of code that a person has written, that
person may be a good reviewer.
If there is overlap between the files touched by the patch-under-review
and the source files that a person has made changes to, that person may
be a good reviewer.
The script provides a percentage for each of the above heuristics and
emails a summary. For example, a summary I received a few weeks ago
from the script is the following:

SUMMARY FOR kristof.beyls@arm.com (found 8 reviews):
[3.37%/41.67%] https://reviews.llvm.org/D46018 '[GlobalISel][IRTranslator] Split aggregates during IR translation' by Amara Emerson
[0.00%/100.00%] https://reviews.llvm.org/D46111 '[ARM] Enable misched for R52.' by Dave Green
[0.00%/50.00%] https://reviews.llvm.org/D45770 '[AArch64] Disable spill slot scavenging when stack realignment required.' by Paul Walker
[0.00%/40.00%] https://reviews.llvm.org/D42759 '[CGP] Split large data structres to sink more GEPs' by Haicheng Wu
[0.00%/25.00%] https://reviews.llvm.org/D45189 '[MachineOutliner][AArch64] Keep track of functions that use a red zone in AArch64MachineFunctionInfo and use that instead of checking for noredzone in the MachineOutliner' by Jessica Paquette
[0.00%/25.00%] https://reviews.llvm.org/D46107 '[AArch64] Codegen for v8.2A dot product intrinsics' by Oliver Stannard
[0.00%/12.50%] https://reviews.llvm.org/D45541 '[globalisel] Update GlobalISel emitter to match new representation of extending loads' by Daniel Sanders
[0.00%/6.25%] https://reviews.llvm.org/D44386 '[x86] Introduce the pconfig/enclv instructions' by Gabor Buella

The first percentage in square brackets is the percentage of lines in
the patch-under-review that changes lines that I wrote. The second
percentage is the percentage of files that I made at least some
changes to out of all of the files touched by the patch-under-review.

Both the script and the heuristics are far from perfect, but I've
heard positive feedback from the few colleagues the script has been
sending a summary to every day - hearing that this does help them to
quickly find patches-under-review they can help to review.

The script takes quite some time to run (I typically see it running
for 2 to 3 hours on weekdays when it gets started by a cron job early
in the morning). There are 2 reasons why it takes a long time:

The REST api into Phabricator isn't very efficient, i.e. a lot of
uninteresting data needs to be fetched. The script tries to reduce this
overhead partly by caching info it has fetched on previous runs, so as
to not have to refetch lots of Phabricator state on each run.
The script uses git blame to find for each line of code in the patch who
wrote the original line of code being altered. git blame is
sloooowww....
Anyway - to run this script:

First install a virtualenv as follows (using Python2.7 - Python3 is
almost certainly not going to work at the moment):
$ virtualenv venv
$ . ./venv/bin/activate
$ pip install Phabricator

Then to run the script, looking for open reviews that could be done by
X.Y@company.com, run (in the venv):
$ python ./find_interesting_reviews.py X.Y@company.com

Please note that "X.Y@company.com" needs to be the exact email address
(capitalization is important) that the git LLVM repository knows the
person as. Multiple email addresses can be specified on the command
line. Note that the script as is will email the results to all email
addresses specified on the command line - so be careful not to spam
people accidentally!

Differential Revision: https://reviews.llvm.org/D46192

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332711 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agouse standard llvm cmake formatting for targets defined in plugin tests
Nico Weber [Fri, 18 May 2018 12:42:30 +0000 (12:42 +0000)]
use standard llvm cmake formatting for targets defined in plugin tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332709 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Improve documentation.
Clement Courbet [Fri, 18 May 2018 12:33:57 +0000 (12:33 +0000)]
[llvm-exegesis] Improve documentation.

Summary:
- Better flag names.
- Fix flag reference in doc.
- Add usage examples in doc.

Fixes PR37497.

Reviewers: gchatelet

Subscribers: llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D47015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332708 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoStackColoring: better handling of statically unreachable code
Than McIntosh [Fri, 18 May 2018 12:25:30 +0000 (12:25 +0000)]
StackColoring: better handling of statically unreachable code

Summary:
Avoid assert/crash during liveness calculation in situations where the
incoming machine function has statically unreachable BBs.

Fixes PR37130.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332707 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Fix commit message of previous commit.
Jonas Paulsson [Fri, 18 May 2018 12:07:16 +0000 (12:07 +0000)]
[SystemZ]  Fix commit message of previous commit.

Sorry, the commit comment for r332703 is completely broken.
My mind slipped - the right description would be:

In SystemZDAGToDAGISel::Select(), in the handling for SELECT_CCMASK:

Check if UpdateNodeOperands() returns a different SDNode and in that
case call ReplaceNode.

Review: Ulrich Weigand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332706 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
Alexander Ivchenko [Fri, 18 May 2018 11:58:25 +0000 (11:58 +0000)]
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)

This patch aims to match the changes introduced in gcc by
https://gcc.gnu.org/ml/gcc-cvs/2018-04/msg00534.html. The
IBT feature definition is removed, with the IBT instructions
being freely available on all X86 targets. The shadow stack
instructions are also being made freely available, and the
use of all these CET instructions is controlled by the module
flags derived from the -fcf-protection clang option. The hasSHSTK
option remains since clang uses it to determine availability of
shadow stack instruction intrinsics, but it is no longer directly used.

Comes with a clang patch (D46881).

Patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D46882

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332705 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Fold AHIMux in foldMemoryOperandImpl.
Jonas Paulsson [Fri, 18 May 2018 11:54:04 +0000 (11:54 +0000)]
[SystemZ]  Fold AHIMux in foldMemoryOperandImpl.

AHIMux can be folded the same way as AHI.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332703 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SimplifyCFG] Fix a debug invariant bug in FoldBranchToCommonDest()
David Stenberg [Fri, 18 May 2018 08:52:15 +0000 (08:52 +0000)]
[SimplifyCFG] Fix a debug invariant bug in FoldBranchToCommonDest()

Summary:
Fix a case where FoldBranchToCommonDest() would bail out from doing CSE
when encountering a debug intrinsic. Handle that by skipping past the
debug intrinsics.

Also, as a minor refactoring, rename checkCSEInPredecessor() to
tryCSEWithPredecessor() to make it a bit more clear that the function
may remove instructions.

Reviewers: fhahn, craig.topper, dblaikie, xbolva00

Reviewed By: fhahn, xbolva00

Subscribers: vsk, davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D46635

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332698 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Fix compile error on VS.
Clement Courbet [Fri, 18 May 2018 07:18:56 +0000 (07:18 +0000)]
[llvm-exegesis] Fix compile error on VS.

llvm::BitVector::const_set_bits_iterator is not formally a
ForwardIterator. Using it as such results in compile time errors on some
compilers:

FAILED: unittests/tools/llvm-exegesis/X86/CMakeFiles/LLVMExegesisX86Tests.dir/RegisterAliasingTest.cpp.obj
C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\INCLUDE\xutility(967): error C2794: 'iterator_category': is not a member of any direct or indirect base class of 'std::iterator_traits<_InIt>'
        with
        [
            _InIt=llvm::BitVector::const_set_bits_iterator
        ]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332697 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced
Shiva Chen [Fri, 18 May 2018 06:42:21 +0000 (06:42 +0000)]
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced

For RISCV branch instructions, we need to preserve relocation types when linker
relaxation enabled, so then linker could modify offset when the branch offsets
changed.

We preserve relocation types by define shouldForceRelocation.
IsResolved return by evaluateFixup will always false when shouldForceRelocation
return true. It will make RISCV MC Branch Relaxation always relax 16-bit
branches to 32-bit form, even if the symbol actually could be resolved.

To avoid 16-bit branches always relax to 32-bit form when linker relaxation
enabled, we add a new parameter WasForced to indicate that the symbol actually
couldn't be resolved and not forced by shouldForceRelocation return true.

RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with
unresolved symbols by (!IsResolved && !WasForced).

RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit
to 16-bit transformation in MC layer.

Differential Revision: https://reviews.llvm.org/D46350

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332696 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LICM] Extend the MustExecute scope
Serguei Katkov [Fri, 18 May 2018 04:56:28 +0000 (04:56 +0000)]
[LICM] Extend the MustExecute scope

CanProveNotTakenFirstIteration utility does not handle the case when
condition of the branch is a constant. Add its handling.

Reviewers: reames, anna, mkazantsev
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46996

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332695 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86DomainReassignment] Hopefully fix buildbot failure
Keno Fischer [Fri, 18 May 2018 04:36:38 +0000 (04:36 +0000)]
[X86DomainReassignment] Hopefully fix buildbot failure

The Darwin build bot failed with:
```
llc -mcpu=skylake-avx512 -mtriple=x86_64-unknown-linux-gnu domain-reassignment-test.ll -o - | llvm-mc
--
Exit Code: 134

Command Output (stderr):
--
Assertion failed: (MAI->hasSingleParameterDotFile()), function EmitFileDirective, file lib/MC/MCAsmStreamer.cpp, line 1087.
```

Looks like this is because the `llvm-mc` command was missing a triple
directive and defaulting to MachO. Add the triple option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332694 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-objcopy] Fix formatting
Alexander Shaposhnikov [Fri, 18 May 2018 04:18:41 +0000 (04:18 +0000)]
[llvm-objcopy] Fix formatting

Apply clang-format -i -style=llvm to llvm-objcopy.cpp
NFC.

Test plan: make check-all

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332693 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[asan] Add instrumentation support for Myriad
Walter Lee [Fri, 18 May 2018 04:10:38 +0000 (04:10 +0000)]
[asan] Add instrumentation support for Myriad

1. Define Myriad-specific ASan constants.

2. Add code to generate an outer loop that checks that the address is
   in DRAM range, and strip the cache bit from the address.  The
   former is required because Myriad has no memory protection, and it
   is up to the instrumentation to range-check before using it to
   index into the shadow memory.

3. Do not add an unreachable instruction after the error reporting
   function; on Myriad such function may return if the run-time has
   not been initialized.

4. Add a test.

Differential Revision: https://reviews.llvm.org/D46451

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332692 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug...
Eric Christopher [Fri, 18 May 2018 03:13:08 +0000 (03:13 +0000)]
Revert "Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission.""

This reapplies commits: r330271, r330592, r330779.

    [DEBUG] Initial adaptation of NVPTX target for debug info emission.

    Summary:
    Patch adds initial emission of the debug info for NVPTX target.
    Currently, only .file and .loc directives are emitted, everything else is
    commented out to not break the compilation of Cuda.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332689 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTidy comment up a bit.
Eric Christopher [Fri, 18 May 2018 02:39:57 +0000 (02:39 +0000)]
Tidy comment up a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332687 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix unused lambda capture.
Eli Friedman [Fri, 18 May 2018 02:11:25 +0000 (02:11 +0000)]
Fix unused lambda capture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332686 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MachineOutliner] Count savings from outlining in bytes.
Eli Friedman [Fri, 18 May 2018 01:52:16 +0000 (01:52 +0000)]
[MachineOutliner] Count savings from outlining in bytes.

Counting the number of instructions is both unintuitive and inaccurate.
On AArch64, this only affects the generated remarks and certain rare
pseudo-instructions, but it will have a bigger impact on other targets.

Differential Revision: https://reviews.llvm.org/D46921

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332685 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86DomainReassignment] Don't compare stack-allocated values by address
Keno Fischer [Fri, 18 May 2018 01:03:01 +0000 (01:03 +0000)]
[X86DomainReassignment] Don't compare stack-allocated values by address

Summary:
The Closure allocated in the main loop is allocated on the stack. However,
later in the code its address is taken (and used for comparisons). This
obviously doesn't work. In fact, the Closure will get the same stack address
during every loop iteration, rendering the check that intended to identify
Closure conflicts entirely ineffective. Fix this bug by giving every Closure
a unique ID and using that for comparison. Alternatively, we could heap
allocate the closure object.

Fixes PR37396
Fixes JuliaLang/julia#27032

Reviewers: craig.topper, guyblank

Reviewed By: craig.topper

Subscribers: vchuravy, llvm-commits

Differential Revision: https://reviews.llvm.org/D46800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332682 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86DomainReassignment] Don't delete IMPLICIT_DEF nodes
Keno Fischer [Fri, 18 May 2018 00:40:52 +0000 (00:40 +0000)]
[X86DomainReassignment] Don't delete IMPLICIT_DEF nodes

Summary:
We cannot simply delete IMPLICIT_DEF nodes. They may be used
later (e.g. by a PHI) and deleting them will cause later passes (e.g.
LiveVariables) to crash. However, it seems fine to ignore them for
purposes of the domain reassignment (as we do with PHI).

Fixes PR37430
Fixes JuliaLang/julia#27080

Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46797

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332680 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoResubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes."
Zachary Turner [Thu, 17 May 2018 22:55:15 +0000 (22:55 +0000)]
Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes."

This fixes the remaining failing tests, so resubmitting with no
functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332676 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoSupport: Add a raw_ostream::write_zeros() function. NFCI.
Peter Collingbourne [Thu, 17 May 2018 22:11:43 +0000 (22:11 +0000)]
Support: Add a raw_ostream::write_zeros() function. NFCI.

This will eventually replace MCObjectWriter::WriteZeros.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332675 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r332657: "[AA] cfl-anders-aa with field sensitivity"
George Burgess IV [Thu, 17 May 2018 21:56:39 +0000 (21:56 +0000)]
Revert r332657: "[AA] cfl-anders-aa with field sensitivity"

I don't believe the person who LGTMed this review has appropriate
context on this code. I apologize if I'm wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332674 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/SI: Don't promote alloca to vector for atomic load/store
Changpeng Fang [Thu, 17 May 2018 21:49:44 +0000 (21:49 +0000)]
AMDGPU/SI: Don't promote alloca to vector for atomic load/store

Summary:
  Don't promote alloca to vector for atomic load/store

Reviewer:
  arsenm

Differential Revision:
  https://reviews.llvm.org/D46085

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332673 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes."
Zachary Turner [Thu, 17 May 2018 21:49:25 +0000 (21:49 +0000)]
Revert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes."

A few tests haven't been properly updated, so reverting while
I have time to investigate proper fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332672 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[pdb] Change /DEBUG:GHASH to emit 8 byte hashes.
Zachary Turner [Thu, 17 May 2018 21:22:48 +0000 (21:22 +0000)]
[pdb] Change /DEBUG:GHASH to emit 8 byte hashes.

Previously we emitted 20-byte SHA1 hashes.  This is overkill
for identifying debug info records, and has the negative side
effect of making object files bigger and links slower.  By
using only the last 8 bytes of a SHA1, we get smaller object
files and ~10% faster links.

This modifies the format of the .debug$H section by adding a new
value for the hash algorithm field, so that the linker will still
work when its object files have an old format.

Differential Revision: https://reviews.llvm.org/D46855

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332669 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Add Wasm personality and isScopedEHPersonality()
Heejin Ahn [Thu, 17 May 2018 20:52:03 +0000 (20:52 +0000)]
[WebAssembly] Add Wasm personality and isScopedEHPersonality()

Summary:
- Add wasm personality function
- Re-categorize the existing `isFuncletEHPersonality()` function into
two different functions: `isFuncletEHPersonality()` and
`isScopedEHPersonality(). This becomes necessary as wasm EH uses scoped
EH instructions (catchswitch, catchpad/ret, and cleanuppad/ret) but not
outlined funclets.
- Changed some callsites of `isFuncletEHPersonality()` to
`isScopedEHPersonality()` if they are related to scoped EH IR-level
stuff.

Reviewers: majnemer, dschuff, rnk

Subscribers: jfb, sbc100, jgravelle-google, eraman, JDevlieghere, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D45559

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332667 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ORC] Consolidate materialization errors, and generate them in VSO's
Lang Hames [Thu, 17 May 2018 20:48:58 +0000 (20:48 +0000)]
[ORC] Consolidate materialization errors, and generate them in VSO's
notifyFailed method rather than passing in an error generator.

VSO::notifyFailed is responsible for notifying queries that they will not
succeed due to error. In practice the queries don't care about the details
of the failure, just the fact that a failure occurred for some symbols.
Having VSO::notifyFailed take care of this simplifies the interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332666 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ORC] Make MaterializationResponsibility's constructor private.
Lang Hames [Thu, 17 May 2018 20:48:50 +0000 (20:48 +0000)]
[ORC] Make MaterializationResponsibility's constructor private.

MaterializationResponsibility instances should be created by
MaterializationUnits only. Making the constructor private enforces this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332665 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[codeview] Include record prefix in global type hashing
Reid Kleckner [Thu, 17 May 2018 20:47:22 +0000 (20:47 +0000)]
[codeview] Include record prefix in global type hashing

The prefix includes type kind, which is important to preserve. Two
different type leafs can easily have the same interior record contents
as another type.

We ran into this issue in PR37492 where a bitfield type record collided
with a const modifier record. Their contents were bitwise identical, but
their kinds were different.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332664 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARC, Nios2: Silence build warnings. NFCI.
Peter Collingbourne [Thu, 17 May 2018 20:46:01 +0000 (20:46 +0000)]
ARC, Nios2: Silence build warnings. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332663 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AA] cfl-anders-aa with field sensitivity
David Bolvansky [Thu, 17 May 2018 20:23:33 +0000 (20:23 +0000)]
[AA] cfl-anders-aa with field sensitivity

Summary:
There was some unfinished work started for offset tracking in CFLGraph by the author of implementation of Andersen algorithm. This work was completed and support for field sensitivity was added to the core of Andersen algorithm.

The performance results seem promising.

SPEC2006 int_base score was increased by 1.1 % (I  compared clang 6.0 with clang 6.0 with this patch). The avergae compile time was increased by +- 1 % according my measures with small and medium C/C++ projects (I did not tested it on the large projects with milions of lines of code)

Reviewers: chandlerc, george.burgess.iv, rja

Reviewed By: rja

Subscribers: rja, llvm-commits

Differential Revision: https://reviews.llvm.org/D46282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332657 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.
Diego Caballero [Thu, 17 May 2018 19:24:47 +0000 (19:24 +0000)]
[LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.

Patch #3 from VPlan Outer Loop Vectorization Patch Series #1
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).

Expected to be NFC for the current inner loop vectorization path. It
introduces the basic algorithm to build the VPlan plain CFG (single-level
CFG, no hierarchical CFG (H-CFG), yet) in the VPlan-native vectorization
path using VPInstructions. It includes:
  - VPlanHCFGBuilder: Main class to build the VPlan H-CFG (plain CFG without nested regions, for now).
  - VPlanVerifier: Main class with utilities to check the consistency of a H-CFG.
  - VPlanBlockUtils: Main class with utilities to manipulate VPBlockBases in VPlan.

Reviewers: rengolin, fhahn, mkuper, mssimpso, a.elovikov, hfinkel, aprantl.

Differential Revision: https://reviews.llvm.org/D44338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332654 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd a limit for phi folding instcombine
Xinliang David Li [Thu, 17 May 2018 19:24:03 +0000 (19:24 +0000)]
Add a limit for phi folding instcombine

Differential Revision: http://reviews.llvm.org/D47023

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332653 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Make Dispatch a subclass of Stage.
Matt Davis [Thu, 17 May 2018 19:22:29 +0000 (19:22 +0000)]
[llvm-mca] Make Dispatch a subclass of Stage.

Summary:
The logic of dispatch remains the same, but now DispatchUnit is a Stage (DispatchStage).

This change has the benefit of simplifying the backend runCycle() code.
The same logic applies, but it belongs to different components now.  This is just a start,
eventually we will need to remove the call to the DispatchStage in Scheduler.cpp, but
that will be a separate patch.  This change is mostly a renaming and moving of existing logic.

This change also encouraged me to remove the Subtarget (STI) member from the
Backend class.  That member was used to initialize the other members of Backend
and to eventually call DispatchUnit::dispatch().  Now that we have Stages, we
can eliminate this by instantiating the DispatchStage with everything it needs
at the time of construction (e.g., Subtarget).  That change allows us to call
DispatchStage::execute(IR) as we expect to call execute() for all other stages.

Once we add the Stage list (D46907) we can more cleanly call preExecute() on
all of the stages, DispatchStage, will probably wrap cycleEvent() in that
case.

Made some formatting and minor cleanups to README.txt.  Some of the text
was re-flowed to stay within 80 cols.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb, courbet

Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332652 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[x86] preserve test intent by removing undef
Sanjay Patel [Thu, 17 May 2018 18:43:44 +0000 (18:43 +0000)]
[x86] preserve test intent by removing undef

We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332648 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-pdbutil] Dump struct/class/union sizes in the minimal dump format
Reid Kleckner [Thu, 17 May 2018 18:33:42 +0000 (18:33 +0000)]
[llvm-pdbutil] Dump struct/class/union sizes in the minimal dump format

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332645 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Debugify] Print the output to stderr
Anastasis Grammenos [Thu, 17 May 2018 18:19:58 +0000 (18:19 +0000)]
[Debugify] Print the output to stderr

Currently debugify prints it's output to stdout,
with this patch all the output generated goes to stderr.

This change lets us use debugify without taking away
the ability to pipe the output to other llvm tools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332642 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Separate base from offset in lowerGlobalAddress
Sameer AbuAsal [Thu, 17 May 2018 18:14:53 +0000 (18:14 +0000)]
[RISCV] Separate base from offset in lowerGlobalAddress

Summary:
When lowering global address, lower the base as a TargetGlobal first then
 create an SDNode for the offset separately and chain it to the address calculation

 This optimization will create a DAG where the base address of a global access will
 be reused between different access. The offset can later be folded into the immediate
 part of the memory access instruction.

  With this optimization we generate:

    lui a0, %hi(s)
    addi a0, a0, %lo(s) ; shared base address.

    addi a1, zero, 20 ; 2 instructions per access.
    sw a1, 44(a0)

    addi a1, zero, 10
    sw a1, 8(a0)

    addi a1, zero, 30
    sw a1, 80(a0)

    Instead of:

    lui a0, %hi(s+44) ; 3 instructions per access.
    addi a1, zero, 20
    sw a1, %lo(s+44)(a0)

    lui a0, %hi(s+8)
    addi a1, zero, 10
    sw a1, %lo(s+8)(a0)

    lui a0, %hi(s+80)
    addi a1, zero, 30
    sw a1, %lo(s+80)(a0)

    Which will save one instruction per access.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits

Differential Revision: https://reviews.llvm.org/D46989

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332641 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[x86] preserve test intent by removing undef
Sanjay Patel [Thu, 17 May 2018 18:13:58 +0000 (18:13 +0000)]
[x86] preserve test intent by removing undef

We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332640 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] preserve test intent by removing undef
Sanjay Patel [Thu, 17 May 2018 18:09:56 +0000 (18:09 +0000)]
[ARM] preserve test intent by removing undef

We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332638 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] preserve test intent by removing undef
Sanjay Patel [Thu, 17 May 2018 18:08:27 +0000 (18:08 +0000)]
[ARM] preserve test intent by removing undef

We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

Follow-up to:
https://reviews.llvm.org/rL332538
...because that change wasn't enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332637 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] preserve test intent by removing undef
Sanjay Patel [Thu, 17 May 2018 18:07:02 +0000 (18:07 +0000)]
[AArch64] preserve test intent by removing undef

We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

Follow-up to:
https://reviews.llvm.org/rL332534
...because that change wasn't enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332636 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Implement MC layer support for the tail pseudoinstruction
Mandeep Singh Grang [Thu, 17 May 2018 17:31:27 +0000 (17:31 +0000)]
[RISCV] Implement MC layer support for the tail pseudoinstruction

Summary:
This patch implements MC support for tail psuedo instruction.
A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits

Differential Revision: https://reviews.llvm.org/D46221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332634 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] MC: Fix typo in comment
Sam Clegg [Thu, 17 May 2018 17:15:15 +0000 (17:15 +0000)]
[WebAssembly] MC: Fix typo in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332632 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CMake] Support runtimes in distributions
Chris Bieneman [Thu, 17 May 2018 16:58:44 +0000 (16:58 +0000)]
[CMake] Support runtimes in distributions

Summary:
This patch adds a new internal variable
LLVM_RUNTIME_DISTRIBUTION_COMPONENTS which specifies distribution
components that are part of runtime projects, and thus should be exposed
from runtime configuraitons up into the top-level CMake configurations.

This is required for allowing runtime components to be included in
LLVM_DISTRIBUTION_COMPONENTS because we verify that the build and
install targets exist for every component specified for the
distribution.

Without this patch runtimes and builtins can only be included in
distributions in whole, not by component.

Reviewers: phosek

Reviewed By: phosek

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332631 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix typo in declaring code-block snippet
Simon Pilgrim [Thu, 17 May 2018 16:58:42 +0000 (16:58 +0000)]
Fix typo in declaring code-block snippet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332630 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CMake] Make optimizing sanitizer builds optional
Chris Bieneman [Thu, 17 May 2018 16:55:29 +0000 (16:55 +0000)]
[CMake] Make optimizing sanitizer builds optional

This behavior has been the default for a long time, so the default value is On, however this can make it difficult to debug sanitizer failures, so we should have an option to turn it off.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332628 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Add an example showing how to get Intel assembly syntax
Andrea Di Biagio [Thu, 17 May 2018 16:48:53 +0000 (16:48 +0000)]
[llvm-mca] Add an example showing how to get Intel assembly syntax

Patch by Jeff Muizelaar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332627 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Split WriteCMOV + WriteCMOV2 scheduler classes
Simon Pilgrim [Thu, 17 May 2018 16:47:30 +0000 (16:47 +0000)]
[X86] Split WriteCMOV + WriteCMOV2 scheduler classes

Handle SNB+ targets which treat CMOVA/CMOVBE specially due to partial EFLAGS handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332626 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite...
Changpeng Fang [Thu, 17 May 2018 16:45:01 +0000 (16:45 +0000)]
AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.

Summary:
  The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocks
to one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working.

In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops.
This will make CFG with infinite loops be structurized.

Reviewer:
  nhaehnle

Differential Revision:
  https://reviews.llvm.org/D46340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332625 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Add support for Global INValidate ASE
Petar Jovanovic [Thu, 17 May 2018 16:30:32 +0000 (16:30 +0000)]
[mips] Add support for Global INValidate ASE

This includes

  Instructions: ginvi, ginvt,

  Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

  Attribute: ginv

  .MIPS.abiflags: GINV (0x20000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D46268

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332624 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Propagate the nsw/nuw flags from the add in the 'shifty' abs pattern...
Craig Topper [Thu, 17 May 2018 16:29:52 +0000 (16:29 +0000)]
[InstCombine] Propagate the nsw/nuw flags from the add in the 'shifty' abs pattern to the sub in the select version.

According to alive this is valid. I'm hoping to use this to make an assumption that the sign bit is zero after this sequence. The only way it wouldn't be is if the input was INT__MIN, but by preserving the flags we can make doing this to INT_MIN UB.

The nuw flags is weird because it creates such a contradiction that the original number would have to be positive meaning we could remove the select entirely, but we don't get that far.

Differential Revision: https://reviews.llvm.org/D46988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332623 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca][X86] Add CMOV test files
Simon Pilgrim [Thu, 17 May 2018 16:29:12 +0000 (16:29 +0000)]
[llvm-mca][X86] Add CMOV test files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332622 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Set isReMaterializable on ADDI and LUI instructions
Alex Bradbury [Thu, 17 May 2018 15:51:37 +0000 (15:51 +0000)]
[RISCV] Set isReMaterializable on ADDI and LUI instructions

The isReMaterlizable flag is somewhat confusing, unlike most other instruction
flags it is currently interpreted as a hint (mightBeRematerializable would be
a better name). While LUI is always rematerialisable, for an instruction like
ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable
will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn
calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on
the logic in the latter to pick out instances of ADDI that really are
rematerializable.

The isReMaterializable flag does make a difference on a variety of test
programs. The recently committed remat.ll test case demonstrates how stack
usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the
Proc0 function in dhrystone reduces from 192 bytes to 112 bytes.

For the sake of completeness, this patch also implements
RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of
places, it doesn't seem to result in different codegen for any programs I've
thrown at it. However, it is called in the rematerialisation codepath and it
seems sensible to implement something correct here.

Differential Revision: https://reviews.llvm.org/D46182

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332617 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUB
Simon Pilgrim [Thu, 17 May 2018 15:43:23 +0000 (15:43 +0000)]
[X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332616 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Hide unrelated flags from the -help output.
Andrea Di Biagio [Thu, 17 May 2018 15:35:14 +0000 (15:35 +0000)]
[llvm-mca] Hide unrelated flags from the -help output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332615 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Remove redudant explicit template instantiations.
Clement Courbet [Thu, 17 May 2018 14:37:31 +0000 (14:37 +0000)]
[llvm-exegesis] Remove redudant explicit template instantiations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332611 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoIn thin and full LTO + CFI, direct function calls may go through jump table
Dmitry Mikulin [Thu, 17 May 2018 14:29:07 +0000 (14:29 +0000)]
In thin and full LTO + CFI, direct function calls may go through jump table
entries to reach the target. Since these calls don't require type checks,
we can short-circuit them to their real targets.

Differential Revision: https://reviews.llvm.org/D46326

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332610 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Write out inconsistencies to a file.
Clement Courbet [Thu, 17 May 2018 13:41:28 +0000 (13:41 +0000)]
[llvm-exegesis] Write out inconsistencies to a file.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D47013

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332608 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Use addAliasForDirective for data directives
Alex Bradbury [Thu, 17 May 2018 13:21:18 +0000 (13:21 +0000)]
[Hexagon] Use addAliasForDirective for data directives

Data directives such as .word, .half, .hword are currently parsed using
HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from
AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in
favour of using addAliasForDirective.

Differential Revision: https://reviews.llvm.org/D46999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332607 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Split WriteADC/WriteADCRMW scheduler classes
Simon Pilgrim [Thu, 17 May 2018 12:43:42 +0000 (12:43 +0000)]
[X86] Split WriteADC/WriteADCRMW scheduler classes

For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332605 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Disable failing ARM assembler tests.
Clement Courbet [Thu, 17 May 2018 12:41:56 +0000 (12:41 +0000)]
[llvm-exegesis] Disable failing ARM assembler tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332604 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] add flag -all-views and flag -all-stats.
Andrea Di Biagio [Thu, 17 May 2018 12:27:03 +0000 (12:27 +0000)]
[llvm-mca] add flag -all-views and flag -all-stats.

Flag -all-views enables all the views.
Flag -all-stats enables all the views that print hardware statistics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332602 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Analysis: detect clustering inconsistencies.
Clement Courbet [Thu, 17 May 2018 12:25:18 +0000 (12:25 +0000)]
[llvm-exegesis] Analysis: detect clustering inconsistencies.

Summary:
Warn on instructions that should have the same performance
characteristics according to the sched model but actually
differ in their benchmarks.

Next step: Make the display nicer to browse, I was thinking maybe html.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D46945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332601 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Disable the tests failing on buildbots while we investigate.
Clement Courbet [Thu, 17 May 2018 11:55:08 +0000 (11:55 +0000)]
[llvm-exegesis] Disable the tests failing on buildbots while we investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332600 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Commenting (NFC)
Jonas Paulsson [Thu, 17 May 2018 11:53:56 +0000 (11:53 +0000)]
[SystemZ]  Commenting (NFC)

Some minor commenting in scheduler files.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332599 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis][NFC] Remove dead function.
Clement Courbet [Thu, 17 May 2018 11:51:49 +0000 (11:51 +0000)]
[llvm-exegesis][NFC] Remove dead function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332597 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca][X86] Add ADX test files
Simon Pilgrim [Thu, 17 May 2018 11:32:38 +0000 (11:32 +0000)]
[llvm-mca][X86] Add ADX test files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332595 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix r332592 : X86 tests should use the X86 target, not the native targets.
Clement Courbet [Thu, 17 May 2018 11:31:24 +0000 (11:31 +0000)]
Fix r332592 : X86 tests should use the X86 target, not the native targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332594 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoreland r332579: [llvm-exegesis] Update to cover latency through another opcode.
Clement Courbet [Thu, 17 May 2018 10:52:18 +0000 (10:52 +0000)]
reland r332579: [llvm-exegesis] Update to cover latency through another opcode.

Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.

https://reviews.llvm.org/D46821

(with fixed ARM tests)

Authored by Guillaume Chatelet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332592 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SNB] Minor scheduler cleanup
Simon Pilgrim [Thu, 17 May 2018 10:36:29 +0000 (10:36 +0000)]
[X86][SNB] Minor scheduler cleanup

Merge 2 instregex and explain the VMOVDQArr/MOVDQArr difference

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332591 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) store...
Sander de Smalen [Thu, 17 May 2018 09:05:41 +0000 (09:05 +0000)]
[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) store instructions.

Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332584 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRequire DominatorTree when requiring/preserving LoopInfo in the old pass manager
Mikael Holmen [Thu, 17 May 2018 09:05:40 +0000 (09:05 +0000)]
Require DominatorTree when requiring/preserving LoopInfo in the old pass manager

Summary:
Require DominatorTree when requiring/preserving LoopInfo in the old pass manager

BreakCriticalEdges tries to keep LoopInfo and DominatorTree updated if they
exist. However, since commit r321653 and r321805, to update LoopInfo we
must have a DominatorTree, or we will hit an assert.

To fix this we now make a couple of passes that only required/preserved
LoopInfo also require DominatorTree.

This solves PR37334.

Reviewers: eli.friedman, efriedma

Reviewed By: efriedma

Subscribers: efriedma, llvm-commits

Differential Revision: https://reviews.llvm.org/D46829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332583 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Analysis] Only use _unlocked stdio functions on linux
Martin Storsjo [Thu, 17 May 2018 08:16:08 +0000 (08:16 +0000)]
[Analysis] Only use _unlocked stdio functions on linux

The existing comment said that the functions were available only
on GNU/Linux (and on certain Android versions), but only checked
T.isGNUEnvironment() which also is true on MinGW (for arch-windows-gnu
triplets), which doesn't have such functions.

Existing checks in the initialize function in TargetLibraryInfo.cpp
also use only T.isOSLinux() to check for glibc features.

This fixes use of stdio on MinGW.

Differential Revision: https://reviews.llvm.org/D47002

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332581 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r332579 "[llvm-exegesis] Update to cover latency through another opcode."
Clement Courbet [Thu, 17 May 2018 08:12:29 +0000 (08:12 +0000)]
Revert r332579 "[llvm-exegesis] Update to cover latency through another opcode."

The revision failed to update the ARM tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332580 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Update to cover latency through another opcode.
Clement Courbet [Thu, 17 May 2018 07:38:21 +0000 (07:38 +0000)]
[llvm-exegesis] Update to cover latency through another opcode.

    Restructuring the code to measure latency and uops.
    The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
    It now uses BitVector instead of Graph for performance reasons.

    https://reviews.llvm.org/D46821

    Authored by Guillaume Chatelet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332579 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SROA] Handle PHI with multiple duplicate predecessors
Bjorn Pettersson [Thu, 17 May 2018 07:21:41 +0000 (07:21 +0000)]
[SROA] Handle PHI with multiple duplicate predecessors

Summary:
The verifier accepts PHI nodes with multiple entries for the
same basic block, as long as the value is the same.

As seen in PR37203, SROA did not handle such PHI nodes properly
when speculating loads over the PHI, since it inserted multiple
loads in the predecessor block and changed the PHI into having
multiple entries for the same basic block, but with different
values.

This patch teaches SROA to reuse the same speculated load for
each PHI duplicate entry in such situations.

Resolves: https://bugs.llvm.org/show_bug.cgi?id=37203

Reviewers: uabelho, chandlerc, hfinkel, bkramer, efriedma

Reviewed By: efriedma

Subscribers: dberlin, efriedma, llvm-commits

Differential Revision: https://reviews.llvm.org/D46426

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332577 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SROA] pr37267: fix assertion failure in integer widening
Hiroshi Inoue [Thu, 17 May 2018 06:32:17 +0000 (06:32 +0000)]
[SROA] pr37267: fix assertion failure in integer widening

The current integer widening does not support rewriting partial split slices in rewriteIntegerStore (and rewriteIntegerLoad).
This patch adds explicit checks for this case in isIntegerWideningViableForSlice.
Before r322533, splitting is allowed only for the whole-alloca slice and hence the above case is implicitly rejected by another check `if (DL.getTypeStoreSize(ValueTy) > Size)` because whole-alloca slice is larger than the partition.

Differential Revision: https://reviews.llvm.org/D46750

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332575 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Add support for .half, .hword, .word, .dword directives
Alex Bradbury [Thu, 17 May 2018 05:58:08 +0000 (05:58 +0000)]
[RISCV] Add support for .half, .hword, .word, .dword directives

These directives are recognised by gas. Support is added through the use of
addAliasForDirective.

Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data
directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332574 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add OptForSize to a couple load folding patterns. Remove some bad FIXME comments.
Craig Topper [Thu, 17 May 2018 05:41:11 +0000 (05:41 +0000)]
[X86] Add OptForSize to a couple load folding patterns. Remove some bad FIXME comments.

The FIXME comments were about preventing load folding to avoid a partial xmm update. But these instructions use GPR as input when the load isn't folded. This won't help prevent a partial xmm update.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332573 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CMake] Support building shared library for Fuchsia
Petr Hosek [Thu, 17 May 2018 03:39:03 +0000 (03:39 +0000)]
[CMake] Support building shared library for Fuchsia

Fuchsia uses ELF as a file format and LLD as the linker so we can
use the same implementation as other ELF based platforms.

Differential Revision: https://reviews.llvm.org/D46991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332570 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Thumb2] fix typo in test from r332548
Sanjay Patel [Thu, 17 May 2018 03:24:25 +0000 (03:24 +0000)]
[Thumb2] fix typo in test from r332548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332569 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMark test with "REQUIRES: shell" since it directly invokes "sh" and was failing on...
Douglas Yung [Thu, 17 May 2018 01:36:25 +0000 (01:36 +0000)]
Mark test with "REQUIRES: shell" since it directly invokes "sh" and was failing on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332563 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] Move lsr test. NFC.
Stanislav Mekhanoshin [Thu, 17 May 2018 01:30:51 +0000 (01:30 +0000)]
[AMDGPU] Move lsr test. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332562 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Fix the opcode number for i64.load16_u.
Dan Gohman [Thu, 17 May 2018 00:14:13 +0000 (00:14 +0000)]
[WebAssembly] Fix the opcode number for i64.load16_u.

Fixes PR37488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332561 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs iterator_range...
Craig Topper [Wed, 16 May 2018 23:39:27 +0000 (23:39 +0000)]
[CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs iterator_range and calling begin. NFC

Defs are well defined to come first in MachineInstr operand list. No need for a more complex indirection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332559 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert 332508 as it caused problems in the clang test suite.
Greg Clayton [Wed, 16 May 2018 23:29:36 +0000 (23:29 +0000)]
Revert 332508 as it caused problems in the clang test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332555 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[STLExtras] Add size() for ranges, and remove distance()
Vedant Kumar [Wed, 16 May 2018 23:20:42 +0000 (23:20 +0000)]
[STLExtras] Add size() for ranges, and remove distance()

r332057 introduced distance() for ranges. Based on post-commit feedback,
this renames distance() to size(). The new size() is also only enabled
when the operation is O(1).

Differential Revision: https://reviews.llvm.org/D46976

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332551 91177308-0d34-0410-b5e6-96231b3b80d8