OSDN Git Service
Craig Topper [Thu, 1 Mar 2018 22:32:25 +0000 (22:32 +0000)]
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code.
Differential Revision: https://reviews.llvm.org/D42679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326500
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Simon Pilgrim [Thu, 1 Mar 2018 22:22:31 +0000 (22:22 +0000)]
[X86][MMX] Improve handling of 64-bit MMX constants
64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type.
This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register.
I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats).
Differential Revision: https://reviews.llvm.org/D43616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326497
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Craig Topper [Thu, 1 Mar 2018 22:15:39 +0000 (22:15 +0000)]
[SelectionDAG] Support some SimplifySetCC cases for comparing against vector splats of constants.
This supports things like
(setcc ugt X, 0) -> (setcc ne X, 0)
I've restricted to only make changes to vectors before legalize ops because I doubt all targets have accurate condition code legality information for vectors given how little we did before.
Differential Revision: https://reviews.llvm.org/D42948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326495
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Simon Pilgrim [Thu, 1 Mar 2018 22:05:40 +0000 (22:05 +0000)]
[X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326494
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Krzysztof Parzyszek [Thu, 1 Mar 2018 21:54:08 +0000 (21:54 +0000)]
[Hexagon] Add trap1 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326492
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Adrian Prantl [Thu, 1 Mar 2018 21:53:17 +0000 (21:53 +0000)]
Add an llc testcase analogous to test/LTO/X86/strip-debug-info.ll
rdar://problem/
37963669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326491
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Matt Arsenault [Thu, 1 Mar 2018 21:25:30 +0000 (21:25 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326490
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Matt Arsenault [Thu, 1 Mar 2018 21:25:25 +0000 (21:25 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for G_OR
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326489
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Simon Pilgrim [Thu, 1 Mar 2018 21:21:30 +0000 (21:21 +0000)]
[X86][SSE] Regenerate float to/from i8/i16 vector tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326488
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Matt Arsenault [Thu, 1 Mar 2018 21:20:44 +0000 (21:20 +0000)]
AMDGPU/GlobalISel: Remove default register mapping
This crashes for some opcodes, which prevents the SelectionDAG
fallback from working.
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326487
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Evandro Menezes [Thu, 1 Mar 2018 21:17:36 +0000 (21:17 +0000)]
[AArch64] Clean up code (NFC)
Clean up a couple of functions in `AArch64TargetLowering` by removing
redundant statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326486
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Simon Pilgrim [Thu, 1 Mar 2018 21:13:26 +0000 (21:13 +0000)]
[X86][SSE] Regenerate odd sized sext/zext tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326484
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Matt Arsenault [Thu, 1 Mar 2018 21:08:51 +0000 (21:08 +0000)]
AMDGPU/GlobalISel: Use a more correct getValueMapping
This was finding the wrong size registers for anything with
more than 2 components.
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326483
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Matt Arsenault [Thu, 1 Mar 2018 20:59:44 +0000 (20:59 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326482
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Matt Arsenault [Thu, 1 Mar 2018 20:56:21 +0000 (20:56 +0000)]
AMDGPU/GlobalISel: Mark i32->i64 zext as legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326481
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Martin Storsjo [Thu, 1 Mar 2018 20:42:28 +0000 (20:42 +0000)]
[AArch64] Add support for secrel add/load/store relocations for COFF
Differential Revision: https://reviews.llvm.org/D43288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326480
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Matt Arsenault [Thu, 1 Mar 2018 20:40:55 +0000 (20:40 +0000)]
AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326479
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Matt Arsenault [Thu, 1 Mar 2018 20:24:37 +0000 (20:24 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326477
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Craig Topper [Thu, 1 Mar 2018 20:05:09 +0000 (20:05 +0000)]
[SimplifyLibCalls] Update an obviously copy and pasted header comment to match this file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326475
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Craig Topper [Thu, 1 Mar 2018 20:05:07 +0000 (20:05 +0000)]
[InstCombine] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326474
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Matt Arsenault [Thu, 1 Mar 2018 19:27:10 +0000 (19:27 +0000)]
AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326472
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Matt Arsenault [Thu, 1 Mar 2018 19:22:05 +0000 (19:22 +0000)]
AMDGPU/GlobalISel: Make i32 mul legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326471
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Matt Arsenault [Thu, 1 Mar 2018 19:16:52 +0000 (19:16 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326470
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Matt Arsenault [Thu, 1 Mar 2018 19:13:30 +0000 (19:13 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326468
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Matt Arsenault [Thu, 1 Mar 2018 19:09:25 +0000 (19:09 +0000)]
AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copies
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326467
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Matt Arsenault [Thu, 1 Mar 2018 19:09:21 +0000 (19:09 +0000)]
AMDGPU/GlobalISel: Make i32 xor legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326466
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Matt Arsenault [Thu, 1 Mar 2018 19:09:16 +0000 (19:09 +0000)]
AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326465
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Matt Arsenault [Thu, 1 Mar 2018 19:04:25 +0000 (19:04 +0000)]
AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal
Patch by Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326464
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Sam Clegg [Thu, 1 Mar 2018 18:48:08 +0000 (18:48 +0000)]
[WebAssembly] Fix broken gcc build after rL326454
The gcc builders were broken by rL326454
See: https://reviews.llvm.org/D43921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326460
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Artem Belevich [Thu, 1 Mar 2018 18:28:45 +0000 (18:28 +0000)]
[NVPTX] use pattern matching to lower int_nvvm_match_all_sync*.
Now that patterns can handle intrinsics returning multiple results,
use tablegen'ed pattern matching instead of custom lowering.
Differential Revision: https://reviews.llvm.org/D43890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326457
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Sam Clegg [Thu, 1 Mar 2018 18:06:21 +0000 (18:06 +0000)]
[WebAssembly] Use uint8_t for single byte values to match the spec
The original BinaryEncoding.md document used to specify that
these values were `varint7`, but the official spec lists them
explicitly as single byte values and not LEB.
A similar change for wabt is in flight:
https://github.com/WebAssembly/wabt/pull/782
Differential Revision: https://reviews.llvm.org/D43921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326454
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Zachary Turner [Thu, 1 Mar 2018 18:00:29 +0000 (18:00 +0000)]
[PDB] Defer writing the build id until the rest of the PDB is written.
For now this is NFC, but this small refactor opens the door to
letting us embed a hash of the PDB in the build id field of the
PDB.
Differential Revision: https://reviews.llvm.org/D43913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326453
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Alexander Timofeev [Thu, 1 Mar 2018 17:36:43 +0000 (17:36 +0000)]
[AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not found
Differential revision: https://reviews.llvm.org./D43334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326451
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Krzysztof Parzyszek [Thu, 1 Mar 2018 17:03:26 +0000 (17:03 +0000)]
[Hexagon] Add guest registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326450
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Sanjay Patel [Thu, 1 Mar 2018 16:28:32 +0000 (16:28 +0000)]
[InstCombine] remove stale comments for tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326448
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Stefan Pintilie [Thu, 1 Mar 2018 16:16:08 +0000 (16:16 +0000)]
[Power9] Add missing instructions to the Power 9 scheduler
Adding more instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.
Differential Revision: https://reviews.llvm.org/D43899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326447
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Nicholas Wilson [Thu, 1 Mar 2018 15:55:59 +0000 (15:55 +0000)]
[WebAssembly] Update pre-generated test files to match latest llc output. NFC.
The ordering of llc's output was changed in rL326334.
Differential Revision: https://reviews.llvm.org/D43941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326445
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Sanjay Patel [Thu, 1 Mar 2018 15:50:26 +0000 (15:50 +0000)]
[InstCombine] simplify code for (X*Y) * X => (X*X) * Y ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326444
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Sebastian Pop [Thu, 1 Mar 2018 15:47:39 +0000 (15:47 +0000)]
[AArch64] generate vuzp instead of mov
when a BUILD_VECTOR is created out of a sequence of EXTRACT_VECTOR_ELT with a
specific pattern sequence, either <0, 2, 4, ...> or <1, 3, 5, ...>, replace the
BUILD_VECTOR with either vuzp1 or vuzp2.
With this patch LLVM generates the following code for the first function fun1 in the testcase:
adrp x8, .LCPI0_0
ldr q0, [x8, :lo12:.LCPI0_0]
tbl v0.16b, { v0.16b }, v0.16b
ext v1.16b, v0.16b, v0.16b, #8
uzp1 v0.8b, v0.8b, v1.8b
str d0, [x8]
ret
Without this patch LLVM currently generates this code:
adrp x8, .LCPI0_0
ldr q0, [x8, :lo12:.LCPI0_0]
tbl v0.16b, { v0.16b }, v0.16b
mov v1.16b, v0.16b
mov v1.b[1], v0.b[2]
mov v1.b[2], v0.b[4]
mov v1.b[3], v0.b[6]
mov v1.b[4], v0.b[8]
mov v1.b[5], v0.b[10]
mov v1.b[6], v0.b[12]
mov v1.b[7], v0.b[14]
str d1, [x8]
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326443
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Sanjay Patel [Thu, 1 Mar 2018 15:30:44 +0000 (15:30 +0000)]
[InstCombine] move/add tests for fmul reassociation; NFC
This transform may be out-of-scope for instcombine,
but this is only documenting the current behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326442
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Sanjay Patel [Thu, 1 Mar 2018 15:13:42 +0000 (15:13 +0000)]
[InstCombine] auto-generate full checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326440
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Alexey Bataev [Thu, 1 Mar 2018 14:32:37 +0000 (14:32 +0000)]
Revert "[DEBUGINFO] Add flag for DWARF2 or less to use sections as references."
This reverts commit r326328 to remove checks for emission of certain
sections after discussion with Eric Christofer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326436
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Than McIntosh [Thu, 1 Mar 2018 13:31:57 +0000 (13:31 +0000)]
[CodeGen] fix argument attribute in lowering statepoint/patchpoint
Summary:
Use the correct loop index varaible, ArgI, to retrieve attributes.
Reviewers: thanm, sanjoy, rnk
Reviewed By: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326433
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Benjamin Kramer [Thu, 1 Mar 2018 11:31:44 +0000 (11:31 +0000)]
[SCCP] Fix unused variable warning in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326429
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Jonas Devlieghere [Thu, 1 Mar 2018 10:05:54 +0000 (10:05 +0000)]
[dsymutil] Move string pool into its own implementatino file. NFC.
The DwarfLinker implementation is already relatively large with over 4k
LOC. This commit moves the implementation of NonRelocatableStringpool
into a separate cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326425
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Max Kazantsev [Thu, 1 Mar 2018 06:56:48 +0000 (06:56 +0000)]
[SCEV] Smart range calculation for SCEVUnknown Phis
The range of SCEVUnknown Phi which merges values `X1, X2, ..., XN`
can be evaluated as `U(Range(X1), Range(X2), ..., Range(XN))`.
Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D43810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326418
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Craig Topper [Thu, 1 Mar 2018 06:25:13 +0000 (06:25 +0000)]
[X86] Stop passing two arguments by reference. NFC
I think these used to be out parameters, but they haven't been for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326417
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Lang Hames [Thu, 1 Mar 2018 02:52:17 +0000 (02:52 +0000)]
[Support] Fix comments for handleAllErrors: it calls llvm_unreachable if the
contract is violated, not report_fatal_error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326413
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Martin Pelikan [Thu, 1 Mar 2018 01:59:24 +0000 (01:59 +0000)]
[XRay] cache symbolized function names for a repeatedly queried function ID
Summary:
Processing 2 GB XRay traces with "llvm-xray convert -symbolize" needs to
go over each trace record and symbolize the function name refered to by
its ID. Currently this happens by asking the LLVM symbolizer code every
single time. A simple cache can save around 30 minutes of processing of
that trace.
llvm-xray's resident memory usage increased negligibly with this cache.
Reviewers: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326407
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Lang Hames [Thu, 1 Mar 2018 01:44:33 +0000 (01:44 +0000)]
[RuntimeDyld][MachO] Fix assertion in encodeAddend, add missing directive to
test case.
r326290 fixed the assertion for decodeAddend, but not encodeAddend. The
regression test failed to catch this because it was missing the
subsections_via_symbols flag, so the desired relocation was not applied.
This patch also fixes the formatting of the assertion from r326290.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326406
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Reid Kleckner [Thu, 1 Mar 2018 01:19:18 +0000 (01:19 +0000)]
[IPSCCP] do not break musttail invariant (PR36485)
Do not replace results of `musttail` calls with a constant if the
call itself can't be removed.
Do not zap returns of `musttail` callees, if the call site can't be
removed and replaced with a constant.
Do not zap returns of `musttail`-calling blocks, this breaks
invariant too.
Patch by Fedor Indutny
Differential Revision: https://reviews.llvm.org/D43695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326404
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Roman Tereshin [Thu, 1 Mar 2018 00:27:48 +0000 (00:27 +0000)]
[GlobalISel][AArch64] Adding -disable-gisel-legality-check CL option
Currently it's impossible to test InstructionSelect pass with MIR which
is considered illegal by the Legalizer in Assert builds. In early stages
of porting an existing backend from SelectionDAG ISel to GlobalISel,
however, we would have very basic CallLowering, Legalizer, and
RegBankSelect implementations, but rather functional Instruction Select
with quite a few patterns selectable due to the semi-automatic porting
process borrowing them from SelectionDAG ISel.
As we are trying to define legality as a property of being selectable by
the instruction selector, it would be nice to be able to easily check
what the selector can do in its current state w/o the legality check
provided by the Legalizer getting in the way.
It also seems beneficial to have a regression testing set up that would
not allow the selector to silently regress in its support of the MIR not
supported yet by the previous passes in the GlobalISel pipeline.
This commit adds -disable-gisel-legality-check command line option to
llc that disables those legality checks in RegBankSelect and
InstructionSelect passes.
It also adds quite a few MIR test cases for AArch64's Instruction
Selector. Every one of them would fail on the legality check at the
moment, but will select just fine if the check is disabled. Every test
MachineFunction is intended to exercise a specific selection rule and
that rule only, encoded in the MachineFunction's name by the rule's
number, ID, and index of its GIM_Try opcode in TableGen'erated
MatchTable (-optimize-match-table=false).
Reviewers: ab, dsanders, qcolombet, rovka
Reviewed By: bogner
Subscribers: kristof.beyls, volkan, aditya_nandakumar, aemerson,
rengolin, t.p.northover, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D42886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326396
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Paul Robinson [Thu, 1 Mar 2018 00:12:35 +0000 (00:12 +0000)]
[DWARF] Emit a split line table only if there are split type units.
A .debug_info.dwo section doesn't use the .debug_line.dwo section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326395
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Reid Kleckner [Thu, 1 Mar 2018 00:09:35 +0000 (00:09 +0000)]
[DAE] don't remove args of musttail target/caller
`musttail` requires identical signatures of caller and callee. Removing
arguments breaks `musttail` semantics.
PR36441
Patch by Fedor Indutny
Differential Revision: https://reviews.llvm.org/D43708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326394
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Craig Topper [Thu, 1 Mar 2018 00:08:38 +0000 (00:08 +0000)]
[X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific node when there are no FMA instructions.
This would cause a 'cannot select' error at isel when we should have emitted a lib call and an xor.
Fixes PR36553.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326393
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Justin Lebar [Wed, 28 Feb 2018 23:58:05 +0000 (23:58 +0000)]
[NVPTX] Lower loads from global constants using ld.global.nc (aka LDG).
Summary:
After D43914, loads from global variables in addrspace(1) happen with
ld.global. But since they're constants, even better would be to use
ld.global.nc, aka ldg.
Reviewers: tra
Subscribers: jholewinski, sanjoy, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D43915
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326390
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Justin Lebar [Wed, 28 Feb 2018 23:57:48 +0000 (23:57 +0000)]
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
Summary:
NVPTXGenericToNVVM was using target-specific intrinsics to do address
space casts. Using the addrspacecast instruction is (a lot) simpler.
But it also has the advantage of being understandable to other passes.
In particular, InferAddrSpaces is able to understand these address space
casts and remove them in most cases.
Reviewers: tra
Subscribers: jholewinski, sanjoy, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D43914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326389
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Roman Tereshin [Wed, 28 Feb 2018 23:51:49 +0000 (23:51 +0000)]
[MIRParser] Accept overloaded intrinsic names w/o type suffixes
Function::lookupIntrinsicID is somewhat forgiving as it comes to
overloaded intrinsics' names: it returns an ID as soon as the name
provided has a prefix that matches a registered intrinsic's name w/o
actually checking that the rest of the name encodes all the concrete arg
types, let alone that those types are compatible with the intrinsic's
definition.
That's probably fine and comes in handy in MIR serialization: we don't
care about IR types at MIR level and every intrinsic should be
selectable based on its ID and low-level types (LLTs) of its operands,
including the overloaded ones, so there is no point in serializing
mangled IR types as part of the intrinsic's name.
However, lookupIntrinsicID is somewhat inconsistent in its forgiveness:
if the name provided is actually an exact match, it will refuse to
return the ID if the intrinsic is overloaded. There is probably no
real reason for that and it renders MIRParser incapable to deserialize
MIR MIRPrinter serialized.
This commit fixes it.
Reviewers: rnk, aditya_nandakumar, qcolombet, thegameg, dsanders,
marcello.maggioni
Reviewed By: bogner
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D43267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326387
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Saleem Abdulrasool [Wed, 28 Feb 2018 23:00:50 +0000 (23:00 +0000)]
build: add the ability to create a symlink for dsymutil
Add a `LLVM_INSTALL_CCTOOLS_SYMLINKS` to mirror
`LLVM_INSTALL_BINUTILS_SYMLINKS`. For now, this allows us to create
symlinks for `dsymutil` to `llvm-dsymutil`. This option is off by
default, but the user can enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326381
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Simon Pilgrim [Wed, 28 Feb 2018 22:57:23 +0000 (22:57 +0000)]
[X86] Regenerate cmpxchg tests
Add 64-bit cmpxchg8b tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326380
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Sanjay Patel [Wed, 28 Feb 2018 22:30:04 +0000 (22:30 +0000)]
[InstCombine] simplify code for X * -1.0 --> -X; NFC
I've added random FMF to one of the tests to show those are propagated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326377
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Jonas Devlieghere [Wed, 28 Feb 2018 22:28:44 +0000 (22:28 +0000)]
[GlobalOpt] don't change CC of musttail calle(e|r)
When the function has musttail call - its cc is fixed to be equal to the
cc of the musttail callee. In such case (and in the case of the musttail
callee), GlobalOpt should not change the cc to fastcc as it will break
the invariant.
This fixes PR36546
Patch by: Fedor Indutny (indutny)
Differential revision: https://reviews.llvm.org/D43859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326376
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Craig Topper [Wed, 28 Feb 2018 22:23:55 +0000 (22:23 +0000)]
[X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 and extending/truncating.
This is equivalent to what isel was doing anyway but by canonicalizing earlier we can remove some patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326375
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Simon Pilgrim [Wed, 28 Feb 2018 21:42:19 +0000 (21:42 +0000)]
[X86][AVX512] Improve support for signed saturation truncation stores
Matches what we already manage for unsigned saturation truncation stores
Differential Revision: https://reviews.llvm.org/D43629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326372
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Krzysztof Parzyszek [Wed, 28 Feb 2018 20:29:36 +0000 (20:29 +0000)]
[Hexagon] Implement target feature +reserved-r19
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326364
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Craig Topper [Wed, 28 Feb 2018 20:14:34 +0000 (20:14 +0000)]
[InstCombine] Split the FP constant code out of lookThroughFPExtensions and use nullptr as a sentinel
Currently this code's control flow very much assumes that there are no meaningful checks after determining that it's a ConstantFP. So whenever it wants to stop it just does "return V". But V is also the variable name it uses when it wants to return a new value. So 'return V' appears multiple times with different meanings.
This patch just moves all the code into a helper function and returns nullptr when it wants to stop.
I've split this from D43774 while I try to figure out how to best handle the vector case there. But this change by itself at least seemed like a readability improvement.
Differential Revision: https://reviews.llvm.org/D43833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326361
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Lei Huang [Wed, 28 Feb 2018 20:05:24 +0000 (20:05 +0000)]
Losen time contraint to accommodate system loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326359
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Dimitry Andric [Wed, 28 Feb 2018 20:04:21 +0000 (20:04 +0000)]
Fix llvm-config --system-libs output on FreeBSD and NetBSD
Summary:
For various reasons, CMake's detection mechanism for `backtrace()`
returns an absolute path `/usr/lib/libexecinfo.so` on FreeBSD and
NetBSD.
Since `tools/llvm-config/CMakeLists.txt` only checks if system
libraries start with `-`, this causes `llvm-config --system-libs` to
produce the following incorrect output:
```
-lrt -l/usr/lib/libexecinfo.so -ltinfo -lpthread -lz -lm
```
Fix it by removing the path and the `lib` prefix, to make it look like a
regular short library name, suitable for appending to a `-l` link flag.
This also fixes the `Bindings/Go/go.test` test case, since that always
died with "unable to find library -l/usr/lib/libexecinfo.so".
Reviewers: chandlerc, emaste, joerg, krytarowski
Reviewed By: krytarowski
Subscribers: hans, bdrewery, mgorny, hintonda, llvm-commits
Differential Revision: https://reviews.llvm.org/D42702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326358
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Tim Renouf [Wed, 28 Feb 2018 19:10:32 +0000 (19:10 +0000)]
[AMDGPU] added writelane intrinsic
Summary:
For use by LLPC SPV_AMD_shader_ballot extension.
The v_writelane instruction was already implemented for use by SGPR
spilling, but I had to add an extra dummy operand tied to the
destination, to represent that all lanes except the selected one keep
the old value of the destination register.
.ll test changes were due to schedule changes caused by that new
operand.
Differential Revision: https://reviews.llvm.org/D42838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326353
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Vedant Kumar [Wed, 28 Feb 2018 19:08:52 +0000 (19:08 +0000)]
Fixed spelling mistake in comments of LLVM Analysis passes
Patch by Reshabh Sharma!
Differential Revision: https://reviews.llvm.org/D43861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326352
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Vedant Kumar [Wed, 28 Feb 2018 19:00:08 +0000 (19:00 +0000)]
[InstrProfiling] Emit the runtime hook when no counters are lowered
The API verification tool tapi has difficulty processing frameworks
which enable code coverage, but which have no code. The profile lowering
pass does not emit the runtime hook in this case because no counters are
lowered.
While the hook is not needed for program correctness (the profile
runtime doesn't have to be linked in), it's needed to allow tapi to
validate the exported symbol set of instrumented binaries.
It was not possible to add a workaround in tapi for empty binaries due
to an architectural issue: tapi generates its expected symbol set before
it inspects a binary. Changing that model has a higher cost than simply
forcing llvm to always emit the runtime hook.
rdar://
36076904
Differential Revision: https://reviews.llvm.org/D43794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326350
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Artem Belevich [Wed, 28 Feb 2018 18:51:22 +0000 (18:51 +0000)]
[NVPTX] Removed always-true predicates in NVPTX.
NVPTX stopped supporting GPUs older than sm_20 (Fermi) quite a while back.
Removal of support of pre-Fermi GPUs made a lot of predicates in the NVPTX
backend pointless as they can't ever be false any more.
It's time to retire them. NFC intended.
Differential Revision: https://reviews.llvm.org/D43843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326349
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Roman Tereshin [Wed, 28 Feb 2018 17:55:45 +0000 (17:55 +0000)]
[GlobalISel] Print/Parse FailedISel MachineFunction property
FailedISel MachineFunction property is part of the CodeGen pipeline
state as much as every other property, notably, Legalized,
RegBankSelected, and Selected. Let's make that part of the state also
serializable / de-serializable, so if GlobalISel aborts on some of the
functions of a large module, but not the others, it could be easily seen
and the state of the pipeline could be maintained through llc's
invocations with -stop-after / -start-after.
To make MIR printable and generally to not to break it too much too
soon, this patch also defers cleaning up the vreg -> LLT map until
ResetMachineFunctionPass.
To make MIR with FailedISel: true also machine verifiable, machine
verifier is changed so it treats a MIR-module as non-regbankselected and
non-selected if there is FailedISel property set.
Reviewers: qcolombet, ab
Reviewed By: dsanders
Subscribers: javed.absar, rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326343
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Chih-Hung Hsieh [Wed, 28 Feb 2018 17:48:55 +0000 (17:48 +0000)]
[TLS] use emulated TLS if the target supports only this mode
Emulated TLS is enabled by llc flag -emulated-tls,
which is passed by clang driver.
When llc is called explicitly or from other drivers like LTO,
missing -emulated-tls flag would generate wrong TLS code for targets
that supports only this mode.
Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether
emulated TLS code should be generated.
Unit tests are modified to run with and without the -emulated-tls flag.
Differential Revision: https://reviews.llvm.org/D42999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326341
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Nicholas Wilson [Wed, 28 Feb 2018 17:19:48 +0000 (17:19 +0000)]
[WebAssembly] Reorder symbol table to match MC order
This removes a TODO introduced in rL325860
Differential Revision: https://reviews.llvm.org/D43685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326334
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Pablo Barrio [Wed, 28 Feb 2018 17:13:07 +0000 (17:13 +0000)]
[ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations
Summary:
Expressions of the form x < 0 ? 0 : x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves
In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before.
Patch by Martin Svanfeldt
Reviewers: fhahn, pbarrio, rogfer01
Reviewed By: pbarrio, rogfer01
Subscribers: chrib, yroux, eugenis, efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326333
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Sanjay Patel [Wed, 28 Feb 2018 16:53:45 +0000 (16:53 +0000)]
[InstCombine] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326331
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Sanjay Patel [Wed, 28 Feb 2018 16:50:51 +0000 (16:50 +0000)]
[InstCombine] move invariant call out of loop; NFC
We really shouldn't need a 2-loop here at all, but that's another cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326330
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Sanjay Patel [Wed, 28 Feb 2018 16:36:24 +0000 (16:36 +0000)]
[InstCombine] move constant check into foldBinOpIntoSelectOrPhi; NFCI
Also, rename 'foldOpWithConstantIntoOperand' because that's annoyingly
vague. The constant check is redundant in some cases, but it allows
removing duplication for most of the calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326329
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Alexey Bataev [Wed, 28 Feb 2018 15:02:59 +0000 (15:02 +0000)]
[DEBUGINFO] Add flag for DWARF2 or less to use sections as references.
Summary:
Some targets does not support labels inside debug sections, but support
references in form `section +|- offset`. Patch adds initial support
for this. Also, this patch disables emission of all additional debug
sections that may have labels inside of it (like pub sections and
string tables).
Reviewers: probinson, echristo
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D43627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326328
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Nicholas Wilson [Wed, 28 Feb 2018 14:03:18 +0000 (14:03 +0000)]
[WebAssembly] Fix copy-paste error in debugging string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326326
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Simon Dardis [Wed, 28 Feb 2018 13:02:44 +0000 (13:02 +0000)]
[mips] Begin reworking instruction predicates for ISAs/encodings (1/N)
The MIPS backend has inconsistent usage of instruction predicates
for assembly and code generation. The issue arises from supporting three
encodings, two (MIPS and microMIPS) of which have a near 1:1 instruction
mapping across ISA revisions and a third encoding with a more restricted
set of instructions (MIPS16e).
To enforce consistent usage, each of the ISA_* adjectives has (or will
have) the relevant encoding attached to it along the relevant ISA revision
where the instruction is defined.
Each instruction, pattern or alias will then have the correct ISA adjective
attached to it, and the base instruction description classes will have any
predicates relating to ISA encoding or revision removed.
Pseudo instructions will also be guarded for the encoding or ABI that they are
supported in.
Finally, the hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods
of MipsSubtarget will be changed such that only one can be true at any one time.
The result of this is that code generation and assembly will produce the
correct encoding up front, while code generated from pseudo instructions
and other inserted sequences of instructions will be able to rely on the mapping
tables to produce the correct encoding. This should fix numerous bugs where
the result 'happens' to be correct but has edge cases where microMIPS and MIPS
have subtle differences (e.g. microMIPSR6 using 'j', 'jal' instructions.)
This patch starts the process by changing most of the ISA adjectives to make
use of the EncodingPredicate member of PredicateControl. Follow on patches
will annotate instructions with their correct ISA adjective and eliminate
the usage of "let Predicates = [..]", "let AdditionalPredicates = [..]" and
"isCodeGenOnly = 1" in the cases where it was used to control instruction
availability.
Contributions from Nitesh Jain.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326322
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Alexander Ivchenko [Wed, 28 Feb 2018 12:11:53 +0000 (12:11 +0000)]
[GlobalIsel][X86] Support G_INTTOPTR instruction.
Add legalization/selection for x86/x86_64 and
corresponding tests.
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D43622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326320
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Xin Tong [Wed, 28 Feb 2018 12:09:53 +0000 (12:09 +0000)]
Fix typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326319
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Xin Tong [Wed, 28 Feb 2018 12:08:00 +0000 (12:08 +0000)]
[MergeICmp] Fix a bug in MergeICmp that can lead to a block being processed more than once.
Summary:
Fix a bug in MergeICmp that can lead to a BCECmp block being processed more than once and eventually lead to a broken LLVM module.
The problem is that if the non-constant value is not produced by the last block, the producer will be processed once when the its parent block
is processed and second time when the last block is processed.
We end up having 2 same BCECmpBlock in the merge queue. And eventually lead to a broken LLVM module.
Reviewers: courbet, davide
Reviewed By: courbet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326318
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Klaus Kretzschmar [Wed, 28 Feb 2018 11:32:23 +0000 (11:32 +0000)]
[IR] - Make User construction exception safe
There are many instruction ctors that call the setName method of the Value base class, which can throw a bad_alloc exception in OOM situations.
In such situations special User delete operators are called which are not implemented yet.
Example:
Lets look at the construction of a CallInst instruction during IR generation:
static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, .. ){
...
return new (TotalOps, DescriptorBytes) CallInst(Ty, Func, Args, Bundles, NameStr, InsertBefore);
}
CallInst::CalInst(Value* Func, ...) {
...
Op<-1>() = Func;
....
setName(name); // throws
...
}
Op<-1>() returns a reference to a Use object of the CallInst instruction and the operator= inserts this use object into the UseList of Func.
The same object is removed from that UseList by calling the User::operator delete If the CallInst object is deleted.
Since setName can throw a bad_alloc exception (if LLVM_ENABLE_EXCEPTIONS is switched on), the unwind chain runs into assertions ("Constructor throws?") in
special User::operator deletes operators:
operator delete(void* Usr, unsigned)
operator delete(void* Usr, unsigned, bool)
This situation can be fixed by simlpy calling the User::operator delete(void*) in these unimplemented methods.
To ensure that this additional call succeeds all information that is necessary to calculate the storage pointer from the Usr address
must be restored in the special case that a sublass has changed this information, e.g. GlobalVariable can change the NumberOfOperands.
Reviewd by: rnk
Differential Revision: https://reviews.llvm.org/D42731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326316
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David Green [Wed, 28 Feb 2018 11:00:08 +0000 (11:00 +0000)]
[Dominators] Remove verifyDomTree and add some verifying for Post Dom Trees
Removes verifyDomTree, using assert(verify()) everywhere instead, and
changes verify a little to always run IsSameAsFreshTree first in order
to print good output when we find errors. Also adds verifyAnalysis for
PostDomTrees, which will allow checking of PostDomTrees it the same way
we check DomTrees and MachineDomTrees.
Differential Revision: https://reviews.llvm.org/D41298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326315
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Alexander Ivchenko [Wed, 28 Feb 2018 09:18:47 +0000 (09:18 +0000)]
[GlobalIsel][X86] Support G_PTRTOINT instruction.
Add legalization/selection for x86/x86_64 and
corresponding tests.
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D43617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326311
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Alex Bradbury [Wed, 28 Feb 2018 08:20:47 +0000 (08:20 +0000)]
[RISCV] Update two tests after r326208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326309
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Craig Topper [Wed, 28 Feb 2018 08:14:28 +0000 (08:14 +0000)]
[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to guarantee zeroes in the upper bits of return.
An extract_element where the result type is larger than the scalar element type is semantically an any_extend of from the scalar element type to the result type. If we expect zeroes in the upper bits of the i8/i32 we need to mae sure those zeroes are explicit in the DAG.
For these cases the best way to accomplish this is use an insert_subvector to pad zeroes to the upper bits of the v1i1 first. We extend to either v16i1(for i32) or v8i1(for i8). Then bitcast that to a scalar and finish with a zero_extend up to i32 if necessary. We can't extend past v16i1 because that's the largest mask size on KNL. But isel is smarter enough to know that a zext of a bitcast from v16i1 to i16 can use a KMOVW instruction. The insert_subvectors will be dropped during isel because we can determine that the producing instruction already zeroed the upper bits of the k-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326308
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Craig Topper [Wed, 28 Feb 2018 06:19:55 +0000 (06:19 +0000)]
[X86] Change the masked FPCLASS implementation to use AND instead of OR to combine the mask results.
While the description for the instruction does mention OR, its talking about how the individual classification test results are ORed together.
The incoming mask is used as a zeroing write mask. If the bit is 1 the classification is written to the output. The bit is 0 the output is 0. This equivalent to an AND.
Here is pseudocode from the intrinsics guide
FOR j := 0 to 1
i := j*64
IF k1[j]
k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
ELSE
k[j] := 0
FI
ENDFOR
k[MAX:2] := 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326306
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Andrew Zhogin [Wed, 28 Feb 2018 05:53:18 +0000 (05:53 +0000)]
[ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-bit, v8.1/v8.2/v8.3, thumb and pseudo instructions)
Added missed scheduling info for ARM Cortex A57 (AArch32) to have CompleteModel with this checkCompleteness fix: https://reviews.llvm.org/D43235.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D43808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326304
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Mohammad Shahid [Wed, 28 Feb 2018 04:19:34 +0000 (04:19 +0000)]
[SLP] Added new tests and updated existing for jumbled load, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326303
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Lang Hames [Wed, 28 Feb 2018 00:58:21 +0000 (00:58 +0000)]
[RuntimeDyld][MachO] Support ARM64_RELOC_BRANCH26 for BL instructions by
relaxing an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326290
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Justin Bogner [Wed, 28 Feb 2018 00:56:24 +0000 (00:56 +0000)]
update_mir_test_checks: Use the regexes from UpdateTestChecks.common
Some of the update_*_test_checks regexes have been moved into a
library, so we might as well use them in update_mir_test_checks.
Also includes minor bugfixes to the regexes that are there so we
don't regress update_mir_test_checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326288
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Justin Bogner [Wed, 28 Feb 2018 00:44:46 +0000 (00:44 +0000)]
update_mir_test_checks: Drop support for vreg block checks
Since vregs are printed in the instruction stream now, checking the
vreg block is always redundant. Remove the temporary feature that
allowed us to do that.
This reverts r316134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326284
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Sam Clegg [Tue, 27 Feb 2018 23:57:37 +0000 (23:57 +0000)]
[WebAssembly] Remove DataSize from linking metadata section
Neither the linker nor the runtime need this information
anymore. We were originally using this to model BSS size
but the plan is now to use the segment metadata to allow
for BSS segments.
Differential Revision: https://reviews.llvm.org/D41366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326267
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Krzysztof Parzyszek [Tue, 27 Feb 2018 22:44:41 +0000 (22:44 +0000)]
[Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326263
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Krzysztof Parzyszek [Tue, 27 Feb 2018 22:40:52 +0000 (22:40 +0000)]
[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX
Absence of memory operands is treated as "aliasing everything", so
dropping them is sufficient.
Recommit r326256 with a fixed testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326262
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Reid Kleckner [Tue, 27 Feb 2018 22:08:15 +0000 (22:08 +0000)]
[CodeView] Lower __restrict and other pointer qualifiers correctly
Qualifiers on a pointer or reference type may apply to either the
pointee or the pointer itself. Consider 'const char *' and 'char *
const'. In the first example, the pointee data may not be modified
without casts, and in the second example, the pointer may not be updated
to point to new data.
In the general case, qualifiers are applied to types with LF_MODIFIER
records, which support the usual const and volatile qualifiers as well
as the __unaligned extension qualifier.
However, LF_POINTER records, which are used for pointers, references,
and member pointers, have flags for qualifiers applying to the
*pointer*. In fact, this is the only way to represent the restrict
qualifier, which can only apply to pointers, and cannot qualify regular
data types.
This patch causes LLVM to correctly fold 'const' and 'volatile' pointer
qualifiers into the pointer record, as well as adding support for
'__restrict' qualifiers in the same place.
Based on a patch from Aaron Smith
Differential Revision: https://reviews.llvm.org/D43060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326260
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