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Boyuan Zhang [Fri, 19 Jun 2020 21:24:35 +0000 (17:24 -0400)]
drm/amdgpu: add navy_flounder vcn firmware support
Add navy_flounder to vcn family
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 10 Jun 2020 08:45:48 +0000 (16:45 +0800)]
drm/amdgpu/gfx10: add gc golden setting for navy_flounder
Add gc golden setting for navy_flounder
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Fri, 5 Jun 2020 02:59:58 +0000 (10:59 +0800)]
drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd support
Add callbacks to KGD for navy flounder.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 2 Jun 2020 08:15:56 +0000 (16:15 +0800)]
drm/amdkfd: Support navy_flounder KFD
Add KFD support for Navy Flounder.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 29 Apr 2020 10:18:23 +0000 (18:18 +0800)]
drm/amdgpu: use front door firmware loading for navy_flounder
Same as other navi asics.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 8 Jul 2020 21:07:26 +0000 (17:07 -0400)]
drm/amdgpu: add psp block for navy_flounder
Add psp and smu block for navy_flounder with
psp firmware load type.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 15 Apr 2020 10:38:05 +0000 (18:38 +0800)]
drm/amdgpu: add psp support for navy_flounder
Currently skip ASD FW loading and ih reroute per
sienna_cichlid.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 15 Apr 2020 03:20:19 +0000 (11:20 +0800)]
drm/amdgpu: add smu block for navy_flounder
Add SMU block for navy_flounder with direct
firmware load type.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Tue, 14 Jul 2020 16:34:45 +0000 (12:34 -0400)]
drm/amdgpu/powerplay: add smu support for navy_flounder
Now navy_flounder will reuse the smu11 driver_if header and ppt
functions for sienna_cichlid. Later navy_flounder can maintain
its own version if the compatibility is broken.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 13 Apr 2020 09:26:30 +0000 (17:26 +0800)]
drm/amdgpu: add gmc cg support for navy_flounder
The athub version used for navy_flounder is v2.1.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 13 Apr 2020 08:11:27 +0000 (16:11 +0800)]
drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP
with sienna_cichlid.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 20 Feb 2020 08:22:31 +0000 (16:22 +0800)]
drm/amdgpu: configure navy_flounder gfx according to gfx 10.3
The gfx version of navy_flounder is 10.3, identical to
sienna_cichlid, follow the way of sienna_cichlid.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 24 Feb 2020 06:28:34 +0000 (14:28 +0800)]
drm/amdgpu: add virtual display support for navy_flounder.
Virtual display support for bring up and virtualization.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Fri, 14 Feb 2020 08:19:13 +0000 (16:19 +0800)]
drm/amdgpu: add sdma ip block for navy_flounder
Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Thu, 13 Feb 2020 07:43:15 +0000 (15:43 +0800)]
drm/amdgpu: add gfx ip block for navy_flounder
since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 12 Feb 2020 14:32:01 +0000 (22:32 +0800)]
drm/amdgpu: add ih ip block for navy_flounder
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 12 Feb 2020 14:19:37 +0000 (22:19 +0800)]
drm/amdgpu: add gmc ip block for navy_flounder
navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 12 Feb 2020 13:47:47 +0000 (21:47 +0800)]
drm/amdgpu: add common ip block for navy_flounder
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 12 Feb 2020 13:12:56 +0000 (21:12 +0800)]
drm/amdgpu: add support on mmhub for navy_flounder
navy_flounder has the same mmhub IP version with sienna_cichlid,
follow its setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Tue, 11 Feb 2020 06:00:39 +0000 (14:00 +0800)]
drm/amdgpu: initialize IP offset for navy_flounder
since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 09:00:28 +0000 (17:00 +0800)]
drm/amdgpu/soc15: add support for navy_flounder
Add soc support.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:50:13 +0000 (15:50 +0800)]
drm/amdgpu/gfx10: add clockgating support for navy_flounder
Same as navi10.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:34:56 +0000 (15:34 +0800)]
drm/amdgpu/gmc10: add navy_flounder support
Same as navi10.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:21:09 +0000 (15:21 +0800)]
drm/amdgpu/gfx10: add support for navy_flounder firmware
Declare the gfx/compute firmwares.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:08:53 +0000 (15:08 +0800)]
drm/amdgpu: set asic family and ip blocks for navy_flounder
Add the asic family and IP blocks for navy flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:03:41 +0000 (15:03 +0800)]
drm/amdgpu: set fw load type for navy_flounder
Currently navy_flounder only supports backdoor loading type.
Will switch to psp load type when psp is ready.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 07:00:33 +0000 (15:00 +0800)]
drm/amdgpu: add navy_flounder gpu info firmware
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Mon, 10 Feb 2020 06:25:57 +0000 (14:25 +0800)]
drm/amdgpu: add navy_flounder asic type
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sat, 12 Oct 2019 11:55:48 +0000 (19:55 +0800)]
drm/amdgpu: expand to add multiple trap event irq id
Sienna_cichlid has four sdma instances, but other chips don't.
So we need expand to add multiple trap event irq id in sdma
v5.2.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Mon, 29 Jun 2020 02:06:49 +0000 (10:06 +0800)]
drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
V2: delete unneccessary white lines and refine implementation.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 15 Jul 2020 07:10:09 +0000 (15:10 +0800)]
drm/amdgpu: correct ta header v2 ucode init start address
resolve bug calculating fw start address within binary
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Mon, 29 Jun 2020 02:01:21 +0000 (10:01 +0800)]
drm/amd/sriov porting sriov cap to vcn3.0
1.In early_init and for sriov, hardcode
harvest_config=0, enc_num=1
2.sw_init/fini
alloc & free mm_table for sriov
doorbell setting for sriov
3.hw_init/fini
Under sriov, add start_sriov to config mmsch
Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings.
4.Implementation for vcn_v3_0_start_sriov
V2:Clean-up some uneccessary funciton declaration.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Mon, 29 Jun 2020 01:55:26 +0000 (09:55 +0800)]
drm/amd/sriov add mmsch_v3 interface
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch
to set the World Switch for MM appropriately. This patch add
the interface for mmsch_v3.0.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Wed, 24 Jun 2020 02:19:20 +0000 (10:19 +0800)]
drm/amdgpu: optimize rlcg write for gfx_v10
For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Tue, 23 Jun 2020 11:36:24 +0000 (19:36 +0800)]
drm/amd/sriov skip jped ip block and close pgcg flags
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 08:06:55 +0000 (16:06 +0800)]
drm/amd/powerplay: drop unused code around thermal range setting
Leftover of previous cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:59:03 +0000 (15:59 +0800)]
drm/amd/powerplay: maximum the code sharing on thermal irq setting
Put the common code in smu_v11_0.c instead of having one copy each.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:38:53 +0000 (15:38 +0800)]
drm/amd/powerplay: sort the call flow on temperature ranges retrieving
This can help to maintain clear code layer.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:13:02 +0000 (15:13 +0800)]
drm/amd/powerplay: cache the software_shutdown_temp
As it's needed in the succeeding thermal irq setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:56:34 +0000 (14:56 +0800)]
drm/amd/powerplay: correct Sienna Cichlid temperature limit settings
These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:48:03 +0000 (14:48 +0800)]
drm/amd/powerplay: correct Navi1X temperature limit settings
These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 3 Jul 2020 06:53:06 +0000 (14:53 +0800)]
drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount
The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:09:18 +0000 (14:09 +0800)]
drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting
This can also help to maintain clear code layer.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:42:06 +0000 (12:42 +0800)]
drm/amd/powerplay: drop unused APIs and parameters
Leftover of previous performance level setting cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:26:26 +0000 (12:26 +0800)]
drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.
V2: fix compile warnings below
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds]
freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds]
freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:12:22 +0000 (12:12 +0800)]
drm/amd/powerplay: drop unnecessary wrappers
By calling the target APIs directly.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Jul 2020 04:21:53 +0000 (12:21 +0800)]
drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:57:33 +0000 (11:57 +0800)]
drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
Use the common smu_v11_0_set_soft_freq_limited_range.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:32:58 +0000 (11:32 +0800)]
drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:26:53 +0000 (11:26 +0800)]
drm/amd/powerplay: drop unnecessary Navi1x specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:00:20 +0000 (11:00 +0800)]
drm/amd/powerplay: drop unnecessary Arcturus specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 02:51:12 +0000 (10:51 +0800)]
drm/amd/powerplay: update the common API for performance level setting
So that it can be more widely shared around SMU v11 ASICs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 08:15:26 +0000 (16:15 +0800)]
drm/amd/powerplay: update UMD pstate clock settings
Preparing for coming code sharing around performance level
setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 06:28:20 +0000 (14:28 +0800)]
drm/amd/powerplay: add new UMD pstate data structure
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 09:02:37 +0000 (17:02 +0800)]
drm/amd/powerplay: update Sienna Cichlid default dpm table setup
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 08:52:32 +0000 (16:52 +0800)]
drm/amd/powerplay: update Navi10 default dpm table setup
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Jul 2020 02:49:42 +0000 (10:49 +0800)]
drm/amd/powerplay: update Arcturus default dpm table setting
Preparing for coming code sharing around performance level
setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Jul 2020 02:46:48 +0000 (10:46 +0800)]
drm/amd/powerplay: implement a common set dpm table API for smu V11
Maximum the code sharing around smu V11.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 06:32:58 +0000 (14:32 +0800)]
drm/amd/powerplay: add more members for dpm table
These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenhui Sheng [Tue, 14 Jul 2020 08:29:18 +0000 (16:29 +0800)]
drm/amdgpu: add module parameter choose reset mode
Default value is auto, doesn't change
original reset method logic.
v2: change to use parameter reset_method
v3: add warn msg if specified mode isn't supported
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenhui Sheng [Mon, 13 Jul 2020 07:15:11 +0000 (15:15 +0800)]
drm/amdgpu: enable mode1 reset
For sienna cichlid, add mode1 reset path for sGPU.
v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenhui Sheng [Mon, 13 Jul 2020 07:14:30 +0000 (15:14 +0800)]
drm/amdgpu: RAS emergency restart logic refine
If we are in RAS triggered situation and
BACO isn't support, emergency restart is needed,
and this code is only needed for some specific
cases(vega20 with given smu fw version).
After we add smu mode1 reset for sienna cichlid, we
need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset,
so in amdgpu_device_gpu_recover, we need differentiate
which mode1 reset we are using, then decide if it's
a full reset and then decide if emergency restart is needed,
the logic will become much more complex.
After discussion with Hawking, move emergency restart logic
to an independent function.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenhui Sheng [Fri, 10 Jul 2020 09:39:24 +0000 (17:39 +0800)]
drm/amd/powerplay: add SMU mode1 reset
From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
v2: add mode1 reset dpm interface
v3: change maro name
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rajneesh Bhardwaj [Mon, 13 Jul 2020 15:15:30 +0000 (11:15 -0400)]
drm/amdkfd: fix kernel-doc and cleanup
- fix some styling issues
- fixes for kernel-doc type
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Tue, 14 Jul 2020 10:57:00 +0000 (13:57 +0300)]
drm/amd/display: remove an unnecessary NULL check
The "stream" pointer can't be NULL and it's dereferenced on the line
before so the check doesn't make sense.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 14 Jul 2020 07:47:31 +0000 (15:47 +0800)]
drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()
"u64 *wptr" points to the the wptr value in write back buffer and
"*wptr = (*wptr) >> 2;" results in the value being overwritten each time
when ->get_wptr() is called.
umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and
decode ring content and it is affected by this issue.
fix and simplify the logic similar as sdma_v4_0_ring_get_wptr().
v2: fix for sdma5.2 as well
Suggested-by: Le Ma <le.ma@amd.com>
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 13 Jul 2020 05:55:42 +0000 (13:55 +0800)]
drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files
to easily add new debugfs file w/o changing the hardcoded list count.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
chen gong [Mon, 13 Jul 2020 08:11:24 +0000 (16:11 +0800)]
drm/amdgpu/powerplay: Modify SMC message name for setting power profile mode
I consulted Cai Land(Chuntian.Cai@amd.com), he told me corresponding smc
message name to fSMC_MSG_SetWorkloadMask() is
"PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir.
Strange though it may seem, but it's a fact.
Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Mon, 13 Jul 2020 14:41:23 +0000 (10:41 -0400)]
drm/amd/display: Allow for vblank enabled with no active planes
[Why]
CRC capture doesn't work when the active plane count is 0 since we
currently tie both vblank and pageflip interrupts to active_plane_count
greater than 0.
[How]
The frontend is what generates the vblank interrupts while the backend
is what generates pageflip interrupts. Both have a requirement for
the CRTC to be active, so control the overall interrupt state based
on that instead.
Pageflip interrupts need to be enabled based on active plane count, but
we actually rely on power gating to take care of disabling the interrupt
for us on pipes that can be power gated.
For pipes that can't be power gated it's still fine to leave it enabled
since the interrupt only triggers after the address has been written
to that particular pipe - which we won't be doing without an active
plane.
The issue we had before with this setup was that we couldn't force
the state back on. We were essentially manipulating the refcount
to enable or disable as needed in a two pass approach.
However, there is a function that solves this problem more elegantly:
amdgpu_irq_update() will unconditionally call the set based on what it
thinks the current enablement state is.
This leaves two future TODO items for our IRQ handling:
- Disabling IRQs in commit tail instead of atomic commit
- Mapping the pageflip interrupt to VUPDATE or something that's tied to
the frontend instead of the backend since the mapping to CRTC is not
correct
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 9 Jul 2020 20:21:37 +0000 (16:21 -0400)]
drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2
[Why]
When enabling the debugfs for CRC capture we hit assertions caused by
register address and field masks and shifts missing.
[How]
We want these registers programmed, so add in the SRI/SF entries for
this register.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Mon, 6 Jul 2020 19:43:39 +0000 (15:43 -0400)]
drm/amd/display: handle failed allocation during stream construction
[Why]
Failing to allocate a transfer function during stream construction leads
to a null pointer dereference
[How]
Handle the failed allocation by failing the stream construction
Cc: stable@vger.kernel.org
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Thu, 26 Mar 2020 18:40:02 +0000 (14:40 -0400)]
drm/amd/display: Reuse parsing code of debugfs write buffer
[why]
Move code for parsing debugfs input into an array of int parameters by
specifying the max number of expected parameters
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 6 Jul 2020 14:08:54 +0000 (10:08 -0400)]
drm/amd/display: 3.2.94
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Mon, 6 Jul 2020 15:53:48 +0000 (11:53 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.24
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 30 Jun 2020 14:20:06 +0000 (10:20 -0400)]
drm/amd/display: fix dcn3 p_state_change_support validation (v2)
Our validation is a known mess with actual validation mixed with
topology configuration. This change makes sure topolgical validation is
completed before any topology changes are made so we do not run into
issues where we merge and split a pipe over the course of a single call.
v2: Squash in compilation fix
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hersen wu [Mon, 6 Jul 2020 13:18:25 +0000 (09:18 -0400)]
drm/amd/display: p-state warning occurs while changing resolution from 120hz to 60hz
[Why]
new calculated dispclk, dppclk are stored in
context->bw_ctx.bw.dcn.clk.dispclk_khz, dppclk_khz. Current dispclk,
dppclk are from dc->clk_mgr->clks.dispclk_khz. dcn_validate_bandwidth
compute new dispclk, dppclk. dispclk will put in use after
optimize_bandwidth when ramp_up_dispclk_with_dpp is called. There are
two places for dppclk be put in use. One location is the same as the
location as dispclk. Another is within update_dchubp_dpp which happens
between pre_bandwidth and optimize_bandwidth. dppclk updated within
update_dchubp_dpp will cause new clock values of dispclk and dppclk not
be in use at the same time. when clocks are decreased, this may cause
dppclk is lower than current configuration and let pipe stuck. for
example, eDP + external dp, change resolution of DP from 1920x1080x144hz
to 1280x960x60hz.
before change: dispclk = 337889 dppclk = 337889
change mode, dcn_validate_bandwidth calculate
dispclk = 143122 dppclk = 143122
update_dchubp_dpp be executed before dispclk be updated,
dispclk = 337889, but dppclk use new value dispclk /2 =
168944. this will cause pipe pstate warning issue.
[How]
between pre_bandwidth and optimize_bandwidth, while dispclk is going to
be decreased, keep dppclk = dispclk
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hersen wu [Mon, 22 Jun 2020 17:29:16 +0000 (13:29 -0400)]
drm/amd/display: OLED panel backlight adjust not work with external display connected
[Why]
amdgpu_dm->backlight_caps is for single eDP only. the caps are upddated
for very connector. Real eDP caps will be overwritten by other external
display. For OLED panel, caps->aux_support is set to 1 for OLED pnael.
after external connected, caps+.aux_support is set to 0. This causes
OLED backlight adjustment not work.
[How]
within update_conector_ext_caps, backlight caps will be updated only for
eDP connector.
Cc: stable@vger.kernel.org
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chiawen Huang [Wed, 1 Jul 2020 22:47:05 +0000 (06:47 +0800)]
drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable
[Why]
when ppt disabled, the watermark doesn't get fine tune causing
underflow.
[How]
It is a temporary solution to reduce sr_xxx_time by 3 us when ppt
disable.
Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Thu, 25 Jun 2020 17:49:31 +0000 (13:49 -0400)]
drm/amd/display: Power down hardware if set mode is not called before timeout
[WHY]
In headless systems, if set mode is not called, hardware will not be
powered down on boot, causing HW/SW discrepancies. Powering down
hardware on boot will ensure SW state is accurate.
[HOW]
Set a timer callback on boot for 10 seconds. If set mode is not called
within that time, power down hardware. Otherwise, do not power down.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 15 Jun 2020 13:40:06 +0000 (09:40 -0400)]
drm/amd/display: update dml var
Update *DynamicMetadata variables for providing more flexibility.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
chen gong [Fri, 10 Jul 2020 06:21:10 +0000 (14:21 +0800)]
drm/amdgpu/powerplay: Target power profile mode should be the second parameter of renoir_set_power_profile_mode
A small mistake
Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Jul 2020 21:50:00 +0000 (17:50 -0400)]
drm/amdgpu/display: create fake mst encoders ahead of time (v4)
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
v3: use the actual number of crtcs on the asic rather than the max
to conserve encoders.
v4: v3 plus missing hunk I forgot to git add.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1108
Fixes:
c6385e503aeaf9 ("drm/amdgpu: drop legacy drm load and unload callbacks")
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 10 Jul 2020 08:37:58 +0000 (09:37 +0100)]
drm/amdgpu: fix spelling mistake "Falied" -> "Failed"
There is a spelling mistake in a DRM_ERROR error message. Fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 10 Jul 2020 04:34:52 +0000 (12:34 +0800)]
drm/amdgpu: fix preemption unit test
Remove signaled jobs from job list and ensure the
job was indeed preempted.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 10 Jul 2020 04:18:22 +0000 (12:18 +0800)]
drm/amdgpu/gfx10: fix race condition for kiq
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Thu, 9 Jul 2020 13:41:40 +0000 (15:41 +0200)]
drm/amdgpu: minor cleanup of phase1 suspend code
Cleanup of phase1 suspend code to reduce unnecessary indentation.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 09:26:39 +0000 (17:26 +0800)]
drm/amd/powerplay: put dpm frequency setting common code in smu_v11_0.c
As designed the common code shared among all smu v11 ASCIs go to
smu_v11_0.c. This helps to maintain clear code layers.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 08:16:56 +0000 (16:16 +0800)]
drm/amd/powerplay: revise calling chain on retrieving frequency range
This helps to maintain clear code layers and drop unnecessary
parameter.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 06:57:06 +0000 (14:57 +0800)]
drm/amd/powerplay: revise calling chain on setting soft limit
This helps to maintain clear code layers and drop unnecessary
parameter.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 06:39:21 +0000 (14:39 +0800)]
drm/amd/powerplay: put setting hard limit common code in smu_v11_0.c
As designed the common code shared among all smu v11 ASCIs go to
smu_v11_0.c. This helps to maintain clear code layers.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 05:32:18 +0000 (13:32 +0800)]
drm/amd/powerplay: drop unused code and wrapper around clock retrieving
Clean code by dropping unnecessary ones.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 05:15:29 +0000 (13:15 +0800)]
drm/amd/powerplay: unshare the code for retrieving current clock frequency
By moving them into asic specific file. Since they are really ASIC
specific.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 04:54:24 +0000 (12:54 +0800)]
drm/amd/powerplay: bypass wrapper on retrieving current clock frequency
By calling the target API(asic specific) directly.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 9 Jun 2020 04:39:26 +0000 (12:39 +0800)]
drm/amd/powerplay: drop unnecessary wrappers around clock retrieving
By calling the target APIs directly.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 9 Jul 2020 06:36:25 +0000 (14:36 +0800)]
drm/amd/powerplay: update driver if file for sienna_cichlid
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 3 Jul 2020 08:50:33 +0000 (16:50 +0800)]
drm/amd/powerplay: correct the .get_workload_type() pointer
This seemed a typo.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Changfeng [Thu, 9 Jul 2020 06:52:11 +0000 (14:52 +0800)]
Revert "drm/amd/display: add mechanism to skip DCN init"
To avoid s3 faild at the first cycle on renoir platform, it needs to
revert this patch:
drm/amd/display: add mechanism to skip DCN init
Signed-off-by: changfeng <Changfeng.Zhu@amd.com>
Ackedy-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 8 Jul 2020 20:30:26 +0000 (16:30 -0400)]
drm/amd/display: Fix CSC remap matrix not being applied on dcn30
[Why]
DCN3 has two gamut remap matrices. When using CSC adjustment the CM
remap is set to bypass and MPCC remap is used. However to bypass CM
some state in the context is modified and not restored correctly
resulting in subsequent calls to disable MPCC remap as well.
[How]
Fix logic for save/restore of remap enable flag when programming MPCC
remap matrix.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 8 Jul 2020 17:29:58 +0000 (13:29 -0400)]
drm/amd/display: Use VUPDATE_NO_LOCK instead of VUPDATE for dcn30
[Why]
Soft hangs occur when FreeSync is engaged since we utilize VUPDATE
(which doesn't fire when holding the pipe lock) to send back vblank
events when FreeSync is active.
[How]
The alternative (working) interrupt source for this mechanism is
VUPDATE_NO_LOCK. We already use this all other DCN revisions so align
dcn30 with those as well.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 8 Jul 2020 03:04:16 +0000 (11:04 +0800)]
drm/amdgpu: enable gpu recovery for sienna cichlid
Enable gpu recovery for sienna cichlid by default to trigger
gpu recovery once needed.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>