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Alina Sbirlea [Mon, 10 Sep 2018 23:47:21 +0000 (23:47 +0000)]
[InstCombine] Partially revert rL341674 due to PR38897.
Summary:
Revert min/max changes in rL341674 dues to high compile times causing timeouts (PR38897).
Checking in to unblock failing builds. Patch available for post-commit review and re-revert once resolved.
Working on a smaller reproducer for PR38897.
Reviewers: craig.topper, spatel
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D51897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341883
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Jessica Paquette [Mon, 10 Sep 2018 23:30:53 +0000 (23:30 +0000)]
Explicitly state triple in machine-size-remarks.ll
A bot was unhappy with the x86 triple there before. Set it explicitly to
x86_64-apple-darwin just to get something consistent.
Example failure:
http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/16846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341882
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Philip Reames [Mon, 10 Sep 2018 23:14:30 +0000 (23:14 +0000)]
[AST] Add test coverage of memsets
Immediately after posting https://reviews.llvm.org/D51895, I noticed a small bug. These tests would have caught that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341880
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Jessica Paquette [Mon, 10 Sep 2018 22:24:10 +0000 (22:24 +0000)]
Add size remarks to MachineFunctionPass
This adds per-function size remarks to codegen, similar to what we have in the
IR layer as of r341588. This only impacts MachineFunctionPasses.
This does the same thing, but for `MachineInstr`s instead of just
`Instructions`. After this, when a `MachineFunctionPass` modifies the number of
`MachineInstr`s in the function it ran on, you'll get a remark.
To enable this, use the size-info analysis remark as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341876
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Lang Hames [Mon, 10 Sep 2018 22:09:11 +0000 (22:09 +0000)]
[ORC] Render unresolved symbol addresses as "<not resolved>" in JITDylib::dump.
This is easier to spot among the real addresses than "0x0000000000000000".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341873
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Lang Hames [Mon, 10 Sep 2018 22:08:57 +0000 (22:08 +0000)]
[ORC] Simplify LLJIT::Create by removing the ExecutionSession parameter.
The Create method can just construct the ExecutionSession, rather than having the
client pass it in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341872
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Craig Topper [Mon, 10 Sep 2018 21:49:01 +0000 (21:49 +0000)]
[X89] Explicitly enable aes in aes-schedule.ll to fix failures after r341861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341868
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JF Bastien [Mon, 10 Sep 2018 21:43:17 +0000 (21:43 +0000)]
Fix bit_cast properly
Mismatched braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341867
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JF Bastien [Mon, 10 Sep 2018 21:41:14 +0000 (21:41 +0000)]
Fix bit_cast __is_trivially_copyable
It's a function-like builtin, not a template.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341866
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JF Bastien [Mon, 10 Sep 2018 21:33:45 +0000 (21:33 +0000)]
[ADT] bit_cast: check for is_trivially_copyable more portably
Summary:
It turns out that isPodLike isn't a good workaround for is_trivially_copyable for bit_cast's purpose. In D51872 Louis points out that tuple and pair really aren't a good fit, and for bit_cast I want to capture array. This patch instead checks is_trivially_copyable directly in bit_cast for all but GCC 4.x. In GCC 4.x developers only check for sizeof match, which means any mistake they make will succeed locally and fail on the bots. Realistically that's few developers and they'll be left behind once we upgrade past C++11.
This will allow using bit_cast with std::array.
Subscribers: dexonsmith, llvm-commits, ldionne, rsmith
Differential Revision: https://reviews.llvm.org/D51888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341865
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Zachary Turner [Mon, 10 Sep 2018 21:31:21 +0000 (21:31 +0000)]
Re-run clang-format on one file.
clang-format was getting confused due to the presence of a macro
invocation that was not terminated by a semicolon. Fixed this by
terminating the macro lines with semicolons and re-ran clang-format
on the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341864
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Zachary Turner [Mon, 10 Sep 2018 21:30:59 +0000 (21:30 +0000)]
[PDB] Change uint32_t to SymIndex wherever it makes sense.
Although it's just a typedef, it helps for readability. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341863
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Erich Keane [Mon, 10 Sep 2018 21:12:19 +0000 (21:12 +0000)]
Move FeatureAES from SLM, WSM and SNB to GLM and SKL
Complements https://reviews.llvm.org/D51510 and matches
https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01940.html
GoldmontProc already has FeatureAES.
Patch By: thiagomacieira
Differential Revision: https://reviews.llvm.org/D51565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341861
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Craig Topper [Mon, 10 Sep 2018 20:31:27 +0000 (20:31 +0000)]
[X86] Mark the ISD::SETLT/SETLE condition codes as illegal for v32i16/v64i8 to match the other vector types.
I'm having a hard time finding a test case for this, but we should be consistent here. The fact that we canonicalize all zeros and all ones constants to vXi32 and all other constants to loads makes this hard to hit the easy DAG combine infinite loop we get for some of the other types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341859
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Stella Stamenova [Mon, 10 Sep 2018 20:24:05 +0000 (20:24 +0000)]
[lit] Disable shtest-timeout on Windows
Summary: This is the only test that is still failing on Windows - or rather, it is expected to fail on the bots, but passes on the new bot that we're preparing causing a failure, so I'm going to disable it. Since the test has rarely, if ever, passed on the bots, this should have the same effect and it will unblock the creation of the new bot.
Reviewers: asmith, delcypher, zturner
Subscribers: stella.stamenova, llvm-commits
Differential Revision: https://reviews.llvm.org/D51871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341856
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Alina Sbirlea [Mon, 10 Sep 2018 20:13:01 +0000 (20:13 +0000)]
API to update MemorySSA for cloned blocks and added CFG edges.
Summary:
End goal is to update MemorySSA in all loop passes. LoopUnswitch clones all blocks in a loop. SimpleLoopUnswitch clones some blocks. LoopRotate clones some instructions.
Some of these loop passes also make CFG changes.
This is an API based on what I found needed in LoopUnswitch, SimpleLoopUnswitch, LoopRotate, LoopInstSimplify, LoopSimplifyCFG.
Adding dependent patches using this API for context.
Reviewers: george.burgess.iv, dberlin
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D45299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341855
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JF Bastien [Mon, 10 Sep 2018 19:56:42 +0000 (19:56 +0000)]
NFC: bit.h don't warn on strict aliasing for GCC <= 7.1
Summary: Addressed https://bugs.llvm.org/show_bug.cgi?id=38885
Subscribers: dexonsmith, llvm-commits, rsmith, steven_wu, RKSimon, Abhilash, srhines
Differential Revision: https://reviews.llvm.org/D51869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341853
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Petr Hosek [Mon, 10 Sep 2018 19:34:44 +0000 (19:34 +0000)]
[ADT] Support converting to lowercase string in toHex
This is useful in certain use-cases such as D51833.
Differential Revision: https://reviews.llvm.org/D51835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341852
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Krzysztof Parzyszek [Mon, 10 Sep 2018 18:49:16 +0000 (18:49 +0000)]
[Hexagon] Split large offsets into properly aligned addends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341851
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Sanjay Patel [Mon, 10 Sep 2018 18:37:59 +0000 (18:37 +0000)]
[InstCombine] use SelectInst operand names to make code clearer; NFC
Cleanup step for D51433.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341850
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Sanjay Patel [Mon, 10 Sep 2018 17:40:15 +0000 (17:40 +0000)]
[x86] test codegen for unsigned saturated add; NFC
All of the ISA holes are going to make this difficult,
but we can't canonicalize the IR and try to solve PR14613
until we have backend support to get this right.
https://bugs.llvm.org/show_bug.cgi?id=14613
https://rise4fun.com/Alive/Guv
https://rise4fun.com/Alive/AADG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341845
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Tatyana Krasnukha [Mon, 10 Sep 2018 17:09:09 +0000 (17:09 +0000)]
[ARC] Fix macro usage (DEBUG -> LLVM_DEBUG)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341844
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Alexander Timofeev [Mon, 10 Sep 2018 16:42:49 +0000 (16:42 +0000)]
[AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32.
Differential revision: https://reviews.llvm.org/D51586
Reviewer: rampitec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341843
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Philip Reames [Mon, 10 Sep 2018 16:00:27 +0000 (16:00 +0000)]
[AST] Visit memtransfer arguments in order
The only point to this change is the test diffs. When I remove this code entirely (in favor of the recently added generic handling), I don't want there to be any confusion due to spurious test diffs.
As an aside, the fact out tests are AST construction order dependent is not great. I thought about fixing that, but the reasonable schemes I might want (e.g. sort by name) need the test diffs anyways.
Philip
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341841
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Petar Jovanovic [Mon, 10 Sep 2018 15:56:52 +0000 (15:56 +0000)]
[MIPS GlobalISel] Select icmp
Select 32bit integer compare instructions for MIPS32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D51489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341840
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Sebastian Pop [Mon, 10 Sep 2018 15:42:17 +0000 (15:42 +0000)]
HotColdSplitting: fix test failing because of last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341839
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Sebastian Pop [Mon, 10 Sep 2018 15:08:02 +0000 (15:08 +0000)]
HotColdSplitting: check that target supports cold calling convention
Before tagging a function with coldcc make sure the target supports cold calling
convention. Without this patch HotColdSplitting pass fails on aarch64 with:
fatal error: error in backend: Unsupported calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341838
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Sebastian Pop [Mon, 10 Sep 2018 15:07:59 +0000 (15:07 +0000)]
add flag instead of using a constant [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341837
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Sebastian Pop [Mon, 10 Sep 2018 15:07:56 +0000 (15:07 +0000)]
make flag name more specific to gvn [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341836
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Gil Rapaport [Mon, 10 Sep 2018 14:56:24 +0000 (14:56 +0000)]
[LSR] Add tests for small constants; NFC
LSR reassociates small constants that fit into add immediate operands as
unfolded offset. Since unfolded offset is not combined with loop-invariant
registers, LSR does not consider solutions that bump invariant registers by
these constants outside the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341835
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Tim Northover [Mon, 10 Sep 2018 14:26:44 +0000 (14:26 +0000)]
InstCombine: move hasOneUse check to the top of foldICmpAddConstant
There were two combines not covered by the check before now, neither of which
actually differed from normal in the benefit analysis.
The most recent seems to be because it was just added at the top of the
function (naturally). The older is from way back in 2008 (r46687) when we just
didn't put those checks in so routinely, and has been diligently maintained
since.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341831
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Benjamin Kramer [Mon, 10 Sep 2018 13:55:38 +0000 (13:55 +0000)]
[Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation is already
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341826
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Alexandre Ganea [Mon, 10 Sep 2018 13:51:21 +0000 (13:51 +0000)]
[LLD][COFF] Cleanup error messages / add more coverage tests
- Log the reason for a PDB or precompiled-OBJ load failure
- Properly handle out-of-date PDB or precompiled-OBJ signature by displaying a corresponding error
- Slightly change behavior on PDB failure: any subsequent load attempt from another OBJ would result in the same error message being logged
- Slightly change behavior on PDB failure: retry with filename only if previous error was ENOENT ("no such file or directory")
- Tests: a. for native PDB errors; b. cover all the cases above
Differential Revision: https://reviews.llvm.org/D51559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341825
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Benjamin Kramer [Mon, 10 Sep 2018 12:53:46 +0000 (12:53 +0000)]
[Target] Untangle disassemblers
Disassemblers cannot depend on main target headers. The same is true for
MCTargetDesc, but there's a lot more cleanup needed for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341822
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Benjamin Kramer [Mon, 10 Sep 2018 12:32:06 +0000 (12:32 +0000)]
Don't create a temporary vector of loop blocks just to iterate over them.
Loop's getBlocks returns an ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341821
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John Brawn [Mon, 10 Sep 2018 12:23:05 +0000 (12:23 +0000)]
[GVN] Invalidate cached info for values replaced by equality propagation
When GVN propagates an equality by replacing one value with another it also
needs to invalidate the cached information for the value being replaced.
Differential Revision: https://reviews.llvm.org/D51218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341820
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Matt Arsenault [Mon, 10 Sep 2018 12:16:11 +0000 (12:16 +0000)]
AMDGPU: Remove function pointer type hack
Now the pointer size should always be correct and
we don't need to improperly inspect the pointee type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341806
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Matt Arsenault [Mon, 10 Sep 2018 11:59:27 +0000 (11:59 +0000)]
AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit
This will require something to cast. Before this would eliminate
the cast, which would result in copies of $noreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341803
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Matt Arsenault [Mon, 10 Sep 2018 11:49:23 +0000 (11:49 +0000)]
DAG: Handle odd vector sizes in calling conv splitting
This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.
Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.
This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341801
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Simon Pilgrim [Mon, 10 Sep 2018 10:45:04 +0000 (10:45 +0000)]
[llvm-exegesis] Ignore double spaced separators in asm strings
Some asm has double spaces between operands, the deserializer was keeping these empty split pieces, causing assertions later on:
'ADC16mi RDI i_0x1x i_0x0x i_0x1x'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341799
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Carl Ritson [Mon, 10 Sep 2018 10:14:48 +0000 (10:14 +0000)]
[AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting
Summary:
This fixes a bug where a large number of implicit def instructions can fill the GCNHazardRecognizer lookahead buffer causing required NOPs to not be inserted.
Reviewers: nhaehnle, arsenm
Reviewed By: arsenm
Subscribers: sheredom, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D51726
Change-Id: Ie75338f94de704ee5816b05afd0c922c6748a95b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341798
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Hans Wennborg [Mon, 10 Sep 2018 08:50:31 +0000 (08:50 +0000)]
ReleaseNotes: update links to use https
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341785
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Max Kazantsev [Mon, 10 Sep 2018 06:50:16 +0000 (06:50 +0000)]
[IndVars] Set Changed if rewriteFirstIterationLoopExitValues changes IR. PR38863
Currently, `rewriteFirstIterationLoopExitValues` does not set Changed flag even if it makes
changes in the IR. There is no clear evidence that it can cause a crash, but it
looks highly suspicious and likely invalid.
Differential Revision: https://reviews.llvm.org/D51779
Reviewed By: skatkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341779
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Max Kazantsev [Mon, 10 Sep 2018 06:32:00 +0000 (06:32 +0000)]
[IndVars] Set Changed if sinkUnusedInvariants changes IR. PR38863
Currently, `sinkUnusedInvariants` does not set Changed flag even if it makes
changes in the IR. There is no clear evidence that it can cause a crash, but it
looks highly suspicious and likely invalid.
Differential Revision: https://reviews.llvm.org/D51777
Reviewed By: skatkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341777
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Vikram TV [Mon, 10 Sep 2018 06:16:44 +0000 (06:16 +0000)]
Move a transformation routine from LoopUtils to LoopVectorize.
Summary:
Move InductionDescriptor::transform() routine from LoopUtils to its only uses in LoopVectorize.cpp.
Specifically, the function is renamed as InnerLoopVectorizer::emitTransformedIndex().
This is a child to D51153.
Reviewers: dmgreen, llvm-commits
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D51837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341776
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David Carlier [Mon, 10 Sep 2018 05:29:49 +0000 (05:29 +0000)]
[XRay] Fix buildbot failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341774
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Vikram TV [Mon, 10 Sep 2018 05:05:08 +0000 (05:05 +0000)]
Move createMinMaxOp() out of RecurrenceDescriptor.
Reviewers: dmgreen, llvm-commits
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D51838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341773
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David Carlier [Mon, 10 Sep 2018 05:00:43 +0000 (05:00 +0000)]
[Xray] tooling allow MachO format support
Getting writable xray __DATA sections from MachO as well.
Reviewers: dberris
Reviewed By: dberris
Differential Revision: https://reviews.llvm.org/D51758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341772
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Dean Michael Berris [Mon, 10 Sep 2018 02:57:05 +0000 (02:57 +0000)]
[XRay] Remove unused reference
The reference was only used in the assertion.
Follow-up on D51723.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341771
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Matt Arsenault [Mon, 10 Sep 2018 02:54:25 +0000 (02:54 +0000)]
AMDGPU: Fix tests using old number for constant address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341770
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Dean Michael Berris [Mon, 10 Sep 2018 02:35:25 +0000 (02:35 +0000)]
[XRay] Add a BlockVerifier visitor for FDR Records
Summary:
This patch implements a `BlockVerifier` type which enforces the
invariants of the log structure of FDR mode logs on a per-block basis.
This ensures that the data we encounter from an FDR mode log
semantically correct (i.e. that records follow the documented "grammar"
for FDR mode log records).
This is another part of the refactoring of D50441.
This is a slightly modified version of rL341628, avoiding the
`std::tuple<...>` constructor that is not constexpr in C++11.
Reviewers: mboerger, eizan
Subscribers: mgorny, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341769
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Matt Arsenault [Mon, 10 Sep 2018 02:23:39 +0000 (02:23 +0000)]
AMDGPU: Use GOT PSV since it has an address space now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341768
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Matt Arsenault [Mon, 10 Sep 2018 02:23:30 +0000 (02:23 +0000)]
AMDGPU: Don't abort on unknown addrspace argument
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341767
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Craig Topper [Sun, 9 Sep 2018 20:36:36 +0000 (20:36 +0000)]
[X86] Custom type legalize (v2i32 (fp_to_uint v2f64))) without avx512vl by widening to v4i32 and v4f64 instead of v8i32 and v8f64. Make it aware of x86-experimental-vector-widening-legalization
We have isel patterns for v4i32/v4f64 that artificially widen to v8i32/v8f64 so just use that.
If x86-experimental-vector-widening-legalization is enabled, we don't need any custom legalization and can just return. I've modified the test RUN lines to cover this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341765
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Sanjay Patel [Sun, 9 Sep 2018 14:13:22 +0000 (14:13 +0000)]
[SelectionDAG] enhance vector demanded elements to look at a vector select condition operand
This is the DAG equivalent of D51433.
If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition.
The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit
vectors because we don't need those anyway.
I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed
to be running there?
Differential Revision: https://reviews.llvm.org/D51696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341762
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Craig Topper [Sat, 8 Sep 2018 19:32:58 +0000 (19:32 +0000)]
[X86] Create paddus/psubus from narrower vectors with i8/i16 element types.
Summary:
This patch allows vectors with a power of 2 number of elements and i8/i16 element type to select paddus/psubus instructions. ReplaceNodeResults has been updated to custom widen these operations up to 128 bits like we already do for PAVG.
Another step towards fixing PR38691
Reviewers: RKSimon, spatel
Reviewed By: RKSimon, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341753
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Craig Topper [Sat, 8 Sep 2018 18:47:56 +0000 (18:47 +0000)]
[X86] Mark the ADCX and ADOX instruction as commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341752
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Craig Topper [Sat, 8 Sep 2018 18:47:54 +0000 (18:47 +0000)]
[X86] Add test cases for commuting ADCX/ADOX instruction to avoid copies.
This is a MIR test so we can test ADOX which we have no isel patterns for. I also plan to remove ADCX isel patterns in the near future so this will help maintain coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341751
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JF Bastien [Sat, 8 Sep 2018 16:50:56 +0000 (16:50 +0000)]
Revert "NFC: use bit_cast more in AArch64AddressingModes"
It seems some bots think std::array is either not trivially-copyable, or isn't
the right size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341750
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JF Bastien [Sat, 8 Sep 2018 16:43:49 +0000 (16:43 +0000)]
NFC: use bit_cast more in AArch64AddressingModes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341749
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Craig Topper [Sat, 8 Sep 2018 06:31:43 +0000 (06:31 +0000)]
[X86] Add commuted isel pattern for the load form of ADCX instructions.
This prevents the legacy ADC instruction from being favored over ADCX when the load is in the operand 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341745
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Craig Topper [Sat, 8 Sep 2018 06:31:41 +0000 (06:31 +0000)]
[X86] Add load folding test cases for the addcarryx intrinsic.
We are currently only able to fold a load in operand 1 to ADCX. A load in operand 0 will use the legacy ADC instruction.
Ultimately I want to remove isel support for ADCX, but first I'm going to fix the shortcomings I know of so I can write proper MIR tests to maintain coverage later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341744
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Craig Topper [Sat, 8 Sep 2018 05:08:18 +0000 (05:08 +0000)]
[X86] Add stack folding MIR test for ADCX/ADOX.
We currently have no way to isel ADOX and I plan to remove isel patterns for ADCX. This test will ensure we still have stack folding support for these instructions if we need them in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341743
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JF Bastien [Sat, 8 Sep 2018 04:07:41 +0000 (04:07 +0000)]
Fix typo in previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341742
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JF Bastien [Sat, 8 Sep 2018 03:55:25 +0000 (03:55 +0000)]
ADT: add <bit> header, implement C++20 bit_cast, use
Summary: I saw a few places that were punning through a union of FP and integer, and that made me sad. Luckily, C++20 adds bit_cast for exactly that purpose. Implement our own version in ADT (without constexpr, leaving us a bit sad), and use it in the few places my grep-fu found silly union punning.
This was originally committed as r341728 and reverted in r341730.
Reviewers: javed.absar, steven_wu, srhines
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341741
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Fangrui Song [Sat, 8 Sep 2018 02:04:20 +0000 (02:04 +0000)]
Fix typos. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341740
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Adrian Prantl [Sat, 8 Sep 2018 00:21:55 +0000 (00:21 +0000)]
Remove addBlockByrefAddress(), it is dead code as far as clang is concerned.
This patch removes addBlockByrefAddress(), it is dead code as far as
clang is concerned: Every byref block capture is emitted with a
complex expression that is equivalent to what this function does.
rdar://problem/
31629055
Differential Revision: https://reviews.llvm.org/D51763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341737
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Alina Sbirlea [Fri, 7 Sep 2018 23:51:41 +0000 (23:51 +0000)]
[MemorySSA] Relax verification of clobbering accesses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341733
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Zachary Turner [Fri, 7 Sep 2018 23:36:08 +0000 (23:36 +0000)]
Fix some of the PDB tests.
They were unintentionally calling DIA directly, which requires
Windows. We need to pass the -native flag, and this then required
fixing up one or two tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341731
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JF Bastien [Fri, 7 Sep 2018 23:23:47 +0000 (23:23 +0000)]
Revert "ADT: add <bit> header, implement C++20 bit_cast, use"
Bots sad. Looks like missing std::is_trivially_copyable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341730
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Zachary Turner [Fri, 7 Sep 2018 23:21:33 +0000 (23:21 +0000)]
[PDB] Support pointer types in the native reader.
In order to start testing this, I've added a new mode to
llvm-pdbutil which is only really useful for writing tests.
It just dumps the value of raw fields in record format.
This isn't really ideal and it won't allow us to test some
important cases, but it's better than nothing for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341729
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JF Bastien [Fri, 7 Sep 2018 23:08:26 +0000 (23:08 +0000)]
ADT: add <bit> header, implement C++20 bit_cast, use
Summary: I saw a few places that were punning through a union of FP and integer, and that made me sad. Luckily, C++20 adds bit_cast for exactly that purpose. Implement our own version in ADT (without constexpr, leaving us a bit sad), and use it in the few places my grep-fu found silly union punning.
Reviewers: javed.absar
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341728
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Reid Kleckner [Fri, 7 Sep 2018 23:07:55 +0000 (23:07 +0000)]
[COFF] Implement llvm.global_ctors priorities for MSVC COFF targets
Summary:
MSVC and LLD sort sections ASCII-betically, so we need to use section
names that sort between .CRT$XCA (the start) and .CRT$XCU (the default
priority).
In the general case, use .CRT$XCT12345 as the section name, and let the
linker sort the zero-padded digits.
Users with low priorities typically want to initialize as early as
possible, so use .CRT$XCA00199 for prioties less than 200. This number
is arbitrary.
Implements PR38552.
Reviewers: majnemer, mstorsjo
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341727
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Abderrazek Zaafrani [Fri, 7 Sep 2018 22:41:57 +0000 (22:41 +0000)]
[SimplifyIndVar] Avoid generating truncate instructions with non-hoisted Laod operand.
Differential Revision: https://reviews.llvm.org/D49151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341726
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Piotr Padlewski [Fri, 7 Sep 2018 22:29:48 +0000 (22:29 +0000)]
Set cost of invariant group intrinsics to 0
Summary:
Like with other similar intrinsics, presense of strip or
launder.invariant.group should not change the result of inlining cost.
This is because they are just markers and do not perform any computation.
Reviewers: amharc, rsmith, reames, kuhar
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D51814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341725
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Thomas Lively [Fri, 7 Sep 2018 21:54:46 +0000 (21:54 +0000)]
[WebAssembly] v8x16.shuffle
Summary:
Since the shuffle mask is not exposed as an operand in the native ISel
DAG, create a new WebAssembly ISD node exposing the mask. The mask is
lowered as sixteen immediate byte indices no matter what type the
original vector shuffle was operating on.
This CL depends on D51656
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341718
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Reid Kleckner [Fri, 7 Sep 2018 21:47:25 +0000 (21:47 +0000)]
[benchmark] Fix flags used to compile benchmark library with clang-cl
`MSVC` is true for clang-cl, but `"${CMAKE_CXX_COMPILER_ID}" STREQUAL
"MSVC"` is false, so we would enable -Wall, which means -Weverything
with clang-cl, and we get tons of undesired warnings.
Use the simpler condition to fix things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341717
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Reid Kleckner [Fri, 7 Sep 2018 21:47:00 +0000 (21:47 +0000)]
[benchmark] Re-enable benchmarks on all platforms including Windows
The assertion in MCCodeView.cpp was resolved in r340878.
This reverts both r340905 and r340836, making benchmarks build by
default everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341716
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Sanjay Patel [Fri, 7 Sep 2018 21:40:41 +0000 (21:40 +0000)]
[InstCombine][x86] add tests for possible blendv transform (PR38814); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341715
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Philip Reames [Fri, 7 Sep 2018 21:36:11 +0000 (21:36 +0000)]
[AST] Generalize argument specific aliasing
AliasSetTracker has special case handling for memset, memcpy and memmove which pre-existed argmemonly on functions and readonly and writeonly on arguments. This patch generalizes it using the AA infrastructure to any call correctly annotated.
The motivation here is to cut down on confusion, not performance per se. For most instructions, there is a direct mapping to alias set. However, this is not guaranteed by the interface and was not in fact true for these three intrinsics *and only these three intrinsics*. I kept getting myself confused about this invariant, so I figured it would be good to clearly distinguish between a instructions and alias sets. Calls happened to be an easy target.
The nice side effect is that custom implementations of memset/memcpy/memmove - including wrappers discovered by IPO - can now be optimized the same as builts by LICM.
Note: The actual removal of the memset/memtransfer specific handling will happen in a follow on NFC patch. It was originally part of this one, but separate for ease of review and rebase.
Differential Revision: https://reviews.llvm.org/D50730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341713
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Reid Kleckner [Fri, 7 Sep 2018 21:30:52 +0000 (21:30 +0000)]
[codeview] Add .cv_string directive for testing purposes
The main use case for this directive is to allow assembly writers to
write their own FPO data strings without going through the .cv_fpo*
directive family.
I'm experimenting with different RPN programs to fix PR38857, and I
figured I should go ahead and make this directive permanent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341712
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Craig Topper [Fri, 7 Sep 2018 21:28:46 +0000 (21:28 +0000)]
[X86] Add codegen tests for narrow PADDUS/PSUBUS patterns for PR38691.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341711
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Alina Sbirlea [Fri, 7 Sep 2018 21:14:48 +0000 (21:14 +0000)]
[MemorySSA] Update MemoryPhi wiring for block splitting to consider if identical edges were merged.
Summary:
Block splitting is done with either identical edges being merged, or not.
Only critical edges can be split without merging identical edges based on an option.
Teach the memoryssa updater to take this into account: for the same edge between two blocks only move one entry from the Phi in Old to the new Phi in New.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D51563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341709
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Sanjay Patel [Fri, 7 Sep 2018 21:03:34 +0000 (21:03 +0000)]
[InstCombine] narrow vector select with padded condition and extracted result (PR38691)
shuf (sel (shuf NarrowCond, undef, WideMask), X, Y), undef, NarrowMask) -->
sel NarrowCond, (shuf X, undef, NarrowMask), (shuf Y, undef, NarrowMask)
The motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=38691
...is the last regression test. In that case, we're just left with the narrow select.
Note that if we do create new shuffles, they use the existing extraction identity mask,
so there's no danger that this transform creates arbitrary shuffles.
Differential Revision: https://reviews.llvm.org/D51496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341708
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Thomas Lively [Fri, 7 Sep 2018 20:59:50 +0000 (20:59 +0000)]
[WebAssembly] Change SIMD lane indices to vec_i8imm_op
Summary: To explicitly opt out of LEB encoding for these immediates.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341707
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Nick Desaulniers [Fri, 7 Sep 2018 20:58:57 +0000 (20:58 +0000)]
[AArch64] Support reserving x1-7 registers.
Summary:
Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.
Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma
Reviewed By: nickdesaulniers, efriedma
Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D48580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341706
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Craig Topper [Fri, 7 Sep 2018 20:56:03 +0000 (20:56 +0000)]
[X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.
The generic type legalizer will scalarize vXi1 instructions getting rid of the vector entirely. Creating wider vector instructions is just going to prevent that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341705
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Craig Topper [Fri, 7 Sep 2018 20:56:01 +0000 (20:56 +0000)]
[X86] Don't create X86ISD::AVG nodes from v1iX vectors.
The type legalizer will try to scalarize this and fail.
It looks like there's some other v1iX oddities out there too since we still generated some vector instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341704
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Fangrui Song [Fri, 7 Sep 2018 20:23:15 +0000 (20:23 +0000)]
[PGO] Fix some style issue of ControlHeightReduction
Reviewers: yamauchi
Reviewed By: yamauchi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341702
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Alexandre Ganea [Fri, 7 Sep 2018 20:07:36 +0000 (20:07 +0000)]
[CMake] Fix LLVM_ENABLE_LTO option on Windows
Differential Revision: https://reviews.llvm.org/D51804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341701
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Craig Topper [Fri, 7 Sep 2018 19:14:15 +0000 (19:14 +0000)]
[X86] Modify the the rdtscp intrinsic to return values instead of taking a pointer argument
Similar to what was recently done for addcarry/subborrow and has been done for rdrand/rdseed for a while. It's better to use two results and an explicit store in IR when the store isn't part of the semantics of the instruction. This allows store->load forwarding to happen in the middle end. Or the store to be removed if its never loaded.
Differential Revision: https://reviews.llvm.org/D51803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341698
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Reid Kleckner [Fri, 7 Sep 2018 18:48:27 +0000 (18:48 +0000)]
[codeview] Improve readobj FPO dumper and pdbutil register names
The improved dumping helps me investigate PR38857.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341695
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Hiroshi Yamauchi [Fri, 7 Sep 2018 18:44:53 +0000 (18:44 +0000)]
[PGO][CHR] Build/warning fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341692
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Ana Pazos [Fri, 7 Sep 2018 18:43:43 +0000 (18:43 +0000)]
[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode
Summary:
Instead of crashing in printFRMArg, decode and warn about invalid instruction.
This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341691
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Alexandre Ganea [Fri, 7 Sep 2018 18:32:59 +0000 (18:32 +0000)]
[Error] Reintroduce type validation in createFileError()
This prevents from using ErrorSuccess as an argument to createFileError().
Differential Revision: https://reviews.llvm.org/D51490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341689
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Fangrui Song [Fri, 7 Sep 2018 18:29:20 +0000 (18:29 +0000)]
[llvm-dwp] Clean up tests X86/*.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341688
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Ana Pazos [Fri, 7 Sep 2018 18:23:19 +0000 (18:23 +0000)]
[RISCV] Fix AddressSanitizer heap-buffer-overflow in disassembling
Summary:
RISCVDisassembler should check number of bytes available before reading them.
Crash noticed when enabling -DLLVM_USE_SANITIZER=Address.
This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341686
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JF Bastien [Fri, 7 Sep 2018 18:17:59 +0000 (18:17 +0000)]
NFC: remove magic bool in LoopIdiomRecognize
Use an enum class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341684
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Hiroshi Yamauchi [Fri, 7 Sep 2018 18:00:58 +0000 (18:00 +0000)]
[PGO][CHR] Small cleanup.
Summary:
Do away with demangling. It wasn't really necessary.
Declared some local functions to be static.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341681
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Kristina Brooks [Fri, 7 Sep 2018 17:33:43 +0000 (17:33 +0000)]
[Bindings][Go] Fixed go.test failure due to C-API argument type mismatch.
go.test was failing previously with error,
Command Output (stderr):
dibuilder.go:301: cannot use C.uint(t.Encoding) (type C.uint) as type
C.LLVMDWARFTypeEncoding in argument to func literal
This patch fixes the argument type.
Patch by Chirag (Chirag Patel)
Differential Revision: https://reviews.llvm.org/D51721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341680
91177308-0d34-0410-b5e6-
96231b3b80d8