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Sanjay Patel [Thu, 26 Apr 2018 17:04:07 +0000 (17:04 +0000)]
[docs] provide the specific sanitizer option to detect junk-in-the-ftrunc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330958
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Sam Clegg [Thu, 26 Apr 2018 16:41:51 +0000 (16:41 +0000)]
[WebAssembly] Implement getRelocationValueString()
And use it in llvm-objdump.
Differential Revision: https://reviews.llvm.org/D46092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330957
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Simon Dardis [Thu, 26 Apr 2018 16:22:47 +0000 (16:22 +0000)]
[mips] Fix a test case which is keeping the expensive checks bot win red (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330956
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Mark Searles [Thu, 26 Apr 2018 16:11:19 +0000 (16:11 +0000)]
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
Differential Revision: https://reviews.llvm.org/D46067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330954
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Simon Dardis [Thu, 26 Apr 2018 16:06:34 +0000 (16:06 +0000)]
[mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.
Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330952
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Sanjay Patel [Thu, 26 Apr 2018 16:04:44 +0000 (16:04 +0000)]
[DAGCombiner] limit ftrunc optimizations with function attribute
As noted, the attribute name is subject to change once we have
the clang side implemented, but it's clear that we need some
kind of attribute-based predication here based on the discussion
for:
rL330437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330951
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Sanjay Patel [Thu, 26 Apr 2018 15:36:15 +0000 (15:36 +0000)]
[x86] add tests to show potential opt-out of ftrunc optimization; NFC
This is another preliminary step for disabling this transform as
discussed in the post-commit thread for:
rL330437
I'm using one of the names suggested there for the attribute, but
we can fix that up as needed once the clang side of this is sorted
out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330950
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Alex Bradbury [Thu, 26 Apr 2018 15:34:27 +0000 (15:34 +0000)]
[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
This causes some slight shuffling but no meaningful codegen differences on the
corpus I used for testing, but it has a larger impact when combined with e.g.
rematerialisation. Regardless, it makes sense to report as accurate
target-specific information as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330949
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Benjamin Kramer [Thu, 26 Apr 2018 15:26:29 +0000 (15:26 +0000)]
[NVPTX] Make the legalizer expand shufflevector of <2 x half>
There's no direct instruction for this, but it's trivially implemented
with two movs. Without this the code generator just dies when
encountering a shufflevector.
Differential Revision: https://reviews.llvm.org/D46116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330948
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Sanjay Patel [Thu, 26 Apr 2018 15:20:18 +0000 (15:20 +0000)]
[DAGCombiner] refactor FP->int->FP folds; NFC
As discussed in the post-review comments for rL330437,
we need to guard this fold to allow existing code to
keep working with the undefined behavior that they've
come to rely on.
That would mean duplicating more code than we already
have, so let's fix that first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330947
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Matthew Simpson [Thu, 26 Apr 2018 14:50:04 +0000 (14:50 +0000)]
[SLP] Add tests for transposable binary operations
These test cases are vectorizable, but we are currently unable to vectorize
them effectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330945
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Alex Bradbury [Thu, 26 Apr 2018 14:04:18 +0000 (14:04 +0000)]
[RISCV] Implement isZextFree
This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected
and avoiding unnecessary masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330943
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Alex Bradbury [Thu, 26 Apr 2018 14:00:35 +0000 (14:00 +0000)]
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short
Implementing isZextFree will allow lbu or lhu to be selected rather than
lb+mask and lh+mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330942
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Matthew Simpson [Thu, 26 Apr 2018 13:48:33 +0000 (13:48 +0000)]
[TTI, AArch64] Add transpose shuffle kind
This patch adds a new shuffle kind useful for transposing a 2xn matrix. These
transpose shuffle masks read corresponding even- or odd-numbered vector
elements from two n-dimensional source vectors and write each result into
consecutive elements of an n-dimensional destination vector. The transpose
shuffle kind is meant to model the TRN1 and TRN2 AArch64 instructions. As such,
this patch also considers transpose shuffles in the AArch64 implementation of
getShuffleCost.
Differential Revision: https://reviews.llvm.org/D45982
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330941
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Alex Bradbury [Thu, 26 Apr 2018 13:37:00 +0000 (13:37 +0000)]
[RISCV] Implement isTruncateFree
Adapted from ARM's implementation introduced in r313533 and r314280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330940
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Lama Saba [Thu, 26 Apr 2018 13:16:11 +0000 (13:16 +0000)]
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
Differential Revision: https://reviews.llvm.org/D45823
Change-Id: Icf6f34f6babc3cb2ff5292fde003472473037a71
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330939
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Alex Bradbury [Thu, 26 Apr 2018 13:15:17 +0000 (13:15 +0000)]
[RISCV] Implement isLegalICmpImmediate
I'm unable to construct a representative test case that demonstrates the
advantage, but it seems sensible to report accurate target-specific
information regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330938
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Alex Bradbury [Thu, 26 Apr 2018 13:00:37 +0000 (13:00 +0000)]
[RISCV] Implement isLegalAddImmediate
This causes a trivial improvement in the recently added lsr-legaladdimm.ll
test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330937
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Alex Bradbury [Thu, 26 Apr 2018 12:57:29 +0000 (12:57 +0000)]
[RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll
Add a test case which will show a codegen difference upon the implementation
of a target-specific isLegalAddImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330936
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Andrea Di Biagio [Thu, 26 Apr 2018 12:56:26 +0000 (12:56 +0000)]
[Tablegen] Simplify code in CodeGenSchedule. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330935
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Sander de Smalen [Thu, 26 Apr 2018 12:54:42 +0000 (12:54 +0000)]
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330934
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Benjamin Kramer [Thu, 26 Apr 2018 12:30:16 +0000 (12:30 +0000)]
[NVPTX] Deduplicate code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330933
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Alex Bradbury [Thu, 26 Apr 2018 12:13:48 +0000 (12:13 +0000)]
[RISCV] Implement isLegalAddressingMode for RISC-V
This has no impact on codegen for the current RISC-V unit tests or my small
benchmark set and very minor changes in a few programs in the GCC torture
suite. Based on this, I haven't been able to produce a representative test
program that demonstrates a benefit from isLegalAddressingMode. I'm committing
the patch anyway, on the basis that presenting accurate information to the
target-independent code is preferable to relying on incorrect generic
assumptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330932
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Florian Hahn [Thu, 26 Apr 2018 10:26:17 +0000 (10:26 +0000)]
[LoopInterchange] Ignore debug intrinsics during legality checks.
Reviewers: aprantl, mcrosier, karthikthecool
Reviewed By: aprantl
Subscribers: mattd, vsk, #debug-info, llvm-commits
Differential Revision: https://reviews.llvm.org/D45379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330931
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Sander de Smalen [Thu, 26 Apr 2018 09:24:45 +0000 (09:24 +0000)]
[AsmMatcher] Extend PredicateMethod with optional DiagnosticPredicate
An optional, light-weight and backward-compatible mechanism to allow
specifying that a diagnostic _only_ applies to a partial mismatch (NearMiss),
rather than a full mismatch.
Patch [1/2] in a series to improve assembler diagnostics for SVE.
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: olista01
Differential Revision: https://reviews.llvm.org/D45879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330930
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Sander de Smalen [Thu, 26 Apr 2018 08:43:22 +0000 (08:43 +0000)]
[AArch64][SVE] Asm: Negative tests for all LD1 gather (scalar+vector) load instructions.
Patch [3/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330929
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Sander de Smalen [Thu, 26 Apr 2018 08:19:53 +0000 (08:19 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Patch [2/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330928
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Shoaib Meenai [Thu, 26 Apr 2018 06:04:46 +0000 (06:04 +0000)]
[cmake] Make linker detection take flags into account
LLVM might be compiled using a toolchain file which controls the linker
to use via flags (e.g. `-B` or `-fuse-ld=`). Take these flags into
account for linker detection. We can also correct the detection by
manually passing LLVM_USE_LINKER, of course, but it seems more
convenient to have the detection take flags into account.
Differential Revision: https://reviews.llvm.org/D45464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330924
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Craig Topper [Thu, 26 Apr 2018 05:07:40 +0000 (05:07 +0000)]
[X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem in Intel syntax.
This matches objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330922
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Craig Topper [Thu, 26 Apr 2018 03:53:39 +0000 (03:53 +0000)]
[X86] Remove alignment restriction on loading folding of pcmp[ei]str* during isel too.
This is a follow up to the changes in r330896 which enabled folding after isel during peephole and register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330897
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Chandler Carruth [Thu, 26 Apr 2018 03:17:25 +0000 (03:17 +0000)]
[x86] Allow folding unaligned memory operands into pcmp[ei]str*
instructions.
These have special permission according to the x86 manual to read
unaligned memory, and this folding is done by ICC and GCC as well.
This corrects one of the issues identified in PR37246.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330896
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Chandler Carruth [Thu, 26 Apr 2018 03:12:17 +0000 (03:12 +0000)]
[x86] NFC: Add tests for idiomatic usage patterns of SSE4.2 string
comparison instructions (pcmp[ei]stri*).
These will help show improvements from fixes to PR37246.
I've not really covered the mask forms of this intrinsic as I don't have
as good of an intuition about the likely usage patterns there. Happy for
someone to extend this with tests covering the mask form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330895
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Max Kazantsev [Thu, 26 Apr 2018 02:07:40 +0000 (02:07 +0000)]
Revert "[SCEV] Make computeExitLimit more simple and more powerful"
This reverts commit
023c8be90980e0180766196cba86f81608b35d38.
This patch triggers miscompile of zlib on PowerPC platform. Most likely it is
caused by some pre-backend PPC-specific pass, but we don't clearly know the
reason yet. So we temporally revert this patch with intention to return it
once the problem is resolved. See bug 37229 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330893
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Reid Kleckner [Wed, 25 Apr 2018 23:34:15 +0000 (23:34 +0000)]
[codeview] Ignore .cv_loc directives at the end of a function
If no data or instructions are emitted after a location directive, we
should clear the cv_loc when we change sections, or it will be emitted
at the beginning of the next section. This violates our invariant that
all .cv_loc directives belong to the same section. Add clearer
assertions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330884
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Vedant Kumar [Wed, 25 Apr 2018 21:50:09 +0000 (21:50 +0000)]
[ADT] Make filter_iterator support bidirectional iteration
This makes it possible to reverse a filtered range. For example, here's
a way to visit memory accesses in a BasicBlock in reverse order:
auto MemInsts = reverse(make_filter_range(BB, [](Instruction &I) {
return isa<StoreInst>(&I) || isa<LoadInst>(&I);
}));
for (auto &MI : MemInsts)
...
To implement this functionality, I factored out forward iteration
functionality into filter_iterator_base, and added a specialization of
filter_iterator_impl which supports bidirectional iteration. Thanks to
Tim Shen, Zachary Turner, and others for suggesting this design and
providing feedback! This version of the patch supersedes the original
(https://reviews.llvm.org/D45792).
This was motivated by a problem we encountered in D45657: we'd like to
visit the non-debug-info instructions in a BasicBlock in reverse order.
Testing: check-llvm, check-clang
Differential Revision: https://reviews.llvm.org/D45853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330875
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Simon Pilgrim [Wed, 25 Apr 2018 20:59:16 +0000 (20:59 +0000)]
[CostModel][X86] Remove hard coded SDIV/UDIV vector costs
Algorithmically compute the 'x20' SDIV/UDIV vector costs - this is necessary for PR36550 when DIV costs will be driven from the scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330870
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Reid Kleckner [Wed, 25 Apr 2018 20:16:24 +0000 (20:16 +0000)]
Fix PluginsTests failure on Windows buildbots by enabling it everywhere
lit is picking up a stale executable in the unittests tree, which is
failing on Windows.
To simplify the CMake and avoid problems like this in the future, now we
always compile the test, but the test exits successfully when plugins
are not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330867
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Tom Stellard [Wed, 25 Apr 2018 20:02:53 +0000 (20:02 +0000)]
AMDGPU/R600: Move int_r600_store_stream_output to the public intrinsic file
Summary:
The TableGen'd GlobalISel instruction selector assumes all intrinsics are in
the public Intrinsic:: namespace.
Reviewers: jvesely, nhaehnle
Reviewed By: jvesely, nhaehnle
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330866
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Mark Searles [Wed, 25 Apr 2018 19:21:26 +0000 (19:21 +0000)]
[AMDGPU] Waitcnt pass: add debug options
- Add "amdgpu-waitcnt-forcezero" to force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- Add debug counters to control force emit of s_waitcnt instrs; debug counters:
si-insert-waitcnts-forceexp: force emit s_waitcnt expcnt(0) instrs
si-insert-waitcnts-forcevm: force emit s_waitcnt lgkmcnt(0) instrs
si-insert-waitcnts-forcelgkm: force emit s_waitcnt vmcnt(0) instrs
- Add some debug statements
Note that a variant of this patch was previously committed/reverted.
Differential Revision: https://reviews.llvm.org/D45888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330862
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David Bolvansky [Wed, 25 Apr 2018 18:58:53 +0000 (18:58 +0000)]
[SimplifyLibcalls] Atoi, strtol replacements
Reviewers: spatel, lebedev.ri, xbolva00, efriedma
Reviewed By: xbolva00, efriedma
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D45418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330860
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Francis Visoiu Mistrih [Wed, 25 Apr 2018 18:58:06 +0000 (18:58 +0000)]
[MIR] Add support for debug metadata for fixed stack objects
Debug var, expr and loc were only supported for non-fixed stack objects.
This patch adds the following fields to the "fixedStack:" entries, and
renames the ones from "stack:" to:
* debug-info-variable
* debug-info-expression
* debug-info-location
Differential Revision: https://reviews.llvm.org/D46032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330859
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Nico Weber [Wed, 25 Apr 2018 18:34:00 +0000 (18:34 +0000)]
IWYU llvm-config.h for LLVM_VERSION_STRING
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330856
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Sam Clegg [Wed, 25 Apr 2018 18:24:08 +0000 (18:24 +0000)]
[WebAssebmly] Add Module name to WasmSymbol
Imports in a wasm module can have custom module name. This change
adds the module name to the WasmSymbol structure so that the linker
can preserve this module name.
This is needed to fix: https://bugs.llvm.org/show_bug.cgi?id=37168
Differential Revision: https://reviews.llvm.org/D45797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330854
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Nico Weber [Wed, 25 Apr 2018 18:06:23 +0000 (18:06 +0000)]
Rename sancov.cc to sancov.cpp
LLVM uses cpp as its C++ file ending.
https://reviews.llvm.org/D46068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330853
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Simon Pilgrim [Wed, 25 Apr 2018 18:03:31 +0000 (18:03 +0000)]
[CostModel][X86] Add div/rem tests for non-uniform constant divisors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330852
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Craig Topper [Wed, 25 Apr 2018 17:35:03 +0000 (17:35 +0000)]
[X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over load folding.
Previously we only formed MUL_IMM when we split a constant. This blocked load folding on those cases. We should also form MUL_IMM for 3/5/9 to favor LEA over load folding.
Differential Revision: https://reviews.llvm.org/D46040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330850
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Reid Kleckner [Wed, 25 Apr 2018 17:30:00 +0000 (17:30 +0000)]
Revert r330755 "[lit] Report line number for failed RUN command"
It is causing many tests to fail on Windows buildbots:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/10211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330848
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Alex Bradbury [Wed, 25 Apr 2018 17:25:29 +0000 (17:25 +0000)]
[RISCV] Allow call pseudoinstruction to be used to call a function name that coincides with a register name
Previously `call zero`, `call f0` etc would fail. This leads to compilation
failures if building programs that define functions with those names and using
-save-temps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330846
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Nico Weber [Wed, 25 Apr 2018 17:24:41 +0000 (17:24 +0000)]
Don't list a source file twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330845
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Taewook Oh [Wed, 25 Apr 2018 17:19:21 +0000 (17:19 +0000)]
[ICP] Do not attempt type matching for variable length arguments.
Summary:
When performing indirect call promotion, current implementation inspects "all" parameters of the callsite and attemps to match with the formal argument type of the callee function. However, it is not possible to find the type for variable length arguments, and the compiler crashes when it attemps to match the type for variable lenght argument.
It seems that the bug is introduced with D40658. Prior to that, the type matching is performed only for the parameters whose ID is less than callee->getFunctionNumParams(). The attached test case will crash without the patch.
Reviewers: mssimpso, davidxl, davide
Reviewed By: mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330844
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Nico Weber [Wed, 25 Apr 2018 17:07:46 +0000 (17:07 +0000)]
Rename Attributes.gen, Intrinsics.gen to Attributes.inc, Intrinsics.inc
Virtually all other tablegen outputs are called .inc, not .gen, so rename these two too for consistency.
No behavior change.
https://reviews.llvm.org/D46058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330843
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Sanjay Patel [Wed, 25 Apr 2018 16:34:01 +0000 (16:34 +0000)]
[InstCombine] clean up foldSelectICmpAnd(); NFC
As discussed in D45862, we want to delete parts of
this code because it can create more instructions
than it removes. But we also want to preserve some
folds that are winners, so tidy up what's here to
make splitting the good from bad a bit easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330841
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Sanjay Patel [Wed, 25 Apr 2018 15:59:23 +0000 (15:59 +0000)]
[InstCombine] add tests for select to logic folds; NFC
As discussed in D45862, we want these folds sometimes
because they're good improvements.
But as we can see here, the current logic doesn't
check uses and doesn't produce optimal code in all
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330837
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Simon Pilgrim [Wed, 25 Apr 2018 15:22:03 +0000 (15:22 +0000)]
[CostModel][X86] Recursive call for cost of imul for packed v16i16 constant shift left.
Don't just assume cost = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330834
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Amara Emerson [Wed, 25 Apr 2018 14:43:59 +0000 (14:43 +0000)]
[AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic.
rdar://
38674040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330831
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Paul Walker [Wed, 25 Apr 2018 14:42:44 +0000 (14:42 +0000)]
Fix typo in static_assert for size of LoadSDNodeBitfields.
Reviewers: fhahn, jlebar, delena, RKSimon
Reviewed By: fhahn, jlebar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330830
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Filipe Cabecinhas [Wed, 25 Apr 2018 14:39:16 +0000 (14:39 +0000)]
[llvm-mca] Make ViewOptions static. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330829
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Shiva Chen [Wed, 25 Apr 2018 14:19:12 +0000 (14:19 +0000)]
[RISCV] Expand function call to "call" pseudoinstruction
To do this:
1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer
split the symbol.
2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer
split the symbol.
3. Let PseudoCALL match direct call with target operand TargetGlobalAddress
and TargetExternalSymbol.
Differential Revision: https://reviews.llvm.org/D44885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330827
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Shiva Chen [Wed, 25 Apr 2018 14:18:55 +0000 (14:18 +0000)]
[RISCV] Support "call" pseudoinstruction in the MC layer
To do this:
1. Add PseudoCALLIndirct to match indirect function call.
2. Add PseudoCALL to support parsing and print pseudo `call` in assembly
3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type
while encoding:
auipc ra, func
jalr ra, ra, 0
If we expand PseudoCALL before emitting assembly, we will see auipc and jalr
pair when compile with -S. It's hard for assembly parser to parsing this
pair and identify it's semantic is function call and then insert R_RISCV_CALL
relocation type. Although we could insert R_RISCV_PCREL_HI20 and
R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL.
Due to RISCV relocation design, auipc and jalr pair only can relax to jal with
R_RISCV_CALL + R_RISCV_RELAX relocation types.
We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before
emitting assembly(RISCVAsmPrinter) because we want to preserve call
pseudoinstruction in assembly code. It's more readable and assembly parser
could identify call assembly and insert R_RISCV_CALL relocation type.
Differential Revision: https://reviews.llvm.org/D45859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330826
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Simon Dardis [Wed, 25 Apr 2018 14:12:57 +0000 (14:12 +0000)]
[mips] Teach the delay slot filler to transform 'jal' for microMIPS
ISel is currently picking 'JAL' over 'JAL_MM' for calling a function when
targeting microMIPS. A later patch will correct this behaviour.
This patch extends the mechanism for transforming instructions into their short
delay to recognise 'JAL_MM' for transforming into 'JALS_MM'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330825
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Simon Pilgrim [Wed, 25 Apr 2018 13:19:04 +0000 (13:19 +0000)]
[llvm-mca][X86] Updated fma3 tests after rL330820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330822
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Simon Pilgrim [Wed, 25 Apr 2018 13:07:58 +0000 (13:07 +0000)]
[X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classes
This removes all the FMA InstRW overrides.
If we ever get PR36924, then we can remove many of these declarations from models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330820
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Roman Lebedev [Wed, 25 Apr 2018 12:48:23 +0000 (12:48 +0000)]
[X86][AArch64][NFC] Finish adding 'bad' tests for masked merge unfolding with constants.
I have initially committed basic tests in, rL330771,
but then quickly discovered that there are a few more
interesting patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330819
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Alexander Timofeev [Wed, 25 Apr 2018 12:32:46 +0000 (12:32 +0000)]
[AMDGPU] Revert
b0efc4fd6 (https://reviews.llvm.org/D40556)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330818
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Gabor Buella [Wed, 25 Apr 2018 12:15:34 +0000 (12:15 +0000)]
Avoid a warning on pointer casting, NFC
Reviewers: philip.pfaffe
Reviewed By: philip.pfaffe
Differential Revision: https://reviews.llvm.org/D46012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330817
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Andrea Di Biagio [Wed, 25 Apr 2018 11:33:14 +0000 (11:33 +0000)]
[llvm-mca] Add a new option category for views.
With this patch, options to add/tweak views are all grouped together in the
-help output.
The new "View Options" category looks like this:
```
View Options:
-dispatch-stats - Print dispatch statistics
-instruction-info - Print the instruction info view
-instruction-tables - Print instruction tables
-register-file-stats - Print register file statistics
-resource-pressure - Print the resource pressure view
-retire-stats - Print retire control unit statistics
-scheduler-stats - Print scheduler statistics
-timeline - Print the timeline view
-timeline-max-cycles=<uint> - Maximum number of cycles in the timeline view. Defaults to 80 cycles
-timeline-max-iterations=<uint> - Maximum number of iterations to print in timeline view
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330816
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Greg Bedwell [Wed, 25 Apr 2018 11:20:42 +0000 (11:20 +0000)]
[UpdateTestChecks] Change update_mca_test_checks.py file mode to match the other scripts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330815
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Simon Pilgrim [Wed, 25 Apr 2018 10:51:19 +0000 (10:51 +0000)]
[X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330813
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Simon Pilgrim [Wed, 25 Apr 2018 10:50:39 +0000 (10:50 +0000)]
[X86][SNB] Remove unnecessary WriteFBlendLd InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330812
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Andrea Di Biagio [Wed, 25 Apr 2018 10:27:30 +0000 (10:27 +0000)]
[llvm-mca] run clang-format on a bunch of files. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330811
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Simon Dardis [Wed, 25 Apr 2018 10:19:22 +0000 (10:19 +0000)]
[mips] Fix the definition of sync, synci
Also, fix the disassembly of synci for microMIPS.
Reviewers: abeserminji, smaksimovic, atanasyan
Differential Revision: https://reviews.llvm.org/D45870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330810
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Andrea Di Biagio [Wed, 25 Apr 2018 10:18:25 +0000 (10:18 +0000)]
[llvm-mca] Default to the native host cpu if flag -mcpu is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330809
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Andrea Di Biagio [Wed, 25 Apr 2018 09:38:58 +0000 (09:38 +0000)]
[llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330807
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Florian Hahn [Wed, 25 Apr 2018 09:35:54 +0000 (09:35 +0000)]
[LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.
This also means we have to check if the latch is the exiting block now,
as `transform` expects the latches to be the exiting blocks too.
https://bugs.llvm.org/show_bug.cgi?id=36586
Reviewers: efriedma, davide, karthikthecool
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330806
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Sander de Smalen [Wed, 25 Apr 2018 09:26:47 +0000 (09:26 +0000)]
[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.
The added combinations of vector (ZPR) and Shift/Extend are:
Unscaled:
ZPR64ExtLSL8: signed 64-bit offsets (z0.d)
ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw)
ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw)
Unpacked and unscaled:
ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw)
ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw)
Unpacked and scaled:
ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>)
ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>)
Scaled:
ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>)
ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>)
ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>)
ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>)
Patch [1/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330805
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Bjorn Pettersson [Wed, 25 Apr 2018 09:23:56 +0000 (09:23 +0000)]
[DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTree
Summary:
When Reassociate is rewriting an expression tree it may
reuse old binary expression nodes, for new expressions.
Whenever an expression node is reused, but with a non-trivial
change in the result, we need to invalidate any debug info
that is associated with the node.
If for example rewriting
x = mul a, b
y = mul c, x
into
x = mul c, b
y = mul a, x
we still get the same result for 'y', but 'x' is a new expression.
All debug info referring to 'x' must be invalidated (marked as
optimized out) since we no longer calculate the expected value.
As a side-effect this patch avoid (at least some) problems where
reassociate could end up creating IR with debug-use before def.
Earlier the dbg.value nodes where left untouched in the IR, while
the reused binary nodes where sinked to just before the root node
of the rewritten expression tree. See PR27273 for more info about
such problems.
Reviewers: dblaikie, aprantl, dexonsmith
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D45975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330804
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Craig Topper [Wed, 25 Apr 2018 06:24:51 +0000 (06:24 +0000)]
[TableGen] Fix bad indentation in tablegen output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330801
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David Bolvansky [Wed, 25 Apr 2018 04:33:36 +0000 (04:33 +0000)]
Merging r46043:
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330799
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Craig Topper [Wed, 25 Apr 2018 03:40:45 +0000 (03:40 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330797
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Geoff Berry [Wed, 25 Apr 2018 02:17:56 +0000 (02:17 +0000)]
[DivRemPairs] Fix non-determinism in use list order.
Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created. This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.
Reviewers: spatel
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D45858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330792
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Chandler Carruth [Wed, 25 Apr 2018 00:18:07 +0000 (00:18 +0000)]
[PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the new
update API for dominators rather than doing manual, hacky updates.
This is just the first step, but in some ways the most important as it
moves the non-trivial unswitching to update the domtree rather than
fully recalculating it each time.
Subsequent patches should remove the custom update logic used by the
trivial unswitch and replace it with uses of the update API.
This also fixes a number of bugs I was seeing when testing non-trivial
unswitch due to it querying the quasi-correct dominator tree. Now the
tree is 100% correct and safe to query. That said, there are still more
bugs I can see with non-trivial unswitch just running over the test
suite, so more bugfix patches are needed as well.
Thanks to both Sanjoy and Fedor for reviews and testing!
Differential Revision: https://reviews.llvm.org/D45943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330787
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Jessica Paquette [Tue, 24 Apr 2018 22:38:15 +0000 (22:38 +0000)]
[MachineOutliner] Check for explicit uses of LR/W30 in MI operands
Before, the outliner would grab ADRPs that used LR/W30. This patch fixes
that by checking for explicit uses of those registers before the special-casing
for ADRPs.
This also adds a test that ensures that those sorts of ADRPs won't be outlined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330783
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Craig Topper [Tue, 24 Apr 2018 22:35:27 +0000 (22:35 +0000)]
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.
Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.
This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.
Differential Revision: https://reviews.llvm.org/D45585#inline-402825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330781
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Reid Kleckner [Tue, 24 Apr 2018 22:03:07 +0000 (22:03 +0000)]
Fix path separator checks on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330779
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Warren Ristow [Tue, 24 Apr 2018 22:01:50 +0000 (22:01 +0000)]
[X86] Account for partial stack slot spills (PR30821)
Previously, _any_ store or load instruction was considered to be
operating on a spill if it had a frameindex as an operand, and thus
was fair game for optimisations such as "StackSlotColoring". This
usually works, except on architectures where spills can be partially
restored, for example on X86 where a spilt vector can have a single
component loaded (zeroing the rest of the target register). This can be
mis-interpreted and the zero extension unsoundly eliminated, see
pr30821.
To avoid this, this commit optionally provides the caller to
isLoadFromStackSlot and isStoreToStackSlot with the number of bytes
spilt/loaded by the given instruction. Optimisations can then determine
that a full spill followed by a partial load (or vice versa), for
example, cannot necessarily be commuted.
Patch by Jeremy Morse!
Differential Revision: https://reviews.llvm.org/D44782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330778
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Alexander Shaposhnikov [Tue, 24 Apr 2018 21:44:13 +0000 (21:44 +0000)]
[llvm-objcopy] Adjust the help message
Capitalize the first letter,
make the text a bit more consistent.
NFC.
Differential revision: https://reviews.llvm.org/D46025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330777
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Reid Kleckner [Tue, 24 Apr 2018 21:41:50 +0000 (21:41 +0000)]
Bring back APInt self-move assignment check for MSVC only
Summary:
It was removed about a year ago in r300477. Bring it back, along with
its unittest, when the MSVC STL is in use. The MSVC STL performs
self-assignment in std::shuffle. These days, llvm::sort calls
std::shuffle when expensive checks are enabled to help find
non-determinism bugs.
Reviewers: craig.topper, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330776
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Tom Stellard [Tue, 24 Apr 2018 21:37:57 +0000 (21:37 +0000)]
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
Summary: This is no longer used by mesa since its 18.0.0 release.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D45988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330775
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Tom Stellard [Tue, 24 Apr 2018 21:29:36 +0000 (21:29 +0000)]
AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functions
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330774
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Mandeep Singh Grang [Tue, 24 Apr 2018 21:25:57 +0000 (21:25 +0000)]
[docs] Add a note on non-deterministic sorting order of equal elements
Reviewers: RKSimon, t.p.northover, dexonsmith
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330773
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Roman Lebedev [Tue, 24 Apr 2018 21:23:22 +0000 (21:23 +0000)]
[X86][AArch64][NFC] Add tests for masked merge unfolding with %y = const
The fold was added in D45733.
This appears to be a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330771
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Daniel Neilson [Tue, 24 Apr 2018 21:12:45 +0000 (21:12 +0000)]
[CaptureTracking] Fixup const correctness of DomTree arg (NFC)
Summary:
The PointerMayBeCapturedBefore function's DomTree arg should be
const instead of non-const. There are no non-const uses of it
in the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330769
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Sanjay Patel [Tue, 24 Apr 2018 21:06:06 +0000 (21:06 +0000)]
[InstCombine] move tests for select with bit-test of condition; NFC
These are all but 1 of the select-of-constant tests that appear
to be transformed within foldSelectICmpAnd() and the block above
it predicated by decomposeBitTestICmp().
As discussed in D45862 (and can be seen in several tests here),
we probably want to stop doing those transforms because they
can increase the instruction count without benefitting other
passes or codegen.
The 1 test not included here is a urem test where the bit hackery
allows us to remove a urem. To preserve killing that urem, we
should do some stronger known-bits analysis or pattern matching of
'urem x, (select-of-pow2-constants)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330768
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Tom Stellard [Tue, 24 Apr 2018 20:51:28 +0000 (20:51 +0000)]
AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330767
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Chandler Carruth [Tue, 24 Apr 2018 20:30:56 +0000 (20:30 +0000)]
[wasm] Fix uninitialized memory introduced in r330749.
Found with MSan. This was causing all the WASM MC tests to fail about
10% of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330764
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Rafael Espindola [Tue, 24 Apr 2018 20:15:27 +0000 (20:15 +0000)]
[bugpoint] Fix crash when testing for miscompilation.
Method BugDriver::performFinalCleanups(...) would delete Module object
it worked on, which was also deleted by its caller
(e.g. TestCodeGenerator(...)). Changed the code to avoid double delete
and make Module ownership slightly clearer.
Patch by Andrzej Janik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330763
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Sam McCall [Tue, 24 Apr 2018 20:08:05 +0000 (20:08 +0000)]
[Support] fix countLeadingZeros for types shorter than int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330762
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Shoaib Meenai [Tue, 24 Apr 2018 19:47:39 +0000 (19:47 +0000)]
[cmake] Fix libc++ detection
-stdlib=libc++ is added to both the compilation and the link flags, but
the logic for adding it was only checking if it was supported during
compilation and not linking. This could lead to false positives, for
example when using clang with libstdc++ (where the compiler would
support -stdlib=libc++ but then linking would fail because of libc++
actually being unavailable).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330761
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Simon Pilgrim [Tue, 24 Apr 2018 19:22:01 +0000 (19:22 +0000)]
[X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330760
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Vedant Kumar [Tue, 24 Apr 2018 19:20:18 +0000 (19:20 +0000)]
[test] Update llc checks for CodeGen/X86/avg.ll
The output of update_llc_test_checks.py on this test file has changed,
so the test file should be updated to minimize source changes in future
patches.
The test updates for this file appear to be limited to relaxations of
the form:
-; SSE2-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
+; SSE2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
This was suggested in https://reviews.llvm.org/D45995.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330758
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