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Nico Weber [Wed, 25 Apr 2018 18:06:23 +0000 (18:06 +0000)]
Rename sancov.cc to sancov.cpp
LLVM uses cpp as its C++ file ending.
https://reviews.llvm.org/D46068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330853
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Simon Pilgrim [Wed, 25 Apr 2018 18:03:31 +0000 (18:03 +0000)]
[CostModel][X86] Add div/rem tests for non-uniform constant divisors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330852
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Craig Topper [Wed, 25 Apr 2018 17:35:03 +0000 (17:35 +0000)]
[X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over load folding.
Previously we only formed MUL_IMM when we split a constant. This blocked load folding on those cases. We should also form MUL_IMM for 3/5/9 to favor LEA over load folding.
Differential Revision: https://reviews.llvm.org/D46040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330850
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Reid Kleckner [Wed, 25 Apr 2018 17:30:00 +0000 (17:30 +0000)]
Revert r330755 "[lit] Report line number for failed RUN command"
It is causing many tests to fail on Windows buildbots:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/10211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330848
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Alex Bradbury [Wed, 25 Apr 2018 17:25:29 +0000 (17:25 +0000)]
[RISCV] Allow call pseudoinstruction to be used to call a function name that coincides with a register name
Previously `call zero`, `call f0` etc would fail. This leads to compilation
failures if building programs that define functions with those names and using
-save-temps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330846
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Nico Weber [Wed, 25 Apr 2018 17:24:41 +0000 (17:24 +0000)]
Don't list a source file twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330845
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Taewook Oh [Wed, 25 Apr 2018 17:19:21 +0000 (17:19 +0000)]
[ICP] Do not attempt type matching for variable length arguments.
Summary:
When performing indirect call promotion, current implementation inspects "all" parameters of the callsite and attemps to match with the formal argument type of the callee function. However, it is not possible to find the type for variable length arguments, and the compiler crashes when it attemps to match the type for variable lenght argument.
It seems that the bug is introduced with D40658. Prior to that, the type matching is performed only for the parameters whose ID is less than callee->getFunctionNumParams(). The attached test case will crash without the patch.
Reviewers: mssimpso, davidxl, davide
Reviewed By: mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330844
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Nico Weber [Wed, 25 Apr 2018 17:07:46 +0000 (17:07 +0000)]
Rename Attributes.gen, Intrinsics.gen to Attributes.inc, Intrinsics.inc
Virtually all other tablegen outputs are called .inc, not .gen, so rename these two too for consistency.
No behavior change.
https://reviews.llvm.org/D46058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330843
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Sanjay Patel [Wed, 25 Apr 2018 16:34:01 +0000 (16:34 +0000)]
[InstCombine] clean up foldSelectICmpAnd(); NFC
As discussed in D45862, we want to delete parts of
this code because it can create more instructions
than it removes. But we also want to preserve some
folds that are winners, so tidy up what's here to
make splitting the good from bad a bit easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330841
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Sanjay Patel [Wed, 25 Apr 2018 15:59:23 +0000 (15:59 +0000)]
[InstCombine] add tests for select to logic folds; NFC
As discussed in D45862, we want these folds sometimes
because they're good improvements.
But as we can see here, the current logic doesn't
check uses and doesn't produce optimal code in all
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330837
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Simon Pilgrim [Wed, 25 Apr 2018 15:22:03 +0000 (15:22 +0000)]
[CostModel][X86] Recursive call for cost of imul for packed v16i16 constant shift left.
Don't just assume cost = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330834
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Amara Emerson [Wed, 25 Apr 2018 14:43:59 +0000 (14:43 +0000)]
[AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic.
rdar://
38674040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330831
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Paul Walker [Wed, 25 Apr 2018 14:42:44 +0000 (14:42 +0000)]
Fix typo in static_assert for size of LoadSDNodeBitfields.
Reviewers: fhahn, jlebar, delena, RKSimon
Reviewed By: fhahn, jlebar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330830
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Filipe Cabecinhas [Wed, 25 Apr 2018 14:39:16 +0000 (14:39 +0000)]
[llvm-mca] Make ViewOptions static. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330829
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Shiva Chen [Wed, 25 Apr 2018 14:19:12 +0000 (14:19 +0000)]
[RISCV] Expand function call to "call" pseudoinstruction
To do this:
1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer
split the symbol.
2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer
split the symbol.
3. Let PseudoCALL match direct call with target operand TargetGlobalAddress
and TargetExternalSymbol.
Differential Revision: https://reviews.llvm.org/D44885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330827
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Shiva Chen [Wed, 25 Apr 2018 14:18:55 +0000 (14:18 +0000)]
[RISCV] Support "call" pseudoinstruction in the MC layer
To do this:
1. Add PseudoCALLIndirct to match indirect function call.
2. Add PseudoCALL to support parsing and print pseudo `call` in assembly
3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type
while encoding:
auipc ra, func
jalr ra, ra, 0
If we expand PseudoCALL before emitting assembly, we will see auipc and jalr
pair when compile with -S. It's hard for assembly parser to parsing this
pair and identify it's semantic is function call and then insert R_RISCV_CALL
relocation type. Although we could insert R_RISCV_PCREL_HI20 and
R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL.
Due to RISCV relocation design, auipc and jalr pair only can relax to jal with
R_RISCV_CALL + R_RISCV_RELAX relocation types.
We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before
emitting assembly(RISCVAsmPrinter) because we want to preserve call
pseudoinstruction in assembly code. It's more readable and assembly parser
could identify call assembly and insert R_RISCV_CALL relocation type.
Differential Revision: https://reviews.llvm.org/D45859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330826
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Simon Dardis [Wed, 25 Apr 2018 14:12:57 +0000 (14:12 +0000)]
[mips] Teach the delay slot filler to transform 'jal' for microMIPS
ISel is currently picking 'JAL' over 'JAL_MM' for calling a function when
targeting microMIPS. A later patch will correct this behaviour.
This patch extends the mechanism for transforming instructions into their short
delay to recognise 'JAL_MM' for transforming into 'JALS_MM'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330825
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Simon Pilgrim [Wed, 25 Apr 2018 13:19:04 +0000 (13:19 +0000)]
[llvm-mca][X86] Updated fma3 tests after rL330820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330822
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Simon Pilgrim [Wed, 25 Apr 2018 13:07:58 +0000 (13:07 +0000)]
[X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classes
This removes all the FMA InstRW overrides.
If we ever get PR36924, then we can remove many of these declarations from models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330820
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Roman Lebedev [Wed, 25 Apr 2018 12:48:23 +0000 (12:48 +0000)]
[X86][AArch64][NFC] Finish adding 'bad' tests for masked merge unfolding with constants.
I have initially committed basic tests in, rL330771,
but then quickly discovered that there are a few more
interesting patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330819
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Alexander Timofeev [Wed, 25 Apr 2018 12:32:46 +0000 (12:32 +0000)]
[AMDGPU] Revert
b0efc4fd6 (https://reviews.llvm.org/D40556)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330818
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Gabor Buella [Wed, 25 Apr 2018 12:15:34 +0000 (12:15 +0000)]
Avoid a warning on pointer casting, NFC
Reviewers: philip.pfaffe
Reviewed By: philip.pfaffe
Differential Revision: https://reviews.llvm.org/D46012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330817
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Andrea Di Biagio [Wed, 25 Apr 2018 11:33:14 +0000 (11:33 +0000)]
[llvm-mca] Add a new option category for views.
With this patch, options to add/tweak views are all grouped together in the
-help output.
The new "View Options" category looks like this:
```
View Options:
-dispatch-stats - Print dispatch statistics
-instruction-info - Print the instruction info view
-instruction-tables - Print instruction tables
-register-file-stats - Print register file statistics
-resource-pressure - Print the resource pressure view
-retire-stats - Print retire control unit statistics
-scheduler-stats - Print scheduler statistics
-timeline - Print the timeline view
-timeline-max-cycles=<uint> - Maximum number of cycles in the timeline view. Defaults to 80 cycles
-timeline-max-iterations=<uint> - Maximum number of iterations to print in timeline view
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330816
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Greg Bedwell [Wed, 25 Apr 2018 11:20:42 +0000 (11:20 +0000)]
[UpdateTestChecks] Change update_mca_test_checks.py file mode to match the other scripts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330815
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Simon Pilgrim [Wed, 25 Apr 2018 10:51:19 +0000 (10:51 +0000)]
[X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330813
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Simon Pilgrim [Wed, 25 Apr 2018 10:50:39 +0000 (10:50 +0000)]
[X86][SNB] Remove unnecessary WriteFBlendLd InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330812
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Andrea Di Biagio [Wed, 25 Apr 2018 10:27:30 +0000 (10:27 +0000)]
[llvm-mca] run clang-format on a bunch of files. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330811
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Simon Dardis [Wed, 25 Apr 2018 10:19:22 +0000 (10:19 +0000)]
[mips] Fix the definition of sync, synci
Also, fix the disassembly of synci for microMIPS.
Reviewers: abeserminji, smaksimovic, atanasyan
Differential Revision: https://reviews.llvm.org/D45870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330810
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Andrea Di Biagio [Wed, 25 Apr 2018 10:18:25 +0000 (10:18 +0000)]
[llvm-mca] Default to the native host cpu if flag -mcpu is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330809
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Andrea Di Biagio [Wed, 25 Apr 2018 09:38:58 +0000 (09:38 +0000)]
[llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330807
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Florian Hahn [Wed, 25 Apr 2018 09:35:54 +0000 (09:35 +0000)]
[LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.
This also means we have to check if the latch is the exiting block now,
as `transform` expects the latches to be the exiting blocks too.
https://bugs.llvm.org/show_bug.cgi?id=36586
Reviewers: efriedma, davide, karthikthecool
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330806
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Sander de Smalen [Wed, 25 Apr 2018 09:26:47 +0000 (09:26 +0000)]
[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.
The added combinations of vector (ZPR) and Shift/Extend are:
Unscaled:
ZPR64ExtLSL8: signed 64-bit offsets (z0.d)
ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw)
ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw)
Unpacked and unscaled:
ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw)
ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw)
Unpacked and scaled:
ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>)
ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>)
Scaled:
ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>)
ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>)
ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>)
ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>)
Patch [1/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330805
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Bjorn Pettersson [Wed, 25 Apr 2018 09:23:56 +0000 (09:23 +0000)]
[DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTree
Summary:
When Reassociate is rewriting an expression tree it may
reuse old binary expression nodes, for new expressions.
Whenever an expression node is reused, but with a non-trivial
change in the result, we need to invalidate any debug info
that is associated with the node.
If for example rewriting
x = mul a, b
y = mul c, x
into
x = mul c, b
y = mul a, x
we still get the same result for 'y', but 'x' is a new expression.
All debug info referring to 'x' must be invalidated (marked as
optimized out) since we no longer calculate the expected value.
As a side-effect this patch avoid (at least some) problems where
reassociate could end up creating IR with debug-use before def.
Earlier the dbg.value nodes where left untouched in the IR, while
the reused binary nodes where sinked to just before the root node
of the rewritten expression tree. See PR27273 for more info about
such problems.
Reviewers: dblaikie, aprantl, dexonsmith
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D45975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330804
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Craig Topper [Wed, 25 Apr 2018 06:24:51 +0000 (06:24 +0000)]
[TableGen] Fix bad indentation in tablegen output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330801
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David Bolvansky [Wed, 25 Apr 2018 04:33:36 +0000 (04:33 +0000)]
Merging r46043:
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330799
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Craig Topper [Wed, 25 Apr 2018 03:40:45 +0000 (03:40 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330797
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Geoff Berry [Wed, 25 Apr 2018 02:17:56 +0000 (02:17 +0000)]
[DivRemPairs] Fix non-determinism in use list order.
Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created. This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.
Reviewers: spatel
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D45858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330792
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Chandler Carruth [Wed, 25 Apr 2018 00:18:07 +0000 (00:18 +0000)]
[PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the new
update API for dominators rather than doing manual, hacky updates.
This is just the first step, but in some ways the most important as it
moves the non-trivial unswitching to update the domtree rather than
fully recalculating it each time.
Subsequent patches should remove the custom update logic used by the
trivial unswitch and replace it with uses of the update API.
This also fixes a number of bugs I was seeing when testing non-trivial
unswitch due to it querying the quasi-correct dominator tree. Now the
tree is 100% correct and safe to query. That said, there are still more
bugs I can see with non-trivial unswitch just running over the test
suite, so more bugfix patches are needed as well.
Thanks to both Sanjoy and Fedor for reviews and testing!
Differential Revision: https://reviews.llvm.org/D45943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330787
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Jessica Paquette [Tue, 24 Apr 2018 22:38:15 +0000 (22:38 +0000)]
[MachineOutliner] Check for explicit uses of LR/W30 in MI operands
Before, the outliner would grab ADRPs that used LR/W30. This patch fixes
that by checking for explicit uses of those registers before the special-casing
for ADRPs.
This also adds a test that ensures that those sorts of ADRPs won't be outlined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330783
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Craig Topper [Tue, 24 Apr 2018 22:35:27 +0000 (22:35 +0000)]
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.
Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.
This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.
Differential Revision: https://reviews.llvm.org/D45585#inline-402825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330781
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Reid Kleckner [Tue, 24 Apr 2018 22:03:07 +0000 (22:03 +0000)]
Fix path separator checks on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330779
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Warren Ristow [Tue, 24 Apr 2018 22:01:50 +0000 (22:01 +0000)]
[X86] Account for partial stack slot spills (PR30821)
Previously, _any_ store or load instruction was considered to be
operating on a spill if it had a frameindex as an operand, and thus
was fair game for optimisations such as "StackSlotColoring". This
usually works, except on architectures where spills can be partially
restored, for example on X86 where a spilt vector can have a single
component loaded (zeroing the rest of the target register). This can be
mis-interpreted and the zero extension unsoundly eliminated, see
pr30821.
To avoid this, this commit optionally provides the caller to
isLoadFromStackSlot and isStoreToStackSlot with the number of bytes
spilt/loaded by the given instruction. Optimisations can then determine
that a full spill followed by a partial load (or vice versa), for
example, cannot necessarily be commuted.
Patch by Jeremy Morse!
Differential Revision: https://reviews.llvm.org/D44782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330778
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Alexander Shaposhnikov [Tue, 24 Apr 2018 21:44:13 +0000 (21:44 +0000)]
[llvm-objcopy] Adjust the help message
Capitalize the first letter,
make the text a bit more consistent.
NFC.
Differential revision: https://reviews.llvm.org/D46025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330777
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Reid Kleckner [Tue, 24 Apr 2018 21:41:50 +0000 (21:41 +0000)]
Bring back APInt self-move assignment check for MSVC only
Summary:
It was removed about a year ago in r300477. Bring it back, along with
its unittest, when the MSVC STL is in use. The MSVC STL performs
self-assignment in std::shuffle. These days, llvm::sort calls
std::shuffle when expensive checks are enabled to help find
non-determinism bugs.
Reviewers: craig.topper, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330776
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Tom Stellard [Tue, 24 Apr 2018 21:37:57 +0000 (21:37 +0000)]
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
Summary: This is no longer used by mesa since its 18.0.0 release.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D45988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330775
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Tom Stellard [Tue, 24 Apr 2018 21:29:36 +0000 (21:29 +0000)]
AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functions
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330774
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Mandeep Singh Grang [Tue, 24 Apr 2018 21:25:57 +0000 (21:25 +0000)]
[docs] Add a note on non-deterministic sorting order of equal elements
Reviewers: RKSimon, t.p.northover, dexonsmith
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330773
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Roman Lebedev [Tue, 24 Apr 2018 21:23:22 +0000 (21:23 +0000)]
[X86][AArch64][NFC] Add tests for masked merge unfolding with %y = const
The fold was added in D45733.
This appears to be a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330771
91177308-0d34-0410-b5e6-
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Daniel Neilson [Tue, 24 Apr 2018 21:12:45 +0000 (21:12 +0000)]
[CaptureTracking] Fixup const correctness of DomTree arg (NFC)
Summary:
The PointerMayBeCapturedBefore function's DomTree arg should be
const instead of non-const. There are no non-const uses of it
in the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330769
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Sanjay Patel [Tue, 24 Apr 2018 21:06:06 +0000 (21:06 +0000)]
[InstCombine] move tests for select with bit-test of condition; NFC
These are all but 1 of the select-of-constant tests that appear
to be transformed within foldSelectICmpAnd() and the block above
it predicated by decomposeBitTestICmp().
As discussed in D45862 (and can be seen in several tests here),
we probably want to stop doing those transforms because they
can increase the instruction count without benefitting other
passes or codegen.
The 1 test not included here is a urem test where the bit hackery
allows us to remove a urem. To preserve killing that urem, we
should do some stronger known-bits analysis or pattern matching of
'urem x, (select-of-pow2-constants)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330768
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 24 Apr 2018 20:51:28 +0000 (20:51 +0000)]
AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330767
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Chandler Carruth [Tue, 24 Apr 2018 20:30:56 +0000 (20:30 +0000)]
[wasm] Fix uninitialized memory introduced in r330749.
Found with MSan. This was causing all the WASM MC tests to fail about
10% of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330764
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 24 Apr 2018 20:15:27 +0000 (20:15 +0000)]
[bugpoint] Fix crash when testing for miscompilation.
Method BugDriver::performFinalCleanups(...) would delete Module object
it worked on, which was also deleted by its caller
(e.g. TestCodeGenerator(...)). Changed the code to avoid double delete
and make Module ownership slightly clearer.
Patch by Andrzej Janik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330763
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Sam McCall [Tue, 24 Apr 2018 20:08:05 +0000 (20:08 +0000)]
[Support] fix countLeadingZeros for types shorter than int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330762
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Shoaib Meenai [Tue, 24 Apr 2018 19:47:39 +0000 (19:47 +0000)]
[cmake] Fix libc++ detection
-stdlib=libc++ is added to both the compilation and the link flags, but
the logic for adding it was only checking if it was supported during
compilation and not linking. This could lead to false positives, for
example when using clang with libstdc++ (where the compiler would
support -stdlib=libc++ but then linking would fail because of libc++
actually being unavailable).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330761
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Simon Pilgrim [Tue, 24 Apr 2018 19:22:01 +0000 (19:22 +0000)]
[X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330760
91177308-0d34-0410-b5e6-
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Vedant Kumar [Tue, 24 Apr 2018 19:20:18 +0000 (19:20 +0000)]
[test] Update llc checks for CodeGen/X86/avg.ll
The output of update_llc_test_checks.py on this test file has changed,
so the test file should be updated to minimize source changes in future
patches.
The test updates for this file appear to be limited to relaxations of
the form:
-; SSE2-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
+; SSE2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
This was suggested in https://reviews.llvm.org/D45995.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330758
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Andrea Di Biagio [Tue, 24 Apr 2018 19:14:56 +0000 (19:14 +0000)]
[llvm-mca] Remove unused flag -verbose. NFC
I forgot to remove it at r329794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330757
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Simon Pilgrim [Tue, 24 Apr 2018 18:49:25 +0000 (18:49 +0000)]
[X86] Split off PHMINPOSUW to their own schedule class
This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330756
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Joel E. Denny [Tue, 24 Apr 2018 18:43:25 +0000 (18:43 +0000)]
[lit] Report line number for failed RUN command
When debugging test failures with -vv (or -v in the case of the
internal shell), this makes it easier to locate the RUN line that
failed. For example, clang's test/Driver/linux-ld.c has 892 total RUN
lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines
after concatenation for line continuations.
When reading the generated shell script, this also makes it easier to
locate the RUN line that produced each command.
To support reporting RUN line numbers in the case of the internal
shell, this patch extends the internal shell to support the null
command, ":", except pipelines are not supported.
Reviewed By: asmith, delcypher
Differential Revision: https://reviews.llvm.org/D44598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330755
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Stanislav Mekhanoshin [Tue, 24 Apr 2018 18:17:55 +0000 (18:17 +0000)]
[AMDGPU] Truncate packed inline constant
If a packed inline constant is sign extended it must be truncated
after the shift. I.e. a constant (0xH0000, 0xHBC00), will be represented
as 0xFFFFFFFFBC000000 in the IR because the immediate is sign extended
to 64 bit. After the value shifted right by 16 to use it in a low part
with op_sel_hi it becomes 0xFFFFFFFFBC00 and does not qualify as inline
constant any longer.
Fixed the error and added verification code. Without the fix and with
the verification bug is causing pk_max_f16_literal.ll to fail.
Differential Revision: https://reviews.llvm.org/D45987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330752
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Simon Pilgrim [Tue, 24 Apr 2018 18:13:57 +0000 (18:13 +0000)]
[XOP] v4i32 IFMA 'VPMACS' instructions should use the WritePMULLD schedule class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330751
91177308-0d34-0410-b5e6-
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Sam Clegg [Tue, 24 Apr 2018 18:11:36 +0000 (18:11 +0000)]
[WebAssembly] Use section index in relocation section header
Rather than referring to sections my their code, use the
absolute index of the target section within the module.
See https://github.com/WebAssembly/tool-conventions/issues/52
Differential Revision: https://reviews.llvm.org/D45980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330749
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Florian Hahn [Tue, 24 Apr 2018 18:10:52 +0000 (18:10 +0000)]
[LoopInterchange] Add REQUIRES: asserts to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330748
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Simon Pilgrim [Tue, 24 Apr 2018 17:59:54 +0000 (17:59 +0000)]
[AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not variable shuffles
These variants all take an immediate shuffle mask value and should be scheduled as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330747
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Nico Weber [Tue, 24 Apr 2018 17:29:05 +0000 (17:29 +0000)]
Let TableGen write output only if it changed, instead of doing so in cmake.
Removes one subprocess and one temp file from the build for each tablegen
invocation.
No intended behavior change.
https://reviews.llvm.org/D45899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330742
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Simon Dardis [Tue, 24 Apr 2018 17:11:37 +0000 (17:11 +0000)]
Reland "[mips] Guard traps for microMIPS correctly"
This is part of fixing the instruction predicates for MIPS.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44212
This patch relands r327409, hopefully without the problematic part of the
tests that cause FileCheck to assert on the windows expensive checks bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330741
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Diego Caballero [Tue, 24 Apr 2018 17:04:17 +0000 (17:04 +0000)]
[LV][VPlan] Detect outer loops for explicit vectorization.
Patch #2 from VPlan Outer Loop Vectorization Patch Series #1
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).
This patch introduces the basic infrastructure to detect, legality check
and process outer loops annotated with hints for explicit vectorization.
All these changes are protected under the feature flag
-enable-vplan-native-path. This should make this patch NFC for the existing
inner loop vectorizer.
Reviewers: hfinkel, mkuper, rengolin, fhahn, aemerson, mssimpso.
Differential Revision: https://reviews.llvm.org/D42447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330739
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Florian Hahn [Tue, 24 Apr 2018 16:55:32 +0000 (16:55 +0000)]
[LoopInterchange] Make isProfitableForVectorization slightly more conservative.
After D43236, we started interchanging loops with empty dependence
matrices. In isProfitableForVectorization, we try to determine if
interchanging makes the loop dependences more friendly to the
vectorizer. If there are no dependences, we should not interchange,
based on that heuristic.
Reviewers: efriedma, mcrosier, karthikthecool, blitz.opensource
Reviewed By: mcrosier
Differential Revision: https://reviews.llvm.org/D45208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330738
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Simon Pilgrim [Tue, 24 Apr 2018 16:43:07 +0000 (16:43 +0000)]
[X86][F16C] Add WriteCvtF2FSt scheduling class
Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330737
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Fangrui Song [Tue, 24 Apr 2018 16:32:55 +0000 (16:32 +0000)]
[ADT] Remove ilist_default_traits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330736
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Simon Pilgrim [Tue, 24 Apr 2018 16:26:51 +0000 (16:26 +0000)]
[X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies
These are stores, not loads, so don't need to account for load latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330735
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Simon Pilgrim [Tue, 24 Apr 2018 16:22:59 +0000 (16:22 +0000)]
[X86][IVB] Add F16C resource tests.
Note this is IvyBridge (which shares the model) NOT SandyBridge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330734
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Andrea Di Biagio [Tue, 24 Apr 2018 16:19:08 +0000 (16:19 +0000)]
[llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.
The instruction printer used by llvm-mca to generate the performance report now
defaults the output assembly format to the format used for the input assembly
file.
On x86, the asm format can be either AT&T or Intel, depending on the
presence/absence of directive `.intel_syntax`.
Users can still specify a different assembly dialect with the command line flag
-output-asm-variant=<uint>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330733
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Simon Atanasyan [Tue, 24 Apr 2018 16:14:00 +0000 (16:14 +0000)]
[mips] Show an error if register number is out of range
Current code does not check that a register number is in the 0-31 range.
Sometimes the parser checks that later for some kinds of instructions,
but that leads to unclear / incorrect error messages like that:
% cat test.s
.text
lb $4, 8($32)
% llvm-mc test.s -triple=mips64-unknown-linux
test.s:2:10: error: expected memory with 16-bit signed offset
lb $4, 8($32)
^
Sometimes the parser just crashes:
% cat test.s
.text
lw $4, 8($32)
% llvm-mc test.s -triple=mips64-unknown-linux
This patch resolves the problem by checking that register number after
'$' sign is in the 0-31 range. If the number is out of the range the
parser shows the `invalid register number` error, but treats invalid
register number as a normal one to continue parsing and catch other
possible errors.
Differential Revision: https://reviews.llvm.org/D45919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330732
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Sanjay Patel [Tue, 24 Apr 2018 16:08:03 +0000 (16:08 +0000)]
[InstCombine] regenerate checks; NFC
The first step in fixing problems raised in D45862
is to make the problems visible. Now we can more easily
see/update cases where selects have been turned into
multiple instructions with no apparent improvement in
analysis or benefits for other passes (vectorization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330731
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Mark Searles [Tue, 24 Apr 2018 15:59:59 +0000 (15:59 +0000)]
[AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency:
- s/SWaitcnt/Waitcnt s/WaitCnt/Waitcnt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330730
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Sanjay Patel [Tue, 24 Apr 2018 15:42:30 +0000 (15:42 +0000)]
[InstCombine] regenerate checks; NFC
The current version of the script uses regex for params.
This could mask a bug (param values got wrongly swapped),
but it seems unlikely in practice, so let's just update
the whole file to reduce diffs when there is a meaningful
change here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330729
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Dan Liew [Tue, 24 Apr 2018 15:42:00 +0000 (15:42 +0000)]
[lit] Remove spurious `-` in invocation of lit in
`shtest-xunit-output.py` test.
Although there is no `-` file Jeremy Morse has reported to me that it
causes problems in their setup because lit tries to find it and ends up
loading an out of tree lit configuration file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330728
91177308-0d34-0410-b5e6-
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Nico Weber [Tue, 24 Apr 2018 15:41:02 +0000 (15:41 +0000)]
Remove LLVM_INSTALL_CCTOOLS_SYMLINKS
It used to symlink dsymutil to llvm-dsymutil, but after r327790 llvm's dsymutil
binary is now called dsymutil without prefix.
r327792 then reversed the direction of the symlink if
LLVM_INSTALL_CCTOOLS_SYMLINKS was set, but that looks like a buildfix and not
like something anyone should need.
https://reviews.llvm.org/D45966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330727
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David Blaikie [Tue, 24 Apr 2018 15:40:07 +0000 (15:40 +0000)]
Fix some layering in AggressiveInstCombine (avoiding inclusion of Scalar.h)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330726
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Benjamin Kramer [Tue, 24 Apr 2018 15:28:47 +0000 (15:28 +0000)]
[LoadStoreVectorize] Ignore interleaved invariant loads.
The memory location an invariant load is using can never be clobbered by
any store, so it's safe to move the load ahead of the store.
Differential Revision: https://reviews.llvm.org/D46011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330725
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Andrea Di Biagio [Tue, 24 Apr 2018 14:53:16 +0000 (14:53 +0000)]
[llvm-mca] Refactor the Scheduler interface in preparation for PR36663.
Zero latency instructions are now scheduled the same way as other instructions.
Before this patch, there was a specialzed code path for those instructions.
All scheduler events are now generated from method `scheduleInstruction()` and
from method `cycleEvent()`. This will make easier to implement a "execution
stage", and let that stage publish all the scheduler events.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330723
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Simon Pilgrim [Tue, 24 Apr 2018 14:47:11 +0000 (14:47 +0000)]
[X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330720
91177308-0d34-0410-b5e6-
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Ulrich Weigand [Tue, 24 Apr 2018 14:03:21 +0000 (14:03 +0000)]
[SystemZ] Use preferred 16-byte function alignment
While not necessary for correctness, it is preferable for
performance reasons on all architectures we currently support
to align functions to 16-byte boundaries by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330718
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 24 Apr 2018 13:38:26 +0000 (13:38 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330716
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 24 Apr 2018 13:24:56 +0000 (13:24 +0000)]
[X86] Fix missing cfi from sitofp checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330715
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 24 Apr 2018 13:21:41 +0000 (13:21 +0000)]
[X86] Add vector element insertion/extraction scheduler classes
Split off pinsr/pextr and extractps instructions.
(Mostly) fixes PR36887.
Note: It might be worth adding a WriteFInsertLd class as well in the future.
Differential Revision: https://reviews.llvm.org/D45929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330714
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Simon Pilgrim [Tue, 24 Apr 2018 13:01:03 +0000 (13:01 +0000)]
[MC] Remove orphan MCSchedModel::computeReciprocalThroughput declaration. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330713
91177308-0d34-0410-b5e6-
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Alexander Ivchenko [Tue, 24 Apr 2018 12:57:51 +0000 (12:57 +0000)]
[X86] Replace action Promote with Expand for operation ISD::SINT_TO_FP
Summary:
If attribute "use-soft-float"="true" is set then X86ISelLowering.cpp sets
'Promote' action for ISD::SINT_TO_FP operation on type i32.
But 'Promote' action is not proper in this case since lib function
__floatsidf is available for casting from signed int to float type.
Thus Expand action is more suitable here.
The Expand action should be set for ISD::UINT_TO_FP for soft float as well.
If function attribute "use-soft-float"="true" is set then infinite looping
can happen in DAG combining, function visitSINT_TO_FP() replaces SINT_TO_FP
node with UINT_TO_FP node and function combineUIntToFP() replace vice versa in cycle.
The fix prevents it.
Patch by vrybalov
Differential Revision: https://reviews.llvm.org/D45572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330711
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Francis Visoiu Mistrih [Tue, 24 Apr 2018 11:00:46 +0000 (11:00 +0000)]
[CodeGen] Print user-friendly debug locations as MI comments
If available, print the file, line and column of the DebugLoc attached
to the MachineInstr:
MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17
renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17
Differential Revision: https://reviews.llvm.org/D45992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330709
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Chandler Carruth [Tue, 24 Apr 2018 10:33:08 +0000 (10:33 +0000)]
[PM/LoopUnswitch] Fix a bug in the loop block set formation of the new
loop unswitch.
This code incorrectly added the header to the loop block set early. As
a consequence we would incorrectly conclude that a nested loop body had
already been visited when the header of the outer loop was the preheader
of the nested loop. In retrospect, adding the header eagerly doesn't
really make sense. It seems nicer to let the cycle be formed naturally.
This will catch crazy bugs in the CFG reconstruction where we can't
correctly form the cycle earlier rather than later, and makes the rest
of the logic just fall out.
I've also added various asserts that make these issues *much* easier to
debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330707
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Petar Jovanovic [Tue, 24 Apr 2018 10:32:08 +0000 (10:32 +0000)]
Correct dwarf unwind information in function epilogue
This patch aims to provide correct dwarf unwind information in function
epilogue for X86.
It consists of two parts. The first part inserts CFI instructions that set
appropriate cfa offset and cfa register in emitEpilogue() in
X86FrameLowering. This part is X86 specific.
The second part is platform independent and ensures that:
* CFI instructions do not affect code generation (they are not counted as
instructions when tail duplicating or tail merging)
* Unwind information remains correct when a function is modified by
different passes. This is done in a late pass by analyzing information
about cfa offset and cfa register in BBs and inserting additional CFI
directives where necessary.
Added CFIInstrInserter pass:
* analyzes each basic block to determine cfa offset and register are valid
at its entry and exit
* verifies that outgoing cfa offset and register of predecessor blocks match
incoming values of their successors
* inserts additional CFI directives at basic block beginning to correct the
rule for calculating CFA
Having CFI instructions in function epilogue can cause incorrect CFA
calculation rule for some basic blocks. This can happen if, due to basic
block reordering, or the existence of multiple epilogue blocks, some of the
blocks have wrong cfa offset and register values set by the epilogue block
above them.
CFIInstrInserter is currently run only on X86, but can be used by any target
that implements support for adding CFI instructions in epilogue.
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D42848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330706
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Simon Dardis [Tue, 24 Apr 2018 10:19:29 +0000 (10:19 +0000)]
[mips] Correct the patterns for bswap
Guard the MIPS64 variant correctly for i64, mark the MIPS32 version as not
in microMIPS and provide the microMIPS version.
Additionally, remove a related stale XFAIL'd test as bswap has its own test
case providing coverage.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330705
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Andrea Di Biagio [Tue, 24 Apr 2018 10:09:32 +0000 (10:09 +0000)]
[llvm-mca][CommandGuide] Fix typo in example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330703
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Andrei Elovikov [Tue, 24 Apr 2018 09:24:29 +0000 (09:24 +0000)]
[CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.
Summary:
The pass is supposed to scalarize such intrinsics if the target does not support
them natively, so if the scalarization does not happen instruction selection
crashes due to inability to lower these intrinsics.
Reviewers: andrew.w.kaylor, craig.topper
Reviewed By: andrew.w.kaylor
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330700
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Max Kazantsev [Tue, 24 Apr 2018 09:11:01 +0000 (09:11 +0000)]
[NFC] Remove recently added SE verification because it may be false-positive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330699
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Florian Hahn [Tue, 24 Apr 2018 09:10:05 +0000 (09:10 +0000)]
[LoopInfo] Verify BBMap tracks innermost loops for BBs.
By checking that none of the child loops contain a BB we make sure BBMap
contains the innermost loop defining BB. This invariant was violated in
LoopInterchange and got caught by this assertion.
Reviewers: chandlerc, mzolotukhin, sanjoy, mehdi_amini, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330698
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Sander de Smalen [Tue, 24 Apr 2018 08:59:08 +0000 (08:59 +0000)]
[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330697
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Roman Lebedev [Tue, 24 Apr 2018 08:40:37 +0000 (08:40 +0000)]
Link to AggressiveInstCombine in a few places. Unbreaks build for me.
/usr/local/bin/ld.lld: error: undefined symbol: llvm::createAggressiveInstCombinerPass()
>>> referenced by cc1_main.cpp
>>> tools/clang/tools/driver/CMakeFiles/clang.dir/cc1_main.cpp.o:(_GLOBAL__sub_I_cc1_main.cpp)
And so on
The bot coverage is clearly missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330693
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