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Fedor Sergeev [Wed, 19 Sep 2018 22:42:57 +0000 (22:42 +0000)]
[New PM] Introducing PassInstrumentation framework
Pass Execution Instrumentation interface enables customizable instrumentation
of pass execution, as per "RFC: Pass Execution Instrumentation interface"
posted 06/07/2018 on llvm-dev@
The intent is to provide a common machinery to implement all
the pass-execution-debugging features like print-before/after,
opt-bisect, time-passes etc.
Here we get a basic implementation consisting of:
* PassInstrumentationCallbacks class that handles registration of callbacks
and access to them.
* PassInstrumentation class that handles instrumentation-point interfaces
that call into PassInstrumentationCallbacks.
* Callbacks accept StringRef which is just a name of the Pass right now.
There were some ideas to pass an opaque wrapper for the pointer to pass instance,
however it appears that pointer does not actually identify the instance
(adaptors and managers might have the same address with the pass they govern).
Hence it was decided to go simple for now and then later decide on what the proper
mental model of identifying a "pass in a phase of pipeline" is.
* Callbacks accept llvm::Any serving as a wrapper for const IRUnit*, to remove direct dependencies
on different IRUnits (e.g. Analyses).
* PassInstrumentationAnalysis analysis is explicitly requested from PassManager through
usual AnalysisManager::getResult. All pass managers were updated to run that
to get PassInstrumentation object for instrumentation calls.
* Using tuples/index_sequence getAnalysisResult helper to extract generic AnalysisManager's extra
args out of a generic PassManager's extra args. This is the only way I was able to explicitly
run getResult for PassInstrumentationAnalysis out of a generic code like PassManager::run or
RepeatedPass::run.
TODO: Upon lengthy discussions we agreed to accept this as an initial implementation
and then get rid of getAnalysisResult by improving RepeatedPass implementation.
* PassBuilder takes PassInstrumentationCallbacks object to pass it further into
PassInstrumentationAnalysis. Callbacks registration should be performed directly
through PassInstrumentationCallbacks.
* new-pm tests updated to account for PassInstrumentationAnalysis being run
* Added PassInstrumentation tests to PassBuilderCallbacks unit tests.
Other unit tests updated with registration of the now-required PassInstrumentationAnalysis.
Reviewers: chandlerc, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D47858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342597
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Evgeniy Stepanov [Wed, 19 Sep 2018 22:29:56 +0000 (22:29 +0000)]
Revert "[XRay][compiler-rt] FDRLogWriter Abstraction" and 1 more.
Revert the following 2 commits to fix standalone compiler-rt build:
* r342523 [XRay] Detect terminfo library
* r342518 [XRay][compiler-rt] FDRLogWriter Abstraction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342596
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Sanjay Patel [Wed, 19 Sep 2018 22:00:56 +0000 (22:00 +0000)]
[x86] add test for 256-bit andn (PR37749); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342595
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Sanjay Patel [Wed, 19 Sep 2018 21:48:30 +0000 (21:48 +0000)]
[SelectionDAG] allow vector types with isBitwiseNot()
The test diff in not-and-simplify.ll is from a use in SimplifyDemandedBits,
and the test diff in add.ll is from a DAGCombiner transform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342594
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Juergen Ributzka [Wed, 19 Sep 2018 21:36:26 +0000 (21:36 +0000)]
Fix the build when LLVM_TARGETS_TO_BUILD is empty.
Using LLVMTestingSupport in the LLVM_LINK_COMPONENTS breaks the build when
LLVM_TARGETS_TO_BUILD is set to empty.
Libraries that depend on LLVMTestingSupport need to use
target_link_libraries(<target> PRIVATE LLVMTestingSupport) instead.
This required change was already commited by r341899 to fix another build
issue.
This fixes rdar://problem/
44615064.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342593
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Sanjay Patel [Wed, 19 Sep 2018 21:28:39 +0000 (21:28 +0000)]
[x86] add test for add+not vector fold; NFC
The fold uses 'isBitwiseNot()', but that's not vector-friendly currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342592
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Matthias Braun [Wed, 19 Sep 2018 20:50:51 +0000 (20:50 +0000)]
AArch64: Add FuseCryptoEOR fusion rules
There's some additional rules available on newer apple CPUs.
rdar://
41235346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342590
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Matthias Braun [Wed, 19 Sep 2018 20:50:49 +0000 (20:50 +0000)]
MachineScheduler: Add -misched-print-dags flag
Add a flag to dump the schedule DAG to the debug stream. This will be
used in upcoming commits to test schedule DAG mutations such as macro
fusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342589
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Chandler Carruth [Wed, 19 Sep 2018 20:45:09 +0000 (20:45 +0000)]
Workaround a limitation of llvm::Any when used with types that have
a converting constructor from llvm::Any like gmock matchers. This issue
has come up elsewhere as well and the workaround here is being
considered for use in the standard long-term, but we can pretty cheaply
experiment with it to see if anything ends up going wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342588
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Evandro Menezes [Wed, 19 Sep 2018 19:51:29 +0000 (19:51 +0000)]
[ARM] Adjust the feature set for Exynos
Fine tune the cost model for all Exynos processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342585
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Evandro Menezes [Wed, 19 Sep 2018 19:43:23 +0000 (19:43 +0000)]
[ARM] Refactor Exynos feature set (NFC)
Since all Exynos processors share the same feature set, fold them in the
implied fatures list for the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342583
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Matt Morehouse [Wed, 19 Sep 2018 19:37:24 +0000 (19:37 +0000)]
[InstCombine] Disable strcmp->memcmp transform for MSan.
Summary:
The strcmp->memcmp transform can make the resulting memcmp read
uninitialized data, which MSan doesn't like.
Resolves https://github.com/google/sanitizers/issues/993.
Reviewers: eugenis, xbolva00
Reviewed By: eugenis
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D52272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342582
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Simon Pilgrim [Wed, 19 Sep 2018 18:59:08 +0000 (18:59 +0000)]
[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86.
Original Patch by @jonpa:
While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.
Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.
Differential Revision: https://reviews.llvm.org/D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342578
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Michael Berg [Wed, 19 Sep 2018 18:52:08 +0000 (18:52 +0000)]
Copy utilities updated and added for MI flags
Summary: This patch adds a GlobalIsel copy utility into MI for flags and updates the instruction emitter for the SDAG path. Some tests show new behavior and I added one for GlobalIsel which mirrors an SDAG test for handling nsw/nuw.
Reviewers: spatel, wristow, arsenm
Reviewed By: arsenm
Subscribers: wdng
Differential Revision: https://reviews.llvm.org/D52006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342576
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Sanjay Patel [Wed, 19 Sep 2018 18:52:00 +0000 (18:52 +0000)]
[x86] change names of vector splitting helper functions; NFC
As the code comments suggest, these are about splitting, and they
are not necessarily limited to lowering, so that misled me.
There's nothing that's actually x86-specific in these either, so
they might be better placed in a common header so any target can
use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342575
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Vitaly Buka [Wed, 19 Sep 2018 18:51:42 +0000 (18:51 +0000)]
[ThinLTO] Write TYPE_IDs for types used in functions imported by aliases
Summary:
ThinLTO imports alias as a copy of a aliasee, so when we import such functions with type tests we will
need type ids used by function. However after D49565 we pick types only during processing of
FunctionSummary which is not happening for such aliesees.
Example:
Unit U1 with a type, a functions F with the type check, and an alias A to the function.
Unit U2 with only call to the alias A.
In particular, this happens when we use -mconstructor-aliases, which is default.
So if c++ unit only creates instance of the class, without calling any other methods it will lack of
necessary type ids, which will result in false CFI reports.
Reviewers: tejohnson, eugenis
Subscribers: pcc, mehdi_amini, inglorion, eraman, hiraditya, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342574
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Vitaly Buka [Wed, 19 Sep 2018 18:51:25 +0000 (18:51 +0000)]
[ThinLTO] Extract getReferencedTypeIds from [NFC]
Summary: Refactoring before D52201
Reviewers: eugenis, tejohnson
Subscribers: pcc, inglorion, hiraditya, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342573
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Simon Atanasyan [Wed, 19 Sep 2018 18:46:29 +0000 (18:46 +0000)]
[mips][microMIPS] Extending size reduction pass with MOVEP
The patch extends size reduction pass for MicroMIPS. Two MOVE
instructions are transformed into one MOVEP instrucition.
Patch by Milena Vujosevic Janicic.
Differential revision: https://reviews.llvm.org/D52037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342572
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Simon Atanasyan [Wed, 19 Sep 2018 18:46:21 +0000 (18:46 +0000)]
[mips][microMIPS] Fix the definition of MOVEP instruction
The patch fixes definition of MOVEP instruction. Two registers are used
instead of register pairs. This is necessary as machine verifier cannot
handle register pairs.
Patch by Milena Vujosevic Janicic.
Differential revision: https://reviews.llvm.org/D52035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342571
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Chris Bieneman [Wed, 19 Sep 2018 18:29:58 +0000 (18:29 +0000)]
[LLJIT] Add API to expose linking layer from LLJIT classes
Summary: This patch just surfaces the object linking layer from the LLJIT classes so that clients can take advantage of the changes implemented in r341154.
Reviewers: lhames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342567
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Simon Pilgrim [Wed, 19 Sep 2018 18:11:34 +0000 (18:11 +0000)]
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support
This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles.
Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity.
Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc.
NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification.
Differential Revision: https://reviews.llvm.org/D52140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342564
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Andrea Di Biagio [Wed, 19 Sep 2018 17:54:01 +0000 (17:54 +0000)]
Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555.
The reason why build #25777 might have failed is because the SmallVector move
constructor is _not_ noexcept, and the stl implementation used by that buildbot
calls _VSTD::move_if_noexcept() (according to the backtrace).
OpcodeInfo has a default move constructor, and the copy constructor is deleted.
However, as far as I can see, SmallVector doesn't declare a noexcept move
constructor. So, what I believe it is happening here is that,
_VSTD::move_if_noexcept() returns an lvalue reference and not an rvalue
reference.
This eventually triggers a copy that fails to compile.
Hopefully, using a std::vector instead of SmallVector (as it was originally
suggested by Simon in the code review) should be enough to unbreak the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342561
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Carl Ritson [Wed, 19 Sep 2018 16:32:12 +0000 (16:32 +0000)]
[AMDGPU] Add instruction selection for i1 to f16 conversion
Summary:
This is required for GPUs with 16 bit instructions where f16 is a
legal register type and hence int_to_fp i1 to f16 is not lowered
by legalizing.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52018
Change-Id: Ie4c0fd6ced7cf10ad612023c6879724d9ded5851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342558
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Yonghong Song [Wed, 19 Sep 2018 16:04:13 +0000 (16:04 +0000)]
[bpf] Symbol sizes and types in object file
Clang-compiled object files currently don't include the symbol sizes and
types. Some tools however need that information. For example, ctfconvert
uses that information to generate FreeBSD's CTF representation from ELF
files.
With this patch, symbol sizes and types are included in object files.
Signed-off-by: Paul Chaignon <paul.chaignon@orange.com>
Reported-by: Yutaro Hayakawa <yhayakawa3720@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342556
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Andrea Di Biagio [Wed, 19 Sep 2018 15:57:45 +0000 (15:57 +0000)]
[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
This patch adds the ability for processor models to describe dependency breaking
instructions.
Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.
The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).
```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
return false;
}
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
return isZeroIdiom(MI);
}
```
An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.
A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.
STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.
This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.
This patch supersedes the one committed at r338372 (phabricator review: D49310).
The main advantages are:
- We can describe subtarget predicates via tablegen using STIPredicates.
- We can describe zero-idioms / dep-breaking instructions directly via
tablegen in the scheduling models.
In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
- Teach how to identify optimizable register-register moves
- Teach how to identify slow LEA instructions (each subtarget defining its own
concept of "slow" LEA).
- Teach how to identify instructions that have undocumented false dependencies
on the output registers on some processors only.
It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.
This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.
Differential Revision: https://reviews.llvm.org/D52174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342555
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Sanjay Patel [Wed, 19 Sep 2018 15:57:40 +0000 (15:57 +0000)]
[DAGCombiner][x86] add transform/hook to decompose integer multiply into shift/add
This is an alternative to D37896. I don't see a way to decompose multiplies
generically without a target hook to tell us when it's profitable.
ARM and AArch64 may be able to remove some duplicate code that overlaps with
this transform.
As a first step, we're only getting the most clear wins on the vector examples
requested in PR34474:
https://bugs.llvm.org/show_bug.cgi?id=34474
As noted in the code comment, it's likely that the x86 constraints are tighter
than necessary, but it may not always be a win to replace a pmullw/pmulld.
Differential Revision: https://reviews.llvm.org/D52195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342554
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Fedor Sergeev [Wed, 19 Sep 2018 14:54:48 +0000 (14:54 +0000)]
Revert rL342544: [New PM] Introducing PassInstrumentation framework
A bunch of bots fail to compile unittests. Reverting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342552
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Simon Pilgrim [Wed, 19 Sep 2018 14:52:34 +0000 (14:52 +0000)]
Fix -Wsign-compare warnings. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342551
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Alex Bradbury [Wed, 19 Sep 2018 14:51:42 +0000 (14:51 +0000)]
[AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR
This involves changing the shouldExpandAtomicCmpXchgInIR interface, but I have
updated the in-tree backends using this hook (ARM, AArch64, Hexagon) so they
will see no functional change. Previously this hook returned bool, but it now
returns AtomicExpansionKind.
This hook allows targets to select how a given cmpxchg is to be expanded.
D48131 uses this to expand part-word cmpxchg to a target-specific intrinsic.
See my associated RFC for more info on the motivation for this change
<http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html>.
Differential Revision: https://reviews.llvm.org/D48130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342550
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Martin Storsjo [Wed, 19 Sep 2018 14:30:45 +0000 (14:30 +0000)]
[benchmark] Cherrypick fix for MinGW/ARM from upstream
This fixes building for Windows on ARM, with MinGW headers.
(Building for Windows on ARM with Windows SDK still is unsupported
by the benchmark library.)
Differential Revision: https://reviews.llvm.org/D52262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342549
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Roman Lebedev [Wed, 19 Sep 2018 13:35:46 +0000 (13:35 +0000)]
[InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanonical ((-1 << y) >> y) mask
Summary:
The last low-bit-mask-pattern-producing-pattern i can think of.
https://rise4fun.com/Alive/UGzE <- non-canonical
But we can not canonicalize it because of extra uses.
https://bugs.llvm.org/show_bug.cgi?id=38123
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342548
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Roman Lebedev [Wed, 19 Sep 2018 13:35:40 +0000 (13:35 +0000)]
[InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanonical ((1 << y)+(-1)) mask
Summary:
Same as to D52146.
`((1 << y)+(-1))` is simply non-canoniacal version of `~(-1 << y)`: https://rise4fun.com/Alive/0vl
We can not canonicalize it due to the extra uses. But we can handle it here.
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342547
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Roman Lebedev [Wed, 19 Sep 2018 13:35:27 +0000 (13:35 +0000)]
[InstCombine] foldICmpWithLowBitMaskedVal(): handle ~(-1 << y) mask
Summary:
Two folds are happening here:
1. https://rise4fun.com/Alive/oaFX
2. And then `foldICmpWithHighBitMask()` (D52001): https://rise4fun.com/Alive/wsP4
This change doesn't just add the handling for eq/ne predicates,
it actually builds upon the previous `foldICmpWithLowBitMaskedVal()` work,
so **all** the 16 fold variants* are immediately supported.
I'm indeed only testing these two predicates.
I do not feel like re-proving all 16 folds*, because they were already proven
for the general case of constant with all-ones in low bits. So as long as
the mask produces all-ones in low bits, i'm pretty sure the fold is valid.
But required, i can re-prove, let me know.
* eq/ne are commutative - 4 folds; ult/ule/ugt/uge - are not commutative (the commuted variant is InstSimplified), 4 folds; slt/sle/sgt/sge are not commutative - 4 folds. 12 folds in total.
https://bugs.llvm.org/show_bug.cgi?id=38123
https://bugs.llvm.org/show_bug.cgi?id=38708
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342546
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Oliver Stannard [Wed, 19 Sep 2018 13:25:31 +0000 (13:25 +0000)]
[ARM] Fix unwind information for floating point registers
Fixes the unwind information generated for floating-point registers.
Previously, all padding registers were assumed to be four bytes wide. Now, the
width of the register is used to specify the amount of padding.
Patch by Jackson Woodruff!
Differential revision: https://reviews.llvm.org/D51494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342545
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Fedor Sergeev [Wed, 19 Sep 2018 12:25:52 +0000 (12:25 +0000)]
[New PM] Introducing PassInstrumentation framework
Summary:
Pass Execution Instrumentation interface enables customizable instrumentation
of pass execution, as per "RFC: Pass Execution Instrumentation interface"
posted 06/07/2018 on llvm-dev@
The intent is to provide a common machinery to implement all
the pass-execution-debugging features like print-before/after,
opt-bisect, time-passes etc.
Here we get a basic implementation consisting of:
* PassInstrumentationCallbacks class that handles registration of callbacks
and access to them.
* PassInstrumentation class that handles instrumentation-point interfaces
that call into PassInstrumentationCallbacks.
* Callbacks accept StringRef which is just a name of the Pass right now.
There were some ideas to pass an opaque wrapper for the pointer to pass instance,
however it appears that pointer does not actually identify the instance
(adaptors and managers might have the same address with the pass they govern).
Hence it was decided to go simple for now and then later decide on what the proper
mental model of identifying a "pass in a phase of pipeline" is.
* Callbacks accept llvm::Any serving as a wrapper for const IRUnit*, to remove direct dependencies
on different IRUnits (e.g. Analyses).
* PassInstrumentationAnalysis analysis is explicitly requested from PassManager through
usual AnalysisManager::getResult. All pass managers were updated to run that
to get PassInstrumentation object for instrumentation calls.
* Using tuples/index_sequence getAnalysisResult helper to extract generic AnalysisManager's extra
args out of a generic PassManager's extra args. This is the only way I was able to explicitly
run getResult for PassInstrumentationAnalysis out of a generic code like PassManager::run or
RepeatedPass::run.
TODO: Upon lengthy discussions we agreed to accept this as an initial implementation
and then get rid of getAnalysisResult by improving RepeatedPass implementation.
* PassBuilder takes PassInstrumentationCallbacks object to pass it further into
PassInstrumentationAnalysis. Callbacks registration should be performed directly
through PassInstrumentationCallbacks.
* new-pm tests updated to account for PassInstrumentationAnalysis being run
* Added PassInstrumentation tests to PassBuilderCallbacks unit tests.
Other unit tests updated with registration of the now-required PassInstrumentationAnalysis.
Reviewers: chandlerc, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D47858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342544
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Simon Pilgrim [Wed, 19 Sep 2018 12:23:50 +0000 (12:23 +0000)]
[TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::set() where possible. NFCI.
In these cases we are always setting to true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342543
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Benjamin Kramer [Wed, 19 Sep 2018 12:01:38 +0000 (12:01 +0000)]
[InstCombine] Don't transform sin/cos -> tanl if for half types
This is still unsafe for long double, we will transform things into tanl
even if tanl is for another type. But that's for someone else to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342542
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Calixte Denizet [Wed, 19 Sep 2018 11:26:20 +0000 (11:26 +0000)]
Verify commit access in fixing typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342538
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Simon Pilgrim [Wed, 19 Sep 2018 11:18:49 +0000 (11:18 +0000)]
[TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::push_back()
As mentioned on D52236, this saves 10secs in debug builds of x86 -gen-dag-isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342536
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Simon Pilgrim [Wed, 19 Sep 2018 11:08:54 +0000 (11:08 +0000)]
[ADT][BitVector] Add push_back()
Add a higher performance alternative to calling resize() every time which performs a lot of clearing to zero - when we're adding a single bit most of the time this will be completely unnecessary.
Differential Revision: https://reviews.llvm.org/D52236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342535
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Alex Bradbury [Wed, 19 Sep 2018 10:54:22 +0000 (10:54 +0000)]
[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A
Introduce a new RISCVExpandPseudoInsts pass to expand atomic
pseudo-instructions after register allocation. This is necessary in order to
ensure that register spills aren't introduced between LL and SC, thus breaking
the forward progress guarantee for the operation. AArch64 does something
similar for CmpXchg (though only at O0), and Mips is moving towards this
approach (see D31287). See also [this mailing list
post](http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) from
James Knight, which summarises the issues with lowering to ll/sc in IR or
pre-RA.
See the [accompanying RFC
thread](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html) for an
overview of the lowering strategy.
Differential Revision: https://reviews.llvm.org/D47882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342534
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Hans Wennborg [Wed, 19 Sep 2018 09:58:30 +0000 (09:58 +0000)]
[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables
The 0x800 bit in @feat.00 needs to be set in order to make LLD pick up
the .gfid$y table. I believe this is fine to set even if we don't emit
the instrumentation.
We haven't emitted @feat.00 on 64-bit before. I see that MSVC does emit
it, but I'm not entirely sure what the default value should be. I went
with zero since that seems as safe as not emitting the symbol in the
first place.
Differential Revision: https://reviews.llvm.org/D52235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342532
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Simon Pilgrim [Wed, 19 Sep 2018 09:50:32 +0000 (09:50 +0000)]
[X86][SSE] Update extractelement test in preparation for D52140
SimplifyDemandedVectorEltsForTargetNode will remove most of this test unless get rid of the undefs - still testing for align 1 which was the point of the test
Removed out of date comment as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342531
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Carlos Alberto Enciso [Wed, 19 Sep 2018 08:16:56 +0000 (08:16 +0000)]
[DebugInfo][Dexter] Speculated BB presents illegal variable value to debugger.
When SimplifyCFG changes the PHI node into a select instruction, the debug information becomes ambiguous. It causes the debugger to display wrong variable value.
Differential Revision: https://reviews.llvm.org/D51976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342527
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Jonas Devlieghere [Wed, 19 Sep 2018 08:08:13 +0000 (08:08 +0000)]
[DWARF Verifier] Add helper function to dump DIEs. [NFC]
It's pretty common for the verifier to dump the relevant DIE when it
finds an issue. This tends to be relatively verbose and error prone
because we have to pass the DIDumpOptions to the DIE's dump method. This
patch adds a helper function to the verifier to make this easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342526
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Thomas Lively [Wed, 19 Sep 2018 00:54:20 +0000 (00:54 +0000)]
[WebAssembly][NFC] Remove extra space in WebAssemblyInstrSIMD.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342522
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Matthias Braun [Wed, 19 Sep 2018 00:23:37 +0000 (00:23 +0000)]
AArch64MacroFusion: Factor out some opcode handling code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342521
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Matthias Braun [Wed, 19 Sep 2018 00:23:35 +0000 (00:23 +0000)]
ScheduleDAG: Cleanup dumping code; NFC
- Instead of having both `SUnit::dump(ScheduleDAG*)` and
`ScheduleDAG::dumpNode(ScheduleDAG*)`, just keep the latter around.
- Add `ScheduleDAG::dump()` and avoid code duplication in several
places. Implement it for different ScheduleDAG variants.
- Add `ScheduleDAG::dumpNodeName()` in favor of the `SUnit::print()`
functions. They were only ever used for debug dumping and putting the
function into ScheduleDAG is consistent with the `dumpNode()` change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342520
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Dean Michael Berris [Tue, 18 Sep 2018 23:59:32 +0000 (23:59 +0000)]
[XRay][compiler-rt] FDRLogWriter Abstraction
Summary:
This change introduces an `FDRLogWriter` type which is responsible for
serialising metadata and function records to character buffers. This is
the first step in a refactoring of the implementation of the FDR runtime
to allow for more granular testing of the individual components of the
implementation.
The main contribution of this change is a means of hiding the details of
how specific records are written to a buffer, and for managing the
extents of these buffers. We make use of C++ features (templates and
some metaprogramming) to reduce repetition in the act of writing out
specific kinds of records to the buffer.
In this process, we make a number of changes across both LLVM and
compiler-rt to allow us to use the `Trace` abstraction defined in the
LLVM project in the testing of the runtime implementation. This gives us
a closer end-to-end test which version-locks the runtime implementation
with the loading implementation in LLVM.
We also allow using gmock in compiler-rt unit tests, by adding the
requisite definitions in the `AddCompilerRT.cmake` module.
Finally, we've gone ahead and updated the FDR logging implementation to
use the FDRLogWriter for the lowest-level record-writing details.
Following patches will isolate the state machine transitions which
manage the set-up and tear-down of the buffers we're using in multiple
threads.
Reviewers: mboerger, eizan
Subscribers: mgorny, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342518
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Thomas Lively [Tue, 18 Sep 2018 21:45:12 +0000 (21:45 +0000)]
[WebAssembly] v4f32.abs and v2f64.abs
Summary: implement lowering of @llvm.fabs for vector types.
Reviewers: aheejin, dschuff
Subscribers:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342513
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Douglas Yung [Tue, 18 Sep 2018 19:34:05 +0000 (19:34 +0000)]
Revert r342494 as it was failing on a bot and the author cannot look at it until tomorrow.
Failing bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/36708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342509
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Martin Storsjo [Tue, 18 Sep 2018 19:31:09 +0000 (19:31 +0000)]
[benchmark] Mention another cherry-picked change in README.LLVM. NFC.
This was cherry-picked in SVN r342450.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342506
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Don Hinton [Tue, 18 Sep 2018 18:39:27 +0000 (18:39 +0000)]
[bugpoint] Revert r318459
Summary: Revert r318459 which introduced a TempFile scoping bug.
Differential Revision: https://reviews.llvm.org/D51836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342503
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Kristina Brooks [Tue, 18 Sep 2018 18:37:16 +0000 (18:37 +0000)]
Remove svn:executable from a documentation file.
Should fix the buildbot failure caused by it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342502
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Kristina Brooks [Tue, 18 Sep 2018 18:05:38 +0000 (18:05 +0000)]
[Docs] [Support] System Library to Support Library transition along with minor corrections to reflect it.
System Library has been a long deprecated term along with the path lib/System, having been superseded/renamed
to the Support Library a long time ago. These patches reflect those changes in documentation as well as
update some outdated examples and provide context to the origin of the Support Library.
Differential Revision: https://reviews.llvm.org/D52107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342500
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Christy Lee [Tue, 18 Sep 2018 17:02:42 +0000 (17:02 +0000)]
Do not optimize atomic load to non-atomic memcmp
Differential Revision: https://reviews.llvm.org/D51998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342498
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Farhana Aleen [Tue, 18 Sep 2018 16:59:48 +0000 (16:59 +0000)]
[AMDGPU] Match udot8 pattern
Summary: D.u32 = S0.u4[0] * S1.u4[0] +
S0.u4[1] * S1.u4[1] +
S0.u4[2] * S1.u4[2] +
S0.u4[3] * S1.u4[3] +
S0.u4[4] * S1.u4[4] +
S0.u4[5] * S1.u4[5] +
S0.u4[6] * S1.u4[6] +
S0.u4[7] * S1.u4[7] +
S2.u32
Author: FarhanaAleen
Reviewed By: arsenm, nhaehnle
Differential Revision: https://reviews.llvm.org/D51947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342497
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Zachary Turner [Tue, 18 Sep 2018 16:58:17 +0000 (16:58 +0000)]
Fix function signature to actually be an override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342496
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Hiroshi Yamauchi [Tue, 18 Sep 2018 16:50:10 +0000 (16:50 +0000)]
[PGO][CHR] Add opt remarks.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342495
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Christy Lee [Tue, 18 Sep 2018 16:43:44 +0000 (16:43 +0000)]
Check lines before using alias analysis to check for interference
This diff is to show the difference before and after D51550
Differential Revision: https://reviews.llvm.org/D52044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342494
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Zachary Turner [Tue, 18 Sep 2018 16:35:05 +0000 (16:35 +0000)]
[PDB] Better support for enumerating pointer types.
There were several issues with the previous implementation.
1) There were no tests.
2) We didn't support creating PDBSymbolTypePointer records for
builtin types since those aren't described by LF_POINTER
records.
3) We didn't support a wide enough variety of builtin types even
ignoring pointers.
This patch fixes all of these issues. In order to add tests,
it's helpful to be able to ignore the symbol index id hierarchy
because it makes the golden output from the DIA version not match
our output, so I've extended the dumper to disable dumping of id
fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342493
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Krzysztof Parzyszek [Tue, 18 Sep 2018 16:10:51 +0000 (16:10 +0000)]
[PostRASink] Make sure to remove subregisters from live-ins as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342492
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Jinsong Ji [Tue, 18 Sep 2018 15:38:56 +0000 (15:38 +0000)]
[NFC] Update comments regarding BufferSize for ProcResources
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342491
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Simon Pilgrim [Tue, 18 Sep 2018 15:38:16 +0000 (15:38 +0000)]
Revert rL342465: Added function to set a register to a particular value + tests.
rL342465 is breaking the MSVC buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342490
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Simon Pilgrim [Tue, 18 Sep 2018 15:35:49 +0000 (15:35 +0000)]
Revert rL342466: [llvm-exegesis] Improve Register Setup.
rL342465 is breaking the MSVC buildbots, but I need to revert this dependent revision as well.
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D51856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342489
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Alex Bradbury [Tue, 18 Sep 2018 15:18:16 +0000 (15:18 +0000)]
[RISCV][MC] Use a custom ParserMethod for the bare_symbol operand type
This allows the hard-coded shouldForceImmediate logic to be removed because
the generated MatchOperandParserImpl makes use of the current context (i.e.
the current mnemonic) to determine parsing behaviour, and so won't first try
to parse a register before parsing a symbol name.
No functional change is intended. gas accepts immediate arguments for call,
tail and lla. This patch doesn't address this discrepancy.
Differential Revision: https://reviews.llvm.org/D51733
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342488
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Alex Bradbury [Tue, 18 Sep 2018 15:13:29 +0000 (15:13 +0000)]
[RISCV][MC] Reject bare symbols for the simm12 operand type
addi a0, a0, foo and lw a0, foo(a0) and similar are now rejected. An explicit
%lo and %pcrel_lo modifier is required. This matches gas behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342487
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Alex Bradbury [Tue, 18 Sep 2018 15:08:35 +0000 (15:08 +0000)]
[RISCV][MC] Tighten up checking of sybol operands to lui and auipc
Reject bare symbols and accept only %pcrel_hi(sym) for auipc and %hi(sym) for
lui. Also test valid operand modifiers in rv32i-valid.s.
Note this is slightly stricter than gas, which will accept either %pcrel_hi or
%hi for both lui and auipc.
Differential Revision: https://reviews.llvm.org/D51731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342486
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Nico Weber [Tue, 18 Sep 2018 15:06:16 +0000 (15:06 +0000)]
Remove dead function user_cache_directory()
It's been unused since it was added almost 3 years ago in
https://reviews.llvm.org/D13801
Motivated by https://reviews.llvm.org/rL342002 since it removes one of the
functions keeping a ref to SHGetKnownFolderPath.
Differential Revision: https://reviews.llvm.org/D52184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342485
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Andrea Di Biagio [Tue, 18 Sep 2018 15:00:06 +0000 (15:00 +0000)]
[llvm-mca] Add the ability to mark register reads/writes associated with dep-breaking instructions. NFCI
This patch adds two new boolean fields:
- Field `ReadState::IndependentFromDef`.
- Field `WriteState::WritesZero`.
Field `IndependentFromDef` is set for ReadState objects associated with
dependency-breaking instructions. It is used by the simulator when updating data
dependencies between registers.
Field `WritesZero` is set by WriteState objects associated with dependency
breaking zero-idiom instructions. It helps the PRF identify which writes don't
consume any physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342483
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Hans Wennborg [Tue, 18 Sep 2018 14:12:54 +0000 (14:12 +0000)]
Revert r342457 "Fixes removal of dead elements from PressureDiff (PR37252)."
This broke the lit tests on a bunch of buildbots, e.g.
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/36679
> Reviewed By: MatzeB
>
> Differential Revision: https://reviews.llvm.org/D51495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342482
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Simon Pilgrim [Tue, 18 Sep 2018 14:05:07 +0000 (14:05 +0000)]
Use pass-by-reference for-range loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342481
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Andrea Di Biagio [Tue, 18 Sep 2018 14:03:46 +0000 (14:03 +0000)]
[llvm-mca] Slightly refactor class InstRef. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342480
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Teresa Johnson [Tue, 18 Sep 2018 13:44:13 +0000 (13:44 +0000)]
[ThinLTO] Update LangRef doc for summary parsing
Summary:
Remove note about summary being ignored. Update to reflect the
fact that summary is now parsed by llvm-as.
While here, fix one summary format that changed since the initial
implementation.
Reviewers: dexonsmith
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D51540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342479
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Nemanja Ivanovic [Tue, 18 Sep 2018 13:43:16 +0000 (13:43 +0000)]
[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
This is a follow-up to the previous patch that eliminated some of the rotates.
With this addition, we will also emit the record-form andis.
This patch increases the number of record-form rotates we eliminate by
more than 70%.
Differential revision: https://reviews.llvm.org/D44897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342478
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Teresa Johnson [Tue, 18 Sep 2018 13:42:24 +0000 (13:42 +0000)]
[LTO] Make detection of WPD remark enablement more robust
Summary:
Currently only the first function in the module is checked to
see if it has remarks enabled. If that first function is a declaration,
remarks will be incorrectly skipped. Change to look for the first
non-empty function.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342477
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whitequark [Tue, 18 Sep 2018 13:36:03 +0000 (13:36 +0000)]
[LLVM-C][OCaml] Add UnifyFunctionExitNodes pass to C and OCaml APIs
Summary:
Adds LLVMAddUnifyFunctionExitNodesPass to expose
createUnifyFunctionExitNodesPass to the C and OCaml APIs.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342476
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whitequark [Tue, 18 Sep 2018 13:35:50 +0000 (13:35 +0000)]
[LLVM-C][OCaml] Add LowerAtomic pass to C and OCaml APIs
Summary:
Adds LLVMAddLowerAtomicPass to expose createLowerAtomicPass in the C
and OCaml APIs.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342475
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whitequark [Tue, 18 Sep 2018 13:35:39 +0000 (13:35 +0000)]
[OCaml] Add OCaml API for LLVMGetIndices
Summary:
This patch adds a thin wrapper around LLVMGetNumIndices and
LLVMGetIndices to return the indices of ExtractValue or InsertValue
instructions as an OCaml array. It has not seemed to be necessary to
expose LLVMGetNumIndices separately.
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342474
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Nemanja Ivanovic [Tue, 18 Sep 2018 13:21:58 +0000 (13:21 +0000)]
[PowerPC] Optimize compares fed by ANDISo
Both ANDIo and ANDISo (and the 64-bit versions) are record-form instructions.
When optimizing compares, we handle the former in order to eliminate the compare
instruction but not the latter. This patch just adds the latter to the set of
instructions we optimize.
The reason these instructions need to be handled separately is that they are not
part of the RecFormRel map (since they don't have a non-record-form). The
missing "and-immediate-shifted" is just an oversight in the initial
implementation.
Differential revision: https://reviews.llvm.org/D51353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342472
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John Brawn [Tue, 18 Sep 2018 13:18:21 +0000 (13:18 +0000)]
[TargetLowering] Android has sincos functions
Since Android API version 9 the Android libm has had the sincos functions, so
they should be recognised as libcalls and sincos optimisation should be applied.
Differential Revision: https://reviews.llvm.org/D52025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342471
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Simon Pilgrim [Tue, 18 Sep 2018 12:01:25 +0000 (12:01 +0000)]
Fix signed/unsigned comparison warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342469
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Simon Pilgrim [Tue, 18 Sep 2018 11:30:30 +0000 (11:30 +0000)]
[TableGen] CodeGenDAGPatterns::GenerateVariants - full caching of matching predicates
Further extension to D51035, this patch avoids all repeated predicates[] matching by caching as it collects the patterns that have multiple variants.
Saves around 25secs in debug builds of x86 -gen-dag-isel.
Differential Revision: https://reviews.llvm.org/D51839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342467
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Guillaume Chatelet [Tue, 18 Sep 2018 11:26:48 +0000 (11:26 +0000)]
[llvm-exegesis] Improve Register Setup.
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D51856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342466
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Guillaume Chatelet [Tue, 18 Sep 2018 11:26:35 +0000 (11:26 +0000)]
Added function to set a register to a particular value + tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342465
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Guillaume Chatelet [Tue, 18 Sep 2018 11:26:27 +0000 (11:26 +0000)]
Improve Register Setup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342464
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Alexander Kornienko [Tue, 18 Sep 2018 10:53:13 +0000 (10:53 +0000)]
Remove trailing whitespace introduced in r342440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342463
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Simon Pilgrim [Tue, 18 Sep 2018 10:44:44 +0000 (10:44 +0000)]
[X86][SSE] LowerShift - pull out repeated getTargetVShiftUniformOpcode calls. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342462
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David Carlier [Tue, 18 Sep 2018 10:31:10 +0000 (10:31 +0000)]
[Xray] llvm-xray fix possible segfault
top argument when superior to the instrumentated code list capacity can lead to a segfault.
Reviewers: dberris
Reviewed By: dberris
Differential Revision: https://reviews.llvm.org/D52224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342461
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Yury Gribov [Tue, 18 Sep 2018 09:53:42 +0000 (09:53 +0000)]
Fixes removal of dead elements from PressureDiff (PR37252).
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D51495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342457
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David Green [Tue, 18 Sep 2018 09:44:53 +0000 (09:44 +0000)]
[AArch64] Attempt to parse more operands as expressions
This tries to make use of evaluateAsRelocatable in AArch64AsmParser::classifySymbolRef
to parse more complex expressions as relocatable operands. It is hopefully better than
the existing code which only handles Symbol +- Constant.
This allows us to parse more complex adr/adrp, mov, ldr/str and add operands. It also
loosens the requirements on parsing addends in ld/st and mov's and adds a number of
tests.
Differential Revision: https://reviews.llvm.org/D51792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342455
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Martin Storsjo [Tue, 18 Sep 2018 08:44:57 +0000 (08:44 +0000)]
[benchmark] Lowercase windows specific includes
The windows SDK headers don't have self-consistent casing anyway,
so we consistently use lowercase for these in other places, in order
to fix crosscompilation with mingw headers.
This applies an upstream commit:
https://github.com/google/benchmark/commit/
52613079824ac58d06c070aa9fbbb186a5859e2c
Differential Revision: https://reviews.llvm.org/D52181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342450
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Max Kazantsev [Tue, 18 Sep 2018 04:57:18 +0000 (04:57 +0000)]
[IndVars] Remove unreasonable checks in rewriteLoopExitValues
A piece of logic in rewriteLoopExitValues has a weird check on number of
users which allowed an unprofitable transform in case if an instruction has
more than 6 users.
Differential Revision: https://reviews.llvm.org/D51404
Reviewed By: etherzhhb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342444
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Matt Arsenault [Tue, 18 Sep 2018 02:34:54 +0000 (02:34 +0000)]
AMDGPU: Don't form fmed3 if it will require materialization
If there is a single use constant, it can be folded into the
min/max, but not into med3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342443
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Matt Arsenault [Tue, 18 Sep 2018 02:05:44 +0000 (02:05 +0000)]
LSV: Fix adjust alloca alignment trick for AMDGPU
This was checking the hardcoded address space 0 for the stack.
Additionally, this should be checking for legality with
the adjusted alignment, so defer the alignment check.
Also try to split if the unaligned access isn't allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342442
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QingShan Zhang [Tue, 18 Sep 2018 02:05:18 +0000 (02:05 +0000)]
[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8
When doing some instruction scheduling work, we noticed some missing itineraries.
Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling,
because we can still get same latency due to default values.
With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.
This will has impact on the count of RetiredMOps, affects the Pending/Available Queue,
then causing different scheduling or suboptimal scheduling further.
Patch By: jsji (Jinsong Ji)
Differential Revision: https://reviews.llvm.org/D52040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342441
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QingShan Zhang [Tue, 18 Sep 2018 01:59:22 +0000 (01:59 +0000)]
[PowerPC][NFC] Add a mulld testcase for scheduling check.
This patch add a mulld testcase for scheduling check.
Patch By: jsji (Jinsong Ji)
Differential Revision: https://reviews.llvm.org/D52039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342440
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Matt Arsenault [Tue, 18 Sep 2018 01:51:33 +0000 (01:51 +0000)]
AMDGPU: Expand vector canonicalizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342439
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whitequark [Tue, 18 Sep 2018 01:48:01 +0000 (01:48 +0000)]
[OCaml] Add OCaml API for LLVMIsCleanup
Summary: Expose test for whether or not a landingpad is a cleanup.
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342438
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whitequark [Tue, 18 Sep 2018 01:47:53 +0000 (01:47 +0000)]
[NFC][OCaml] Fix copy paste error in file header
Summary: Just copypasta resulting in the wrong file name in the header.
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342437
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