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Jason Ekstrand [Tue, 28 Jun 2016 21:38:54 +0000 (14:38 -0700)]
isl/state: Add an assertion for IVB multisample array textures
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 23:14:24 +0000 (16:14 -0700)]
isl: Add a #define for DEV_IS_BAYTRAIL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:34:02 +0000 (18:34 -0700)]
i965/blorp: Remove unused fields from blorp_surface_info
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces. Let's just have the one field for that.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:33:05 +0000 (18:33 -0700)]
i965/blorp: Simplify depth buffer state setup a bit
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:13:39 +0000 (17:13 -0700)]
i965/blorp: Use the generic surface state path for gen8 textures
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 15:43:27 +0000 (08:43 -0700)]
isl: Add asserts for gen8+ X/YOffset rules
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 18:54:14 +0000 (11:54 -0700)]
i965/blorp: Only do offset hacks for fake W-tiling and IMS
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces. This isn't really necessary since
we can just use the base level/layer provided in the surface state. While
it may have simplified blorp's original design, we haven't been using the
blorp path for surface state on gen8 thanks to render compression and
there's really no good need for it most of the time. This commit restricts
such surface munging to the cases of fake W-tiling and fake interleaved
multisampling.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:46:07 +0000 (14:46 -0700)]
i965/blorp: Add a z_offset field to blorp_surface_info
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:10:49 +0000 (14:10 -0700)]
i965/blorp: Pass the Z component into all texture operations
Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message. We may
as well just pass it through everything.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 02:30:32 +0000 (19:30 -0700)]
i965/blorp: Rework hiz rect alignment calculations
At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero. However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification. Also, we only need to align the surface dimensions in the
case where we are operating on miplevel 0. Previously, it didn't matter
because it aligned on miplevel 0 and, for all other miplevels, the miptree
code guaranteed that the level was already aligned.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:30:35 +0000 (17:30 -0700)]
i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9
The sampling hardware can handle them ok. It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one. The render
hardware isn't so smart.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 22:30:15 +0000 (15:30 -0700)]
i965/miptree: Fill out the isl_surf::usage field
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:25:59 +0000 (14:25 -0700)]
isl: Take the slice0_extent shortcut for interleaved MSAA
The shortcut works just fine for MSAA and the comment even says so.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:21:44 +0000 (14:21 -0700)]
isl: Remove duplicate px->sa conversions
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples. There is no
need to do the conversion and doing so gives us an incorrect value.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 16:05:46 +0000 (09:05 -0700)]
i965/blorp: Use the isl_view from the blorp_surface_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 17 Aug 2016 08:06:36 +0000 (01:06 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::width/height
Instead, we manually mutate the surface size as needed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:48:20 +0000 (20:48 -0700)]
i965/blorp: Move surface offset calculations into a helper
The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:57:41 +0000 (20:57 -0700)]
i965/blorp: Use ISL to compute image offsets
For the moment, we still call the old miptree function; we just assert that
the two are equal.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 22:00:31 +0000 (15:00 -0700)]
isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 04:50:22 +0000 (21:50 -0700)]
isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer. While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:11:46 +0000 (20:11 -0700)]
i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state. For now, we just use it for the format and the
swizzle.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 01:40:08 +0000 (18:40 -0700)]
i965/blorp: Move intratile offset calculations out of surface state setup
Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that. Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 00:06:37 +0000 (17:06 -0700)]
i965/blorp: Refactor interleaved multisample destination handling
We put all of the code for fake IMS together. This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 23:27:17 +0000 (16:27 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::array_layout
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:50:18 +0000 (15:50 -0700)]
i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
We also remove brw_blorp_surface_info::msaa_layout.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:17:15 +0000 (15:17 -0700)]
i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 18:00:59 +0000 (11:00 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::num_samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 18:35:50 +0000 (11:35 -0700)]
i965/blorp: Make sample count asserts a bit more lazy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:46:20 +0000 (16:46 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:41:58 +0000 (16:41 -0700)]
i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 22:33:44 +0000 (15:33 -0700)]
i965/blorp: Create the isl_surf up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:32:57 +0000 (15:32 -0700)]
i965/blorp/clear: Initialize surface info after allocating an MCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:20:15 +0000 (14:20 -0700)]
isl/state: Use a valid alignment for 1-D textures
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:13:42 +0000 (16:13 -0700)]
i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks
It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:37:54 +0000 (16:37 -0700)]
isl: Fix the parameter names for get_intratile_offset
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Brian Paul [Wed, 17 Aug 2016 16:41:30 +0000 (10:41 -0600)]
util: try to use SSE instructions with MSVC and 32-bit gcc
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient. This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.
Note, this patch doesn't address the use of SSE4.1 with MSVC.
v2: get rid of the ROUND_WITH_SSE symbol, per Matt.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Wed, 17 Aug 2016 14:31:20 +0000 (08:31 -0600)]
svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()
The function was always returning false because of this typo.
Retested with piglit. There's some sRGB-related blit failures, but
that seems unrelated.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Brian Paul [Wed, 17 Aug 2016 14:20:33 +0000 (08:20 -0600)]
svga: initialize a variable to silence a gcc warning
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Ian Romanick [Wed, 15 Apr 2015 23:43:20 +0000 (16:43 -0700)]
glsl: Pull enum ir_expression_operation out to its own file
No change except to the copyright symbol. The next patch will generate
this file with Python, and Unicode + Python = pure rage.
v2: Massive rebase... I guess a lot can change in a year.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 14 Jul 2016 01:02:10 +0000 (18:02 -0700)]
glsl: Make the generated sources build rules more like NIR
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francesco Ansanelli [Tue, 16 Aug 2016 12:38:46 +0000 (14:38 +0200)]
mesa/st: use llabs instead of abs for long args (v2)
v2: long has 32bit on Windows (Marek)
Signed-off-by: Francesco Ansanelli <francians@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Fri, 12 Aug 2016 11:00:58 +0000 (13:00 +0200)]
radeonsi: fix up buffer descriptor upper-bound checking
st/mesa does this too, so we're safe.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 12 Aug 2016 00:33:41 +0000 (02:33 +0200)]
gallium: change pipe_image_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.
Example: Bind RGBA32F with offset = 4 bytes.
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 12 Aug 2016 00:33:41 +0000 (02:33 +0200)]
gallium: change pipe_sampler_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.
Example: Bind RGBA32F with offset = 4 bytes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:11:34 +0000 (22:11 +0200)]
gallium/radeon: assign the highest priority to scratch; make rings second
just FYI, the kernel receives priority/4
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:08:51 +0000 (22:08 +0200)]
gallium/winsys: re-number winsys priority flags
free 60..63, move CP_DMA up
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:00:49 +0000 (22:00 +0200)]
gallium/radeon: mark shader rings as highest-priority buffers
and rename the enum
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 19:50:55 +0000 (21:50 +0200)]
gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffers
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 15:56:44 +0000 (17:56 +0200)]
radeonsi: use current context for DCC feedback-loop decompress, fixes Elemental
This is just a workaround. The problem is described in the code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541
v2: say that it's only between the current context and aux_context
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Wed, 10 Aug 2016 10:43:45 +0000 (12:43 +0200)]
radeonsi: simplify CB_TARGET_MASK logic
we can now rely on CB_COLORn_INFO to disable empty slots.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Aug 2016 10:21:53 +0000 (12:21 +0200)]
radeonsi: don't set CB_COLOR1_INFO for dual src blending
Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT
from NI was moved to SPI_SHADER_COL_FORMAT for SI.
I asked CB guys about this 2 days ago and they still haven't replied.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Aug 2016 10:19:49 +0000 (12:19 +0200)]
radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound
All VP DX9 ports benefit from this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 9 Aug 2016 21:37:04 +0000 (23:37 +0200)]
gallium/radeon: use unflushed fences for PIPE_QUERY_GPU_FINISHED
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:26:37 +0000 (12:26 +0200)]
gallium/radeon: use lp_build_alloca_undef
Avoid building all those store 0 / store undef instruction pairs that
end up getting removed anyway.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:25:43 +0000 (12:25 +0200)]
gallivm: add lp_build_alloca_undef
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:23:41 +0000 (12:23 +0200)]
gallivm: add create_builder_at_entry helper function
Reduces code duplication.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:52:54 +0000 (23:52 +0200)]
gallium/radeon: protect against out of bounds temporary array accesses
They can lead to VM faults and worse, which goes against the GL robustness
promises.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:52:06 +0000 (23:52 +0200)]
gallium/radeon: add radeon_llvm_bound_index for bounds checking
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:31:02 +0000 (22:31 +0200)]
gallium/radeon: reduce alloca of temporaries based on usagemask
v2: take actual writemasks into account
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 10 Aug 2016 16:50:24 +0000 (18:50 +0200)]
gallium/radeon: use tgsi_scan_arrays for temp arrays
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 10 Aug 2016 16:41:21 +0000 (18:41 +0200)]
gallium/radeon: allocate temps array info in radeon_llvm_context_init
Also, prepare for using tgsi_array_info.
This also opens the door for properly handling allocation failures, but I'm
leaving that for a separate change.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:20:45 +0000 (23:20 +0200)]
gallium/radeon: always do the full store in store_value_to_array
Doing the write-back of the temporary vector in radeon_llvm_emit_store makes
no sense.
This also allows us to get rid of get_alloca_for_array.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:13:44 +0000 (23:13 +0200)]
gallium/radeon: extract common getelementptr logic into get_pointer_into_array
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:50:05 +0000 (22:50 +0200)]
gallium/radeon: pass indirect register info into get_alloca_for_array
To have the same signature as get_array_range.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:43:09 +0000 (22:43 +0200)]
gallium/radeon: extract common lookup code into get_temp_array function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:15:04 +0000 (22:15 +0200)]
gallium/radeon: clarify the comment on the array alloca heuristic
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 19:55:47 +0000 (21:55 +0200)]
gallium/radeon: more descriptive names for LLVM temporaries in debug builds
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 17:54:53 +0000 (19:54 +0200)]
gallium/radeon: simplify radeon_llvm_emit_store for direct array addressing
We can use the pointer stored in the temps array directly.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 17:52:46 +0000 (19:52 +0200)]
gallium/radeon: simplify radeon_llvm_emit_fetch for direct array addressing
We can use the pointer stored in the temps array directly.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 17:50:52 +0000 (19:50 +0200)]
gallium/radeon: clean up emit_declaration for temporaries
In the alloca'd array case, no longer create redundant and unused allocas
for the individual elements; create getelementptrs instead.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 18:41:04 +0000 (20:41 +0200)]
st_glsl_to_tgsi: use calloc the way it's meant to be used
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 10 Aug 2016 16:05:13 +0000 (18:05 +0200)]
tgsi/scan: add tgsi_scan_arrays
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ian Romanick [Tue, 12 Jul 2016 23:23:27 +0000 (16:23 -0700)]
glsl: Add missing ir_quadop_vector constant evaluation for Boolean types
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 13 Jul 2016 00:06:34 +0000 (17:06 -0700)]
glsl: Fix typo in ir_unop_f2u implementation
This won't affect the output, but it was, technically, wrong.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 11 Jul 2016 22:38:00 +0000 (15:38 -0700)]
glsl: Fix typo in ir_unop_b2i implementation
This won't affect the output, but it was, technically, wrong.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Sat, 9 Jul 2016 00:39:48 +0000 (17:39 -0700)]
glsl: Don't support integer types for operations that can't handle them
ir_unop_fract already forbade integer types in ir_validate. ir_unop_rcp,
ir_unop_rsq, and ir_unop_sqrt should also forbid them in ir_validate.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Sat, 9 Jul 2016 00:34:53 +0000 (17:34 -0700)]
glsl: Don't support ir_unop_abs or ir_unop_sign for unsigned integers
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 20 Jul 2016 00:47:38 +0000 (17:47 -0700)]
nir/algebraic: Optimize common array indexing sequence
Some shaders include code that looks like:
uniform int i;
uniform vec4 bones[...];
foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]);
CSE would do some work on this:
x = i * 3
foo(bones[x], bones[x + 1], bones[x + 2]);
The compiler may then add '<< 4 + base' to the index calculations.
This results in expressions like
x = i * 3
foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]);
Just rearranging the math to produce (i * 48) + 16 saves an
instruction, and it allows CSE to do more work.
x = i * 48;
foo(bones[x], bones[x + 16], bones[x + 32]);
So, ~6 instructions becomes ~3.
Some individual shader-db results look pretty bad. However, I have a
really, really hard time believing the change in estimated cycles in,
for example, 3dmmes-taiji/51.shader_test after looking that change in
the generated code.
G45
total instructions in shared programs:
4020840 ->
4010070 (-0.27%)
instructions in affected programs: 177460 -> 166690 (-6.07%)
helped: 894
HURT: 0
total cycles in shared programs:
98829000 ->
98784990 (-0.04%)
cycles in affected programs:
3936648 ->
3892638 (-1.12%)
helped: 894
HURT: 0
Ironlake
total instructions in shared programs:
6418887 ->
6408117 (-0.17%)
instructions in affected programs: 177460 -> 166690 (-6.07%)
helped: 894
HURT: 0
total cycles in shared programs:
143504542 ->
143460532 (-0.03%)
cycles in affected programs:
3936648 ->
3892638 (-1.12%)
helped: 894
HURT: 0
Sandy Bridge
total instructions in shared programs:
8357887 ->
8339251 (-0.22%)
instructions in affected programs: 432715 -> 414079 (-4.31%)
helped: 2795
HURT: 0
total cycles in shared programs:
118284184 ->
118207412 (-0.06%)
cycles in affected programs:
6114626 ->
6037854 (-1.26%)
helped: 2478
HURT: 317
Ivy Bridge
total instructions in shared programs:
7669390 ->
7653822 (-0.20%)
instructions in affected programs: 388234 -> 372666 (-4.01%)
helped: 2795
HURT: 0
total cycles in shared programs:
68381982 ->
68263684 (-0.17%)
cycles in affected programs:
1972658 ->
1854360 (-6.00%)
helped: 2458
HURT: 307
Haswell
total instructions in shared programs:
7082636 ->
7067068 (-0.22%)
instructions in affected programs: 388234 -> 372666 (-4.01%)
helped: 2795
HURT: 0
total cycles in shared programs:
68282020 ->
68164158 (-0.17%)
cycles in affected programs:
1891820 ->
1773958 (-6.23%)
helped: 2459
HURT: 261
Broadwell
total instructions in shared programs:
9002466 ->
8985875 (-0.18%)
instructions in affected programs: 658784 -> 642193 (-2.52%)
helped: 2795
HURT: 5
total cycles in shared programs:
78503092 ->
78450404 (-0.07%)
cycles in affected programs:
2873304 ->
2820616 (-1.83%)
helped: 2275
HURT: 415
Skylake
total instructions in shared programs:
9156978 ->
9140387 (-0.18%)
instructions in affected programs: 682625 -> 666034 (-2.43%)
helped: 2795
HURT: 5
total cycles in shared programs:
75591392 ->
75550574 (-0.05%)
cycles in affected programs:
3192120 ->
3151302 (-1.28%)
helped: 2271
HURT: 425
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Michel Dänzer [Tue, 16 Aug 2016 06:35:44 +0000 (15:35 +0900)]
glx: Don't use current context in __glXSendError
There's no guarantee that there is one, and we don't need one anyway.
Fixes piglit tests:
glx@glx-fbconfig-bad
glx@glx_ext_import_context@import context, multi process
glx@glx_ext_import_context@import context, single process
Fixes:
2e3f067458e4 ("glx: fix error code when there is no context bound")
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ilia Mirkin [Sun, 14 Aug 2016 02:19:39 +0000 (22:19 -0400)]
nv50/ir: fix bb positions after exit instructions
It's fairly rare that the BB layout puts BBs after the exit block, which
is likely the reason these issues lingered for so long.
This fixes a fraction of issues with the giant pixmark piano shader.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 13 Aug 2016 19:45:35 +0000 (15:45 -0400)]
nv50/ir: properly clear upper bits of a bitset fill
Found by inspection. In practice, val is always == 0, so this never got
triggered.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Fri, 12 Aug 2016 21:05:19 +0000 (14:05 -0700)]
i965/fs: Estimate maximum sampler message execution size more accurately.
The current logic used to determine the execution size of sampler
messages was based on special-casing several argument and opcode
combinations, which unsurprisingly missed the possibility that some
messages could exceed the payload size limit or not depending on the
number of coordinate components present. In particular:
- The TXL, TXB and TEX messages (the latter on non-FS stages only)
would attempt to use SIMD16 on Gen7+ hardware even if a shadow
reference was present and the texture was a cubemap array, causing
it to overflow the maximum supported sampler payload size and
crash.
- The TG4_OFFSET message with shadow comparison was falling back to
SIMD8 regardless of the number of coordinate components, which is
unnecessary when two coordinates or less are present.
Both cases have been handled incorrectly ever since cubemap arrays and
texture gather were respectively enabled (the current logic used by
the SIMD lowering pass is almost unchanged from the previous no16
fall-back logic used pre-SIMD lowering times).
Fixes the following GL4.5 conformance test on Gen7-8 (the bug also
affects Gen9+ in principle, but SKL passes the test by luck because it
manages to use the TXL_LZ message instead of TXL):
GL45-CTS.texture_cube_map_array.sampling
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97267
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Sat, 13 Aug 2016 01:33:58 +0000 (18:33 -0700)]
i965/fs: Return zero from fs_inst::components_read for non-present sources.
This makes it easier for the caller to find out how many scalar
components are actually read by the instruction. As a bonus we no
longer need to special-case BAD_FILE in the implementation of
fs_inst::regs_read.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 12 Aug 2016 18:38:29 +0000 (11:38 -0700)]
i965/fs: Lower TEX to TXL during NIR translation.
This simplifies the code slightly and will allow the SIMD lowering
pass to find out easily what the actual texturing opcode is in order
to determine the maximum execution size of texturing instructions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Tue, 16 Aug 2016 23:13:55 +0000 (19:13 -0400)]
freedreno/a3xx: fix generic clear path
Signed-off-by: Rob Clark <robdclark@gmail.com>
Brian Paul [Fri, 12 Aug 2016 18:37:02 +0000 (12:37 -0600)]
st/mesa: use pipe var instead of st->pipe in st_create_context_priv()
As is done in most other places in the function.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Aug 2016 15:32:18 +0000 (09:32 -0600)]
gallium: remove unused u_clear.h file
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Aug 2016 15:30:51 +0000 (09:30 -0600)]
gallium/i915: inline the util_clear() code into i915_clear_blitter()
This is the only place the util_clear() function was used.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Aug 2016 15:16:39 +0000 (09:16 -0600)]
gallium/util: minor reformatting in u_box.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 16 Aug 2016 14:27:49 +0000 (08:27 -0600)]
svga: remove unused var in svga_mark_surfaces_dirty()
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Tue, 2 Aug 2016 20:30:41 +0000 (14:30 -0600)]
svga: avoid a calloc in svga_buffer_transfer_map()
Just initialize the two other pipe_transfer fields explicitly.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 2 Aug 2016 20:27:33 +0000 (14:27 -0600)]
svga: don't call os_get_time() when not needed by Gallium HUD
The calls to os_get_time() were showing up higher than expected in
profiles.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 1 Aug 2016 22:31:13 +0000 (16:31 -0600)]
svga: remove unneeded memset() call in draw_vgpu10()
All three fields of the vbuffer_attrs[] array are assigned in the following
loop. The remaining elements of the array are not used.
Tested with full Piglit run, Heaven 4.0, etc.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 1 Aug 2016 22:30:14 +0000 (16:30 -0600)]
svga: reduce looping in svga_mark_surfaces_dirty()
We don't need to loop over the max number of color buffers, just the
current number (which is usually one).
Tested with full Piglit run, Heaven 4.0, etc.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 29 Jul 2016 15:10:02 +0000 (09:10 -0600)]
svga: minor clean-ups in define_rasterizer_object()
Add const qualifiers, new comment.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 15 Aug 2016 22:33:16 +0000 (16:33 -0600)]
svga: remove incorrect buffer invalidation code
Fixes regression with team_fortress_2 trace.
This change has been in our in-house tree for some time.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 12 Aug 2016 19:13:22 +0000 (13:13 -0600)]
svga: additional comments for svga_hw_draw_state members
And re-order a few fields.
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 15 Aug 2016 17:38:39 +0000 (11:38 -0600)]
svga: use the sws local var to simplify some code
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 11 Aug 2016 15:52:31 +0000 (09:52 -0600)]
svga: minor whitespace and code clean-ups
Signed-off-by: Brian Paul <brianp@vmware.com>
Rob Clark [Thu, 11 Aug 2016 16:00:52 +0000 (12:00 -0400)]
freedreno/a4xx: use generic clear path
Signed-off-by: Rob Clark <robdclark@gmail.com>