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Eric Christopher [Mon, 27 Mar 2017 22:40:51 +0000 (22:40 +0000)]
Remove an oddly unnecessary temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298888
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Renato Golin [Mon, 27 Mar 2017 22:38:43 +0000 (22:38 +0000)]
[ARM] Mark falky test unsupported until we find the cause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298887
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Juergen Ributzka [Mon, 27 Mar 2017 22:33:05 +0000 (22:33 +0000)]
[libfuzzer] Remove XFAIL for OutOfMemory test.
This test is now passing on Darwin.
See rdar://problem/
31282257.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298886
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Javed Absar [Mon, 27 Mar 2017 20:46:37 +0000 (20:46 +0000)]
Improve machine schedulers for in-order processors
This patch enables schedulers to specify instructions that
cannot be issued with any other instructions.
It also fixes BeginGroup/EndGroup.
Reviewed by: Andrew Trick
Differential Revision: https://reviews.llvm.org/D30744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298885
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Kevin Enderby [Mon, 27 Mar 2017 20:09:23 +0000 (20:09 +0000)]
Add the error handling for Mach-O dyld compact lazy bind, weak bind and
rebase entry errors and test cases for each of the error checks.
Also verified with Nick Kledzik that a BIND_OPCODE_SET_ADDEND_SLEB
opcode is legal in a lazy bind table, so code that had that as an error
check was removed.
With MachORebaseEntry and MachOBindEntry classes now returning
an llvm::Error in all cases for malformed input the variables Malformed
and logic to set use them is no longer needed and has been removed
from those classes.
Also in a few places, removed the redundant Done assignment to true
when also calling moveToEnd() as it does that assignment.
This only leaves the dyld compact export entries left to have
error handling yet to be added for the dyld compact info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298883
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Matthew Simpson [Mon, 27 Mar 2017 20:07:38 +0000 (20:07 +0000)]
[LV] Transform truncations of non-primary induction variables
The vectorizer tries to replace truncations of induction variables with new
induction variables having the smaller type. After r295063, this optimization
was applied to all integer induction variables, including non-primary ones.
When optimizing the truncation of a non-primary induction variable, we still
need to transform the new induction so that it has the correct start value.
This should fix PR32419.
Reference: https://bugs.llvm.org/show_bug.cgi?id=32419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298882
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Craig Topper [Mon, 27 Mar 2017 20:07:31 +0000 (20:07 +0000)]
[APInt] Move operator=(uint64_t) inline as its pretty simple and is often used with small constants that the compiler can optimize.
While there recognize that we only need to clearUnusedBits on the single word case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298881
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Krzysztof Parzyszek [Mon, 27 Mar 2017 19:08:24 +0000 (19:08 +0000)]
[TableGen] Print #nnn as a name of an non-native reg unit with id nnn
When using -debug with -gen-register-info, tablegen will crash when
trying to print a name of a non-native register unit. This patch only
affects the debug information generated while running llvm-tblgen,
and has no impact on the compilable code coming out of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298875
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Valery Pykhtin [Mon, 27 Mar 2017 18:22:39 +0000 (18:22 +0000)]
[AMDGPU] SISched: Detect dependency types between blocks
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298872
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Bruno Cardoso Lopes [Mon, 27 Mar 2017 18:21:31 +0000 (18:21 +0000)]
[Support] Avoid concurrency hazard in signal handler registration
Several static functions from the signal API can be invoked
simultaneously; RemoveFileOnSignal for instance can be called indirectly
by multiple parallel loadModule() invocations, which might lead to
the assertion:
Assertion failed: (NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) && "Out of space for signal handlers!"),
function RegisterHandler, file /llvm/lib/Support/Unix/Signals.inc, line 105.
RemoveFileOnSignal calls RegisterHandlers(), which isn't currently
mutex protected, leading to the behavior above. This potentially affect
a few other users of RegisterHandlers() too.
rdar://problem/
30381224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298871
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Craig Topper [Mon, 27 Mar 2017 18:16:17 +0000 (18:16 +0000)]
[APInt] Move operator&=(uint64_t) inline and use memset to clear the upper words.
This method is pretty new and probably isn't use much in the code base so this should have a negligible size impact. The OR and XOR operators are already inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298870
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Ahmed Bougacha [Mon, 27 Mar 2017 18:14:20 +0000 (18:14 +0000)]
[GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.
r298863 used PtrReg, but that's never defined in release builds. Fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298869
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Craig Topper [Mon, 27 Mar 2017 17:50:54 +0000 (17:50 +0000)]
[APInt] Use memset in setAllBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298867
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Adrian Prantl [Mon, 27 Mar 2017 17:36:31 +0000 (17:36 +0000)]
Remove redundant check for nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298866
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Adrian Prantl [Mon, 27 Mar 2017 17:34:04 +0000 (17:34 +0000)]
Remove unneccessary virtual destructor from DwarfExpression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298865
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:56 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.
A majority of loads and stores at O0 access an alloca.
It's trivial to fold the G_FRAME_INDEX into the instruction; do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298864
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:52 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.
We're not to the point of supporting the load/store patterns yet
(because they extensively use PatFrags).
But in the meantime, we can implement some of the simplest addressing
modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298863
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Ahmed Bougacha [Mon, 27 Mar 2017 17:31:48 +0000 (17:31 +0000)]
[GlobalISel][AArch64] Select store of zero to WZR/XZR.
These occur very frequently, and are quite trivial to catch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298862
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Valery Pykhtin [Mon, 27 Mar 2017 17:26:40 +0000 (17:26 +0000)]
[AMDGPU] SISched: Update colorEndsAccordingToDependencies
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298861
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Craig Topper [Mon, 27 Mar 2017 17:10:21 +0000 (17:10 +0000)]
[APInt] Move the >64 bit case for flipAllBits out of line.
This is more consistent with what we do for other operations. This shrinks the opt binary on my build by ~72k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298858
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Valery Pykhtin [Mon, 27 Mar 2017 17:06:36 +0000 (17:06 +0000)]
[AMDGPU] Fix SI scheduler LiveOut Refcount issue
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298857
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:31 +0000 (16:35 +0000)]
[GlobalISel][AArch64] Select CBZ.
CBZ/CBNZ represent a substantial portion of all conditional branches.
Look through G_ICMP to select them.
We can't use tablegen yet because the existing patterns match an
AArch64ISD node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298856
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:27 +0000 (16:35 +0000)]
[GlobalISel] Add a 'getConstantVRegVal' helper.
Use it to compare immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298855
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Ahmed Bougacha [Mon, 27 Mar 2017 16:35:23 +0000 (16:35 +0000)]
[GlobalISel][AArch64] Use proper constant types in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298854
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Dmitry Preobrazhensky [Mon, 27 Mar 2017 15:57:17 +0000 (15:57 +0000)]
[AMDGPU][MC] Fix for Bug 28207 + LIT tests
Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type
Reviewers: vpykhtin, arsenm
Differential Revision: https://reviews.llvm.org/D31327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298852
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Chad Rosier [Mon, 27 Mar 2017 15:52:38 +0000 (15:52 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.
Among other things, this allows Machine LICM to hoist a costly 'mrs'
instruction from within a loop.
Differential Revision: http://reviews.llvm.org/D31151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298851
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Yaxun Liu [Mon, 27 Mar 2017 14:04:01 +0000 (14:04 +0000)]
[AMDGPU] Get address space mapping by target triple environment
As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.
The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.
Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.
Differential Revision: https://reviews.llvm.org/D31284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298846
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Anna Thomas [Mon, 27 Mar 2017 13:52:51 +0000 (13:52 +0000)]
[InstCombine] Avoid incorrect folding of select into phi nodes when incoming element is a vector type
Summary:
We are incorrectly folding selects into phi nodes when the incoming value of a phi
node is a constant vector. This optimization is done in `FoldOpIntoPhi` when the
select condition is a phi node with constant incoming values.
Without the fix, we are miscompiling (i.e. incorrectly folding the
select into the phi node) when the vector contains non-zero
elements.
This patch fixes the miscompile and we will correctly fold based on the
select vector operand (see added test cases).
Reviewers: majnemer, sanjoy, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298845
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Daniel Sanders [Mon, 27 Mar 2017 13:43:24 +0000 (13:43 +0000)]
Correct OptionCategoryCompare() in the command line library.
Summary:
It should return <0, 0, or >0 for less-than, equal, and greater-than like
strcmp() (according to the history, it used to be implemented with
strcmp()) but it actually returned 0, or 1 for not-equal and equal.
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D30996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298844
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Daniel Sanders [Mon, 27 Mar 2017 13:15:13 +0000 (13:15 +0000)]
[tablegen] Use categories on options that only matter to one emitter.
Summary:
The categories are emitted in a strange order in this patch due to a bug in the
CommandLine library.
Reviewers: ab
Reviewed By: ab
Subscribers: ab, llvm-commits
Differential Revision: https://reviews.llvm.org/D30995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298843
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Justin Bogner [Mon, 27 Mar 2017 12:56:12 +0000 (12:56 +0000)]
ADT: Add range helpers for pointer_ and pointee_iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298841
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Gadi Haber [Mon, 27 Mar 2017 12:13:37 +0000 (12:13 +0000)]
[X86][AVX2] bugzilla bug 21281 Performance regression in vector interleave in AVX2
This is a patch for an on-going bugzilla bug 21281 on the generated X86 code for a matrix transpose8x8 subroutine which requires vector interleaving. The generated code in AVX2 is currently non-optimal and requires 60 instructions as opposed to only 40 instructions generated for AVX1.
The patch includes a fix for the AVX2 case where vector unpack instructions use less operations than the vector blend operations available in AVX2.
In this case using vector unpack instructions is more efficient.
Reviewers:
zvi
delena
igorb
craig.topper
guyblank
eladcohen
m_zuckerman
aymanmus
RKSimon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298840
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Karl-Johan Karlsson [Mon, 27 Mar 2017 07:13:44 +0000 (07:13 +0000)]
[TableGen] Make CodeGenMapTable understand the namespace field of an instruction
Do not force the backends to use target name as namespace.
Original patch by Mattias Eriksson
Reviewers: stoklund, craig.topper
Reviewed By: stoklund
Subscribers: materi, llvm-commits
Differential Revision: https://reviews.llvm.org/D31322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298834
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Craig Topper [Mon, 27 Mar 2017 05:47:03 +0000 (05:47 +0000)]
[IR] Implement pairs of non-const and const methods using the const version instead of the non-const version. NFCI
This removes a const_cast of the this pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298831
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Craig Topper [Mon, 27 Mar 2017 05:46:58 +0000 (05:46 +0000)]
[IR] Share implementation for pairs of const and non-const methods using const_cast. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298830
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Craig Topper [Mon, 27 Mar 2017 02:38:17 +0000 (02:38 +0000)]
[IR] Share implementation of pairs of const and non-const methods in BasicBlock using the const version instead of the non-const version
Summary:
During post-commit review of a previous change I made it was pointed out that const casting 'this' is technically a bad practice. This patch re-implements all of the methods in BasicBlock that do this to use the const BasicBlock version and const_cast the return value instead.
I think there are still many other classes that do similar things. I may look at more in the future.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298827
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Craig Topper [Sun, 26 Mar 2017 23:23:29 +0000 (23:23 +0000)]
[IR] Make Instruction::isAssociative method inline. Add LLVM_READONLY to the static version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298826
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Davide Italiano [Sun, 26 Mar 2017 21:45:04 +0000 (21:45 +0000)]
[Target] Remove some code probably copy/pasted from another backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298825
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Davide Italiano [Sun, 26 Mar 2017 21:27:21 +0000 (21:27 +0000)]
[MachineScheduler] Reference the correct header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298823
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Sanjoy Das [Sun, 26 Mar 2017 20:56:25 +0000 (20:56 +0000)]
Fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298819
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Simon Pilgrim [Sun, 26 Mar 2017 17:39:41 +0000 (17:39 +0000)]
Fix signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298813
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Shoaib Meenai [Sun, 26 Mar 2017 17:10:11 +0000 (17:10 +0000)]
[llvm-readobj] Prefer ILT to IAT for reading COFF imports
We're seeing binutils ld produce binaries where the import address
table's NameRVA entry is actually a VA instead (i.e. it's already base
relocated), which llvm-readobj then chokes on. Both dumpbin and the
Windows loader are able to handle these binaries correctly, however, and
we can make llvm-readobj handle them correctly too by iterating the
import lookup table (which doesn't have a relocated NameRVA) rather than
the import address table.
The import lookup table and the import address table are supposed to be
identical on disk, and prior to r277298 the import lookup table would be
used by `llvm-readobj -coff-imports` anyway, so this shouldn't have any
functional change (except in the case of our malformed binaries). The
import lookup table can apparently be missing when using old Borland
linkers, so fall back to the import address table in that case.
Resolves PR31766.
Differential Revision: https://reviews.llvm.org/D31362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298812
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Serge Pavlov [Sun, 26 Mar 2017 16:46:53 +0000 (16:46 +0000)]
[LoopUnroll] Remap references in peeled iteration
References in cloned blocks must be remapped prior to dominator
calculation.
Differential Revision: https://reviews.llvm.org/D31281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298811
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Chandler Carruth [Sun, 26 Mar 2017 14:24:06 +0000 (14:24 +0000)]
[IR] Switch to more normal template parameter names ending in `T`
instead of `Ty`.
The `Ty` suffix is much more commonly used for LLVM `Type` variable
names, so this seemed like a particularly confusing collision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298808
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Simon Pilgrim [Sun, 26 Mar 2017 13:59:17 +0000 (13:59 +0000)]
Fix signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298807
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Simon Pilgrim [Sun, 26 Mar 2017 13:17:55 +0000 (13:17 +0000)]
[X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298806
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Simon Pilgrim [Sun, 26 Mar 2017 12:52:28 +0000 (12:52 +0000)]
[X86][AVX512F] Fix reg class for VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk
Fixed -verify-machineinstrs errors in fast-isel-select-sse.ll (one of many in PR27481)
The VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk instructions were assuming both source registers were V128X when the second is actually supposed to be FR32X/FR64X
Differential Revision: https://reviews.llvm.org/D31200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298805
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Simon Pilgrim [Sun, 26 Mar 2017 11:17:05 +0000 (11:17 +0000)]
Fix MSVC signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298804
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Simon Pilgrim [Sun, 26 Mar 2017 10:33:03 +0000 (10:33 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298803
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Simon Pilgrim [Sun, 26 Mar 2017 10:31:37 +0000 (10:31 +0000)]
Regenerate test
The CHECK-DAG aren't necessary and get in the way of automated checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298802
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Simon Pilgrim [Sun, 26 Mar 2017 10:28:39 +0000 (10:28 +0000)]
Regenerate tests to remove duplicated checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298801
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Igor Breger [Sun, 26 Mar 2017 08:11:12 +0000 (08:11 +0000)]
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
Support G_FRAME_INDEX instruction selection.
Reviewers: zvi, rovka, ab, qcolombet
Reviewed By: ab
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298800
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Joerg Sonnenberger [Sun, 26 Mar 2017 06:44:08 +0000 (06:44 +0000)]
Split the SimplifyCFG pass into two variants.
The first variant contains all current transformations except
transforming switches into lookup tables. The second variant
contains all current transformations.
The switch-to-lookup-table conversion results in code that is more
difficult to analyze and optimize by other passes. Most importantly,
it can inhibit Dead Code Elimination. As such it is often beneficial to
only apply this transformation very late. A common example is inlining,
which can often result in range restrictions for the switch expression.
Changes in execution time according to LNT:
SingleSource/Benchmarks/Misc/fp-convert +3.03%
MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk -11.20%
MultiSource/Benchmarks/Olden/perimeter/perimeter -10.43%
and a couple of smaller changes. For perimeter it also results 2.6%
a smaller binary.
Differential Revision: https://reviews.llvm.org/D30333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298799
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Andrew Wilkins [Sun, 26 Mar 2017 05:58:48 +0000 (05:58 +0000)]
Add check for BSD when setting LIB_NAMES for GNU ld
Patch by Koop Mast and Alex Arslan!
Differential Revision: https://reviews.llvm.org/D28215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298798
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Chandler Carruth [Sun, 26 Mar 2017 02:49:23 +0000 (02:49 +0000)]
[IR] Make SwitchInst::CaseIt almost a normal iterator.
This moves it to the iterator facade utilities giving it full random
access semantics, etc. It can also now be used with standard algorithms
like std::all_of and std::any_of and range adaptors like llvm::reverse.
Also make the semantics of iterating match what every other iterator
uses and forbid decrementing past the begin iterator. This was used as
a hacky way to work around iterator invalidation. However, every
instance trying to do this failed to actually avoid touching invalid
iterators despite the clear documentation that the removed and all
subsequent iterators become invalid including the end iterator. So I've
added a return of the next iterator to removeCase and rewritten the
loops that were doing this to correctly follow the iterator pattern of
either incremneting or removing and assigning fresh values to the
iterator and the end.
In one case we were trying to go backwards to make this cleaner but it
doesn't actually work. I've made that code match the code we use
everywhere else to remove cases as we iterate. This changes the order of
cases in one test output and I moved that test to CHECK-DAG so it
wouldn't care -- the order isn't semantically meaningful anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298791
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Simon Pilgrim [Sat, 25 Mar 2017 21:22:12 +0000 (21:22 +0000)]
[X86] Pull out repeated ScalarValueSizeInBits code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298783
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Simon Pilgrim [Sat, 25 Mar 2017 20:43:01 +0000 (20:43 +0000)]
[X86][SSE] Combine (VSRLI (VSRAI X, Y), (NumSignBits-1)) -> (VSRLI X, (NumSignBits-1))
Part 3 of 3.
Differential Revision: https://reviews.llvm.org/D31347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298782
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Eric Christopher [Sat, 25 Mar 2017 20:20:23 +0000 (20:20 +0000)]
Change the default attributes for llvm.prefetch to inaccessiblemem_or_argmemonly
so that we can perform some optimizations across it.
Fixes PR32365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298781
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Simon Pilgrim [Sat, 25 Mar 2017 19:58:36 +0000 (19:58 +0000)]
[X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI
Part 2 of 3.
Differential Revision: https://reviews.llvm.org/D31347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298780
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Simon Pilgrim [Sat, 25 Mar 2017 19:50:14 +0000 (19:50 +0000)]
[X86][SSE] Generalised CMP+AND1 combine to ZERO/ALLBITS+MASK
Patch to generalize combinePCMPAnd1 (for handling SETCC + ZEXT cases) to work for any input that has zero/all bits set masked with an 'all low bits' mask.
Replaced the implicit assumption of shift availability with a call to SupportedVectorShiftWithImm.
Part 1 of 3.
Differential Revision: https://reviews.llvm.org/D31347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298779
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Sanjay Patel [Sat, 25 Mar 2017 16:05:33 +0000 (16:05 +0000)]
[x86] use PMOVMSK to replace memcmp libcalls for 16-byte equality
This is the payoff for D31156 - if a target has efficient comparison instructions for vector-sized equality,
we can replace memcmp calls with inline code that is both smaller and faster.
Differential Revision: https://reviews.llvm.org/D31290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298775
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Simon Pilgrim [Sat, 25 Mar 2017 15:43:36 +0000 (15:43 +0000)]
[X86][SSE] Add extra computeNumSignBits test case for D31311.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298774
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Craig Topper [Sat, 25 Mar 2017 06:52:52 +0000 (06:52 +0000)]
[InstCombine] Change the interface of SimplifyDemandedBits so that it takes the instruction and operand instead of the Use.
The first thing it did was get the User for the Use to get the instruction back. This requires looking through the Uses for the User using the waymarking walk. That's pretty fast, but its probably still better to just pass the Instruction we already had.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298772
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Balaram Makam [Sat, 25 Mar 2017 04:02:39 +0000 (04:02 +0000)]
[AArch64] Refine Falkor Machine Model - Part1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298768
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Davide Italiano [Sat, 25 Mar 2017 02:40:02 +0000 (02:40 +0000)]
[NewGVN] Adjust NDEBUG markers.
This avoids 'used but not defined' warnings in Release builds
with GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298760
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Yaxun Liu [Sat, 25 Mar 2017 02:05:44 +0000 (02:05 +0000)]
[AMDGPU] Switch data layout by triple environment amdgiz
Switch data layout by target triple environment amdgiz and amdgizcl indicating using of an address space mapping in which generic address space is 0.
amdgiz is for non-OpenCL environment where generic address space is 0.
amdgizcl is for OpenCL environment where generic address space is 0.
Differential Revision: https://reviews.llvm.org/D31211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298758
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Vitaly Buka [Sat, 25 Mar 2017 01:19:45 +0000 (01:19 +0000)]
[libFuzzer] Fix test on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298757
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Evgeniy Stepanov [Sat, 25 Mar 2017 01:01:11 +0000 (01:01 +0000)]
[asan] Put ctor/dtor in comdat.
When possible, put ASan ctor/dtor in comdat.
The only reason not to is global registration, which can be
TU-specific. This is not the case when there are no instrumented
globals. This is also limited to ELF targets, because MachO does
not have comdat, and COFF linkers may GC comdat constructors.
The benefit of this is a lot less __asan_init() calls: one per DSO
instead of one per TU. It's also necessary for the upcoming
gc-sections-for-globals change on Linux, where multiple references to
section start symbols trigger quadratic behaviour in gold linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298756
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Kostya Serebryany [Sat, 25 Mar 2017 00:56:08 +0000 (00:56 +0000)]
[libFuzzer] read asan's dedup_token while minimizing a crash and stop minimization if another bug was found during minimization (https://github.com/google/oss-fuzz/issues/452)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298755
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Eli Friedman [Sat, 25 Mar 2017 00:13:24 +0000 (00:13 +0000)]
[ARM] Fix mixup between Lo and Hi in SMLALBB formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298752
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Simon Pilgrim [Fri, 24 Mar 2017 23:47:41 +0000 (23:47 +0000)]
Apply clang-format as commented in D31311. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298751
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Reid Kleckner [Fri, 24 Mar 2017 23:28:42 +0000 (23:28 +0000)]
[codeview] Don't assert when the user violates the ODR
If we have an array of a user-defined aggregates for which there was an
ODR violation, then the array size will not necessarily match the number
of elements times the size of the element.
Fixes PR32383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298750
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Jessica Paquette [Fri, 24 Mar 2017 23:00:21 +0000 (23:00 +0000)]
[Outliner] Revert r298734.
When I tested r298734, I thought that red zones were enabled by default like in
X86. Since red zones are behind a flag on AArch64 the testing wasn't true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298747
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Kostya Serebryany [Fri, 24 Mar 2017 22:19:52 +0000 (22:19 +0000)]
[libFuzzer] be more careful when calling strlen of strcmp parameters, PR32357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298746
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Craig Topper [Fri, 24 Mar 2017 22:12:10 +0000 (22:12 +0000)]
Revert r298711 "[InstCombine] Provide a way to calculate KnownZero/One for Add/Sub in SimplifyDemandedUseBits without recursing into ComputeKnownBits"
Tsan bot is failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298745
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Sanjay Patel [Fri, 24 Mar 2017 22:09:48 +0000 (22:09 +0000)]
[x86] add 32-bit RUN for better memcmp coverage; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298744
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Kostya Serebryany [Fri, 24 Mar 2017 21:09:16 +0000 (21:09 +0000)]
[libFuzzer] honor -exact_artifact_path for all intermediate files during crash minimization (https://github.com/google/oss-fuzz/issues/250)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298740
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Krzysztof Parzyszek [Fri, 24 Mar 2017 21:01:16 +0000 (21:01 +0000)]
Move spill size and alignment info from MC to TargetRegisterInfo
This is another step towards implementing register classes with
parametrized register/spill sizes and value types.
This is an updated version of r298652. The difference is that MCRegister-
Class still contains register size, available as getPhysRegSize(). The
old function getSize was retained as a temporary measure to avoid build
breakage for out-of-tree targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298739
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Matt Arsenault [Fri, 24 Mar 2017 20:57:10 +0000 (20:57 +0000)]
AMDGPU: Fix annotating loops with nested loop conditions
If the branch condition for a loop was a phi which itself
was fed from a phi from a loop, it isn't safe to try
to delete the phi until after the loop is handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298737
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Davide Italiano [Fri, 24 Mar 2017 20:52:56 +0000 (20:52 +0000)]
[MachineScheduler] Add missing machine pass dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298736
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Ivan Krasin [Fri, 24 Mar 2017 20:49:43 +0000 (20:49 +0000)]
Revert r298620: [LV] Vectorize GEPs
Reason: breaks linking Chromium with LLD + ThinLTO (a pass crashes)
LLVM bug: https://bugs.llvm.org//show_bug.cgi?id=32413
Original change description:
[LV] Vectorize GEPs
This patch adds support for vectorizing GEPs. Previously, we only generated
vector GEPs on-demand when creating gather or scatter operations. All GEPs from
the original loop were scalarized by default, and if a pointer was to be stored
to memory, we would have to build up the pointer vector with insertelement
instructions.
With this patch, we will vectorize all GEPs that haven't already been marked
for scalarization.
The patch refines collectLoopScalars to more exactly identify the scalar GEPs.
The function now more closely resembles collectLoopUniforms. And the patch
moves vector GEP creation out of vectorizeMemoryInstruction and into the main
vectorization loop. The vector GEPs needed for gather and scatter operations
will have already been generated before vectoring the memory accesses.
Original Differential Revision: https://reviews.llvm.org/D30710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298735
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Jessica Paquette [Fri, 24 Mar 2017 20:47:59 +0000 (20:47 +0000)]
[Outliner] Remove no red zone requirment for AArch64
AArch64 doesn't require -mno-red-zone; stack fixups are sufficient here. This was
unnecessarily copied over from the X86 target.
(You can now outline with red zones! Yay!)
Removing the requirement passes all Single/MultiSource tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298734
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Reid Kleckner [Fri, 24 Mar 2017 20:47:41 +0000 (20:47 +0000)]
Document how to fetch monorepo SVN revision notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298733
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Evgeniy Stepanov [Fri, 24 Mar 2017 20:42:15 +0000 (20:42 +0000)]
[asan] Delay creation of asan ctor.
Create the constructor in the module pass.
This in needed for the GC-friendly globals change, where the constructor can be
put in a comdat in some cases, but we don't know about that in the function
pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298731
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Matt Arsenault [Fri, 24 Mar 2017 20:04:18 +0000 (20:04 +0000)]
AMDGPU: Implement f16 fround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298730
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Matt Arsenault [Fri, 24 Mar 2017 19:52:05 +0000 (19:52 +0000)]
AMDGPU: Unify divergent function exits.
StructurizeCFG can't handle cases with multiple
returns creating regions with multiple exits.
Create a copy of UnifyFunctionExitNodes that only
unifies exit nodes that skips exit nodes
with uniform branch sources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298729
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Krzysztof Parzyszek [Fri, 24 Mar 2017 19:18:29 +0000 (19:18 +0000)]
Revert r298652 on Quentin's request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298727
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Adrian Prantl [Fri, 24 Mar 2017 19:11:31 +0000 (19:11 +0000)]
Make testcase less nonsensical while still exercising the same code paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298726
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Matt Arsenault [Fri, 24 Mar 2017 19:04:57 +0000 (19:04 +0000)]
AMDGPU: Fold rcp/rsq of undef to undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298725
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Matt Arsenault [Fri, 24 Mar 2017 18:56:43 +0000 (18:56 +0000)]
TTI: Split IsSimple in MemIntrinsicInfo
All this did before was assert in EarlyCSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298724
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Stanislav Mekhanoshin [Fri, 24 Mar 2017 18:55:20 +0000 (18:55 +0000)]
[AMDGPU] Fold V_CNDMASK with identical source operands
Such instructions sometimes appear after lowering and folding.
Differential Revision: https://reviews.llvm.org/D31318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298723
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Konstantin Zhuravlyov [Fri, 24 Mar 2017 18:43:15 +0000 (18:43 +0000)]
[AMDGPU] Rename Kind to ValueKind in metadata to be consistent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298722
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Stanislav Mekhanoshin [Fri, 24 Mar 2017 18:01:14 +0000 (18:01 +0000)]
[AMDGPU] Add AMDGPUAliasAnalysis to opt pipeline
Previously it was added only to the BE.
Differential Revision: https://reviews.llvm.org/D31323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298721
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Teresa Johnson [Fri, 24 Mar 2017 17:59:06 +0000 (17:59 +0000)]
[ThinLTO] Correct counting of functions in inliner stats
Summary: Declarations need to be filtered out when counting functions.
Reviewers: eraman
Subscribers: Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D31336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298720
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Benjamin Kramer [Fri, 24 Mar 2017 17:53:06 +0000 (17:53 +0000)]
[AMDGPU] Don't enforce constexpr, there are still old standard libraries around that don't have a constexpr std::pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298719
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Valery Pykhtin [Fri, 24 Mar 2017 17:49:05 +0000 (17:49 +0000)]
[AMDGPU] Remove double map lookups in SI scheduler
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298718
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Reid Kleckner [Fri, 24 Mar 2017 17:26:38 +0000 (17:26 +0000)]
[PDB] Split item and type records when merging type streams
Summary: MSVC does this when producing a PDB.
Reviewers: ruiu
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298717
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Simon Pilgrim [Fri, 24 Mar 2017 17:25:47 +0000 (17:25 +0000)]
[X86][SSE] Add ashr + mask test cases.
Test cases showing cases where we're missing an opportunity to lshr a value with an extended sign to avoid loading a mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298716
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Craig Topper [Fri, 24 Mar 2017 16:56:51 +0000 (16:56 +0000)]
[InstCombine] Provide a way to calculate KnownZero/One for Add/Sub in SimplifyDemandedUseBits without recursing into ComputeKnownBits
SimplifyDemandedUseBits for Add/Sub already recursed down LHS and RHS for simplifying bits. If that didn't provide any simplifications we fall back to calling computeKnownBits which will recurse again. Instead just take the known bits for LHS and RHS we already have and call into a new function in ValueTracking that can calculate the known bits given the LHS/RHS bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298711
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Valery Pykhtin [Fri, 24 Mar 2017 16:45:50 +0000 (16:45 +0000)]
[AMDGPU] Fix SGPR usage count in SI scheduler
Patch by Axel Davy (axel.davy@normalesup.org)
Differential revision: https://reviews.llvm.org/D30149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298710
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