OSDN Git Service
Kevin P. Neal [Thu, 30 May 2019 16:44:47 +0000 (16:44 +0000)]
[FPEnv] Added a special UnrollVectorOp method to deal with the chain on StrictFP opcodes
This change creates UnrollVectorOp_StrictFP. The purpose of this is to address a failure that consistently occurs when calling StrictFP functions on vectors whose number of elements is 3 + 2n on most platforms, such as PowerPC or SystemZ. The old UnrollVectorOp method does not expect that the vector that it will unroll will have a chain, so it has an assert that prevents it from running if this is the case. This new StrictFP version of the method deals with the chain while unrolling the vector. With this new function in place during vector widending, llc can run vector-constrained-fp-intrinsics.ll for SystemZ successfully.
Submitted by: Drew Wock <drew.wock@sas.com>
Reviewed by: Cameron McInally, Kevin P. Neal
Approved by: Cameron McInally
Differential Revision: http://reviews.llvm.org/D62546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362112
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Roman Lebedev [Thu, 30 May 2019 16:07:19 +0000 (16:07 +0000)]
[NFC][Codegen] Add better test coverage for potential add/sub constant folding
This adds hopefully-full test coverage for all the possible permutations:
First op is one of:
* x + c1
* x - c1
* c1 - x
Second op is one of:
* + c2
* - c2
* c2 -
And thus 3*3=9 patterns.
Some of them show missed constant-folds.
Without previous patch (the revert), these tests were causing endless
dagcombine loop. I really should have thought about this first :S
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362110
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Roman Lebedev [Thu, 30 May 2019 16:07:11 +0000 (16:07 +0000)]
[DAGCombine] Revert of recommit of "binop-with-const hoisting" patches
I was looking into an endless combine loop the uncommitted follow-up patch
was causing, and it appears even these patches can exibit such an
endless loop. The root cause is that we try to hoist one binop (add/sub) with
constant operand, and if we get two such binops both of which are
eligible for this hoisting, we get stuck.
Some cases may highlight missing constant-folds.
Reverts r361871,r361872,r361873,r361874.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362109
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Sam Parker [Thu, 30 May 2019 15:26:37 +0000 (15:26 +0000)]
[NFC][ARM][ParallelDSP] Refactor narrow sequence
Most of the code used for finding a 'narrow' sequence is not used,
so I've removed it and simplified the calls from the smlad matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362104
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Sjoerd Meijer [Thu, 30 May 2019 14:34:29 +0000 (14:34 +0000)]
[ARM] Change the MC names for VMAXNM/VMINNM
Now the NEON ones have a prefix "NEON_", and the VFP ones have a
prefix "VFP_". This is so that the regex in ARMScheduleA57.td can be
made to match both of _those_ classes of VMAXNM without also matching
the MVE ones that are going to be introduced soon. NFCI.
Patch by Simon Tatham.
Differential Revision: https://reviews.llvm.org/D60700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362097
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Simon Pilgrim [Thu, 30 May 2019 14:01:24 +0000 (14:01 +0000)]
[ARM] LowerVECTOR_SHUFFLE - fix uninitialized variable warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362094
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Roman Lebedev [Thu, 30 May 2019 13:02:11 +0000 (13:02 +0000)]
[NFC][Codegen] Add add+sub/sub+add constant-fold tests for from D62257
add+sub/sub+add when second operands are constants should be folded
into a single add, just like with add+add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362093
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Roman Lebedev [Thu, 30 May 2019 13:02:06 +0000 (13:02 +0000)]
[LoopIdiom] Basic OptimizationRemarkEmitter handling
Summary:
I'm adding ORE to memset/memcpy formation, with tests,
but mainly this is split off from D61144.
Reviewers: reames, anemet, thegameg, craig.topper
Reviewed By: thegameg
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362092
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Roman Lebedev [Thu, 30 May 2019 13:01:53 +0000 (13:01 +0000)]
[LoopIdiomRecognize][NFC] Sort includes
Split off from D61144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362091
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Sjoerd Meijer [Thu, 30 May 2019 12:57:04 +0000 (12:57 +0000)]
[ARM] add target arch definitions for 8.1-M and MVE
This adds:
- LLVM subtarget features to make all the new instructions conditional on,
- CPU and FPU names for use on clang's command line, with default FPUs set
so that "armv8.1-m.main+fp" and "armv8.1-m.main+fp.dp" will select the right
FPU features,
- architecture extension names "mve" and "mve.fp",
- ABI build attribute support for v8.1-M (a new value for Tag_CPU_arch) and MVE
(a new actual tag).
Patch mostly by Simon Tatham.
Differential Revision: https://reviews.llvm.org/D60698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362090
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George Rimar [Thu, 30 May 2019 12:39:05 +0000 (12:39 +0000)]
[llvm-readobj] - Rewrite reloc-types.test to use YAML. NFCI.
This change rewrites and splits reloc-types.test
to use yaml2obj instead of precompiled binaries.
That allowed to remove 7 precompiled objects from the inputs.
I took the existent objects, used obj2yaml on them, simplified the result and
used yaml2obj in the test case with the result.
Notes:
* I converted, but did not remove relocs.obj.elf-i386, relocs.obj.elf-x86_64 or relocs.obj.elf-mips objects
because found they are used in other tests.
* I was unable to convert relocs.obj.elf-ppc64, because obj2yaml hangs on this file for me.
* I was unable to convert relocs.obj.macho-arm, relocs.obj.macho-i386 and relocs.obj.macho-x86_64
because the output produced by obj2yaml does not seem to be correct.
* Because of the above I did not remove the script for creating all
of those objects: test\tools\llvm-readobj\Inputs\relocs.py
Differential revision: https://reviews.llvm.org/D62594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362089
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Sjoerd Meijer [Thu, 30 May 2019 12:37:05 +0000 (12:37 +0000)]
[ARM] Introduce separate features for FP registers
The MVE extension in Arm v8.1-M permits the use of some move, load and
store isntructions which access the FP registers, even if there's no
actual FP support in the processor (in particular, if you have the
integer-only version of MVE).
Therefore, we need separate subtarget features to condition those
instructions on, which are implied by both FP and MVE but are not part
of either.
Patch mostly by Simon Tatham.
Differential Revision: https://reviews.llvm.org/D60694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362088
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George Rimar [Thu, 30 May 2019 10:42:47 +0000 (10:42 +0000)]
[llvm-readobj] - An attemp to fix BB.
BB failed:
http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/15062/steps/build%20stage%201/logs/stdio
Error was:
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/tools/llvm-readobj/ELFDumper.cpp:3540:7:
error: non-constant-expression cannot be narrowed from type 'llvm::support::detail::packed_endian_specific_integral<unsigned long long,
llvm::support::endianness::little, 1>::value_type' (aka 'unsigned long long') to 'size_t' (aka 'unsigned int') in initializer list [-Wc++11-narrowing]
StrTabSec->sh_size};
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362084
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Simon Pilgrim [Thu, 30 May 2019 10:41:04 +0000 (10:41 +0000)]
[CostModel][X86] Add bool vector and/or/xor cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362083
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George Rimar [Thu, 30 May 2019 10:36:52 +0000 (10:36 +0000)]
[llvm-readobj/llvm-readelf] - Implement GNU style dumper of the SHT_GNU_verdef section.
It was not implemented yet, we had only LLVM style dumper implemented.
Section description is here: https://refspecs.linuxfoundation.org/LSB_5.0.0/LSB-Core-generic/LSB-Core-generic/symversion.html
Differential revision: https://reviews.llvm.org/D62520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362082
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Simon Pilgrim [Thu, 30 May 2019 10:25:20 +0000 (10:25 +0000)]
[X86][SSE] Improve bool vector extload (PR26091)
We already have good codegen for (vXiY *ext(vXi1 bitcast(iX))) cases, this patch uses it for loads of vXi1 types as well - changing the load into a iX integer load, and bitcasting so that combineToExtendBoolVectorInReg can then use it.
Differential Revision: https://reviews.llvm.org/D62449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362081
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George Rimar [Thu, 30 May 2019 10:14:41 +0000 (10:14 +0000)]
[llvm-readobj/llvm-readelf] - Implement GNU style dumper of the SHT_GNU_verneed section.
It was not implemented yet, we had only LLVM style dumper implemented.
Section description is here: https://refspecs.linuxfoundation.org/LSB_2.0.1/LSB-Core/LSB-Core/symverrqmts.html
Differential revision: https://reviews.llvm.org/D62516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362080
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Simon Pilgrim [Thu, 30 May 2019 09:40:35 +0000 (09:40 +0000)]
Fix sphinx warning about missing footnote.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362077
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Eugene Leviant [Thu, 30 May 2019 09:09:01 +0000 (09:09 +0000)]
[llvm-objcopy] Remove %p format specifiers
On 32-bit machines %p expects 32 bit values, however
addresses in llvm-objcopy are always 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362074
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Cullen Rhodes [Thu, 30 May 2019 08:51:39 +0000 (08:51 +0000)]
[AArch64][SVE2] Asm: support SVE2 vector splice (constructive)
Summary:
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362073
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Cullen Rhodes [Thu, 30 May 2019 08:44:27 +0000 (08:44 +0000)]
[AArch64][SVE2] Asm: support SVE2 load instructions
Summary:
Patch adds support for the following instructions:
* LDNT1SB, LDNT1B, LDNT1SH, LDNT1H, LDNT1SW, LDNT1W, LDNT1D
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362072
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Cullen Rhodes [Thu, 30 May 2019 08:35:12 +0000 (08:35 +0000)]
[AArch64][SVE2] Asm: support FCVTX/FLOGB instructions
Summary:
Patch completes SVE2 support for:
SVE Floating Point Unary Operations - Predicated Group
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362071
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Cullen Rhodes [Thu, 30 May 2019 08:25:17 +0000 (08:25 +0000)]
[AArch64][SVE2] Asm: add ext (immediate offset, constructive) instruction
Summary:
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362070
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Sjoerd Meijer [Thu, 30 May 2019 08:07:06 +0000 (08:07 +0000)]
[ARM] Add an MVE execution domain
MVE architecturally specifies a 'beat' system in which a vector
instruction executed now will complete its actual operation over the
next four cycles, so it can overlap with the execution of the previous
and next MVE instruction.
This makes it generally an advantage to avoid moving values back and
forth between MVE registers and anywhere else, if there's any sensible
way to do the same processing in whatever register type the values
already occupied.
That's just what the 'execution domain' system is supposed to achieve.
So here we add a new execution domain which will contain all the MVE
vector instructions when they are added.
Patch by: Simon Tatham
Differential Revision: https://reviews.llvm.org/D60703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362068
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Sjoerd Meijer [Thu, 30 May 2019 07:38:09 +0000 (07:38 +0000)]
[TableGen] AsmMatcher: allow repeated input operands
If an assembly instruction has to mention an input operand name twice,
for example the MVE VMOV instruction that accesses two lanes of the
same vector by writing 'vmov r1, r2, q0[3], q0[1]', then the obvious
way to write its AsmString is to include the same operand (here $Qd)
twice. But this causes the AsmMatcher generator to omit that
instruction completely from the match table, on the basis that the
generator isn't clever enough to deal with the duplication.
But you need to have _some_ way of dealing with an instruction like
this - and in this case, where the mnemonic is shared with many other
instructions that the AsmMatcher does handle, it would be very painful
to take it out of the AsmMatcher system completely.
A nicer way is to add a custom AsmMatchConverter routine, and let that
deal with the problem if the autogenerated converter can't. But that
doesn't work, because TableGen leaves the instruction out of its table
_even_ if you provide a custom converter.
Solution: this change, which makes TableGen relax the restriction on
duplicated operands in the case where there's a custom converter.
Patch by: Simon Tatham
Differential Revision: https://reviews.llvm.org/D60695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362066
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Petr Hosek [Thu, 30 May 2019 07:34:39 +0000 (07:34 +0000)]
[CMake] Use find_package(LLVM) instead of LLVMConfig
This addresses an issues introduced in r362047.
Differential Revision: https://reviews.llvm.org/D62640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362065
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Sjoerd Meijer [Thu, 30 May 2019 07:30:37 +0000 (07:30 +0000)]
[TableGen] New default operand "undef_tied_input"
This is a new special identifier which you can use as a default in
OperandWithDefaultOps. The idea is that you use it for an input
operand of an instruction that's tied to an output operand, and its
semantics are that (in the default case) the input operand's value is
not used at all.
The detailed effect is that when instruction selection emits the
instruction in the form of a pre-regalloc MachineInstr, it creates an
IMPLICIT_DEF node to use as that input.
If you're creating an MCInst with explicit register names, then the
right handling would be to set the input operand to the same register
as the output one (honouring the tie) and to add the 'undef' flag
indicating that that register is deemed to acquire a new don't-care
definition just before we read it. But I haven't done that in this
commit, because there was no need to - no Tablegen backend seems to
autogenerate default fields in an MCInst.
Patch by: Simon Tatham
Differential Revision: https://reviews.llvm.org/D60696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362064
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Craig Topper [Thu, 30 May 2019 06:48:13 +0000 (06:48 +0000)]
[LoopVectorize] Precommit tests for D62510. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362060
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Florian Hahn [Thu, 30 May 2019 05:03:12 +0000 (05:03 +0000)]
[LV] Inform about exactly reason of loop illegality
Currently, only the following information is provided by LoopVectorizer
in the case when the CF of the loop is not legal for vectorization:
LV: Can't vectorize the instructions or CFG
LV: Not vectorizing: Cannot prove legality.
But this information is not enough for the root cause analysis; what is
exactly wrong with the loop should also be printed:
LV: Not vectorizing: The exiting block is not the loop latch.
Patch by Pavel Samolysov.
Reviewers: mkuper, hsaito, rengolin, fhahn
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D62311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362056
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Pengfei Wang [Thu, 30 May 2019 03:59:16 +0000 (03:59 +0000)]
[X86] Add ENQCMD instructions
For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.
Patch by Tianqing Wang (tianqing)
Differential Revision: https://reviews.llvm.org/D62281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362053
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Petr Hosek [Thu, 30 May 2019 01:24:31 +0000 (01:24 +0000)]
[CMake] Set LLVM_PATH in the runtimes build
This avoids using llvm-config for inferring various paths within the
runtimes build. We also set LLVM_INCLUDE_DIR variable that's used by
these builds and move assignment of LLVM_BINARY_DIR and LLVM_LIBRARY_DIR
to the same location for consistency.
Differential Revision: https://reviews.llvm.org/D62637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362047
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Jan Korous [Thu, 30 May 2019 01:08:38 +0000 (01:08 +0000)]
[BitstreamWriter][NFC] Remove obsolete comment.
The Abbv parameter was just a raw pointer when the comment was written.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362046
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Seiya Nuta [Wed, 29 May 2019 22:21:12 +0000 (22:21 +0000)]
[llvm-objcopy][MachO] Print an error message on use of unsupported options
Summary:
It is better to print an error message instead of silently ignoring unsupported options.
As mentioned in https://reviews.llvm.org/D57045, this is not the best solution and we should print which flag is not supported at some time.
Reviewers: alexshap, rupprecht, jhenderson, jakehehrlich
Reviewed By: alexshap, rupprecht, jakehehrlich
Subscribers: jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362040
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Amy Huang [Wed, 29 May 2019 21:45:34 +0000 (21:45 +0000)]
CodeView - add static data members to global variable debug info.
Summary:
Add static data members to IR debug info's list of global variables
so that they are emitted as S_CONSTANT records.
Related to https://bugs.llvm.org/show_bug.cgi?id=41615.
Reviewers: rnk
Subscribers: aprantl, cfe-commits, llvm-commits, thakis
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D62167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362038
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Reid Kleckner [Wed, 29 May 2019 21:26:25 +0000 (21:26 +0000)]
[llvm-pdbutil] Dump inline call site line table annotations
This ports and improves on some existing llvm-readobj -codeview dumping
functionality that llvm-pdbutil lacked.
Helpful for comparing inline line tables between MSVC and clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362037
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Matt Arsenault [Wed, 29 May 2019 20:47:59 +0000 (20:47 +0000)]
LoopVersioningLICM: Respect convergent and noduplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362031
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Tim Northover [Wed, 29 May 2019 20:46:38 +0000 (20:46 +0000)]
Revert "IR: add optional type to 'byval' function parameters"
The IRLinker doesn't delve into the new byval attribute when mapping types, and
this breaks LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362029
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Roman Lebedev [Wed, 29 May 2019 20:11:53 +0000 (20:11 +0000)]
[LoopIdiomRecognize][NFC] Use DEBUG_TYPE, add LLVM_DEBUG() to runOnNoncountableLoop()
Split off from D61144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362022
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Pete Couperus [Wed, 29 May 2019 20:07:35 +0000 (20:07 +0000)]
[ARC] Cleanup ARCAsmPrinter.
Summary:
Remove unused getTargetStreamer.
Remove unused headers.
Reviewers: dantrushin
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362021
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Roman Lebedev [Wed, 29 May 2019 20:03:00 +0000 (20:03 +0000)]
UpdateTestChecks: Lanai triple support
Summary:
The assembly structure most resembles the SPARC pattern:
```
.globl f6 ! -- Begin function f6
.p2align 2
.type f6,@function
f6: ! @f6
.cfi_startproc
! %bb.0:
st %fp, [--%sp]
<...>
ld -8[%fp], %fp
.Lfunc_end0:
.size f6, .Lfunc_end0-f6
.cfi_endproc
! -- End function
```
Test being affected by upcoming patch, so regenerate it.
Reviewers: RKSimon, jpienaar
Reviewed By: RKSimon
Subscribers: jyknight, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362019
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Nico Weber [Wed, 29 May 2019 20:00:36 +0000 (20:00 +0000)]
gn build: Make it possible to build with coverage information
Differential Revision: https://reviews.llvm.org/D62508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362018
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Benjamin Kramer [Wed, 29 May 2019 19:24:19 +0000 (19:24 +0000)]
[DAGCombiner] Replace gathers with a zero mask with the passthru value
These can be created by the legalizer when splitting a larger gather.
See https://llvm.org/PR42055 for a motivating example.
Differential Revision: https://reviews.llvm.org/D62613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362015
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Tim Northover [Wed, 29 May 2019 19:12:48 +0000 (19:12 +0000)]
IR: add optional type to 'byval' function parameters
When we switch to opaque pointer types we will need some way to describe
how many bytes a 'byval' parameter should occupy on the stack. This adds
a (for now) optional extra type parameter.
If present, the type must match the pointee type of the argument.
Note to front-end maintainers: if this causes test failures, it's probably
because the "byval" attribute is printed after attributes without any parameter
after this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362012
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Chris Bieneman [Wed, 29 May 2019 18:37:49 +0000 (18:37 +0000)]
[CMake] [Runtimes] Set *_STANDALONE_BUILD
Summary:
The runtimes use `*_STANDALONE_BUILD=OFF` to signify that clang is an in-tree target. This is not the case with the runtime builds, so we really need this set to `ON`.
In order to resolve the issues phosek was having with checks, we should use checks that don't link. We can use compiler-rt's `try_compile_only` as a basis for that.
This patch is *required* to be able to run the runtime libraries check-* targets.
Reviewers: smeenai, phosek, compnerd
Reviewed By: phosek
Subscribers: mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362007
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Nikita Popov [Wed, 29 May 2019 18:37:13 +0000 (18:37 +0000)]
[InstCombine] Optimize always overflowing signed saturating add/sub
Based on the overflow direction information added in D62463, we can
now fold always overflowing signed saturating add/sub to signed min/max.
Differential Revision: https://reviews.llvm.org/D62544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362006
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Aakanksha Patil [Wed, 29 May 2019 18:20:11 +0000 (18:20 +0000)]
AMDGPU: Return address lowering
The patch computes the return address for the current function.
Differential revision: https://reviews.llvm.org/D59666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362001
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Stella Stamenova [Wed, 29 May 2019 18:07:39 +0000 (18:07 +0000)]
lit: modernize the lit configuration for the lit tests
Summary: This also normalizes the config feature that represents the windows platform to "system-windows" as opposed to having both "windows" and "system-windows"
Reviewers: asmith, probinson
Subscribers: delcypher, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361998
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Eugene Leviant [Wed, 29 May 2019 17:14:48 +0000 (17:14 +0000)]
Yet another attempt to fix buildbot after r361949
Looks like %p format specifier of createStringError behaves
differently on different platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361993
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Craig Topper [Wed, 29 May 2019 17:02:27 +0000 (17:02 +0000)]
[X86] Fix machineverifier error on avx512f-256-set0.mir
Previously the pass ran the entire llc pipeline which caused the IR to be recodegened.
This commit restricts it to just running the postrapseudos pass and checking the results of that instead of the final assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361991
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Matt Arsenault [Wed, 29 May 2019 16:59:48 +0000 (16:59 +0000)]
CallSiteSplitting: Respect convergent and noduplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361990
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Teresa Johnson [Wed, 29 May 2019 16:50:46 +0000 (16:50 +0000)]
[ThinLTO] Use original alias visibility when importing
Summary:
When we import an alias, we do so by making a clone of the aliasee. Just
as this clone uses the original alias name and linkage, it should also
use the same visibility (not the aliasee's visibility). Otherwise,
linker behavior is affected (e.g. if the aliasee was hidden, but the
alias is not, the resulting imported clone should not be hidden,
otherwise the linker will make the final symbol hidden which is
incorrect).
Reviewers: wmi
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361989
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Cameron McInally [Wed, 29 May 2019 16:50:14 +0000 (16:50 +0000)]
[NFC][InstCombine] Add a unary FNeg test to fsub.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361988
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Kevin P. Neal [Wed, 29 May 2019 16:29:31 +0000 (16:29 +0000)]
Partial revert of revert of r361827: Add constrained intrinsic tests for powerpc64le.
The powerpc64-"nonle" tests are removed. They fail because of a bug that
Drew is currently working on that affects multiple targets.
Submitted by: Drew Wock <drew.wock@sas.com>
Reviewed by: Hal Finkel, Kevin P. Neal
Approved by: Hal Finkel
Differential Revision: http://reviews.llvm.org/D62388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361985
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Cameron McInally [Wed, 29 May 2019 15:29:35 +0000 (15:29 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fpcast.ll and fpextend.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361973
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Cameron McInally [Wed, 29 May 2019 15:21:28 +0000 (15:21 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fsub.ll known-never-nan.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361971
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Sam McCall [Wed, 29 May 2019 15:02:16 +0000 (15:02 +0000)]
Qualify use of llvm::empty that's ambiguous with std::empty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361968
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Simon Atanasyan [Wed, 29 May 2019 14:59:07 +0000 (14:59 +0000)]
[mips] Use reg-exp in tests to tolerate register indexes changing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361966
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Simon Atanasyan [Wed, 29 May 2019 14:58:56 +0000 (14:58 +0000)]
[mips] Iterate over MSACtrlRegClass to reserve all MSA control registers. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361965
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Simon Atanasyan [Wed, 29 May 2019 14:58:50 +0000 (14:58 +0000)]
[mips] Use range-based for loops. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361964
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Simon Pilgrim [Wed, 29 May 2019 14:39:37 +0000 (14:39 +0000)]
Revert rL361944 from llvm/trunk :
[ADT] add iterator_range::empty()
........
Breaks windows buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361963
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Nico Weber [Wed, 29 May 2019 14:15:35 +0000 (14:15 +0000)]
gn build: Merge r361953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361961
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Sjoerd Meijer [Wed, 29 May 2019 13:41:57 +0000 (13:41 +0000)]
[ARM] Split predicates out into their own .td file
The new ARMPredicates.td is included from ARM.td, early enough that
the predicate definitions are already in scope when ARMSchedule.td is
included. This will make it possible to refer to them in
UnsupportedFeatures fields of scheduling models.
NFC: the chunk of Tablegen being moved here is copied and pasted
verbatim.
Patch by: Simon Tatham
Differential Revision: https://reviews.llvm.org/D60693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361958
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Matt Arsenault [Wed, 29 May 2019 13:14:39 +0000 (13:14 +0000)]
SpeculateAroundPHIs: Respect convergent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361957
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Matt Arsenault [Wed, 29 May 2019 13:14:35 +0000 (13:14 +0000)]
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
This has been a mandatory part of the build for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361956
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Eugene Leviant [Wed, 29 May 2019 12:26:23 +0000 (12:26 +0000)]
Attempt to fix buildbot after r361949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361954
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Graham Hunter [Wed, 29 May 2019 12:22:54 +0000 (12:22 +0000)]
[SVE][IR] Scalable Vector IR Type
* Adds a 'scalable' flag to VectorType
* Adds an 'ElementCount' class to VectorType to pass (possibly scalable) vector lengths, with overloaded operators.
* Modifies existing helper functions to use ElementCount
* Adds support for serializing/deserializing to/from both textual and bitcode IR formats
* Extends the verifier to reject global variables of scalable types
* Updates documentation
See the latest version of the RFC here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124396.html
Reviewers: rengolin, lattner, echristo, chandlerc, hfinkel, rkruppe, samparker, SjoerdMeijer, greened, sebpop
Reviewed By: hfinkel, sebpop
Differential Revision: https://reviews.llvm.org/D32530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361953
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Andrea Di Biagio [Wed, 29 May 2019 11:38:27 +0000 (11:38 +0000)]
[MCA] Refactor class LSUnit. NFCI
This should be the last bit of refactoring in preparation for a patch that would
finally fix PR37494.
This patch introduces the concept of memory dependency groups (class
MemoryGroup) and "Load/Store Unit token" (LSUToken) to track the status of a
memory operation.
A MemoryGroup is a node of a memory dependency graph. It is used internally to
classify memory operations based on the memory operations they depend on. Let I
and J be two memory operations, we say that I and J equivalent (for the purpose
of mapping instructions to memory dependency groups) if the set of memory
operations they depend depend on is identical.
MemoryGroups are identified by so-called LSUToken (a unique group identifier
assigned by the LSUnit to every group). When an instruction I is dispatched to
the LSUnit, the LSUnit maps I to a group, and then returns a LSUToken.
LSUTokens are used by class Scheduler to track memory dependencies.
This patch simplifies the LSUnit interface and moves most of the implementation
details to its base class (LSUnitBase). There is no user visible change to the
output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361950
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Eugene Leviant [Wed, 29 May 2019 11:37:16 +0000 (11:37 +0000)]
[llvm-objcopy] Implement IHEX writer
Differential revision: https://reviews.llvm.org/D60270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361949
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George Rimar [Wed, 29 May 2019 11:01:07 +0000 (11:01 +0000)]
[llvm-readobj] - Repair the test case.
I forgot to change the test tag in r361932.
Now it is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361945
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Sam McCall [Wed, 29 May 2019 10:39:01 +0000 (10:39 +0000)]
[ADT] add iterator_range::empty()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361944
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George Rimar [Wed, 29 May 2019 10:31:46 +0000 (10:31 +0000)]
[llvm-readelf] - Allow dumping of the .dynamic section even if there is no PT_DYNAMIC header.
It is now possible after D61937 was landed and was discussed
in it's review comments. It is not consistent with GNU, which
does not output .dynamic section content in this case for
no visible reason.
Differential revision: https://reviews.llvm.org/D62179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361943
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Cullen Rhodes [Wed, 29 May 2019 09:03:27 +0000 (09:03 +0000)]
[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
Summary:
Patch adds support for the following instructions:
* EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR
Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361936
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Cullen Rhodes [Wed, 29 May 2019 08:53:06 +0000 (08:53 +0000)]
[AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add
Summary:
Patch adds support for the indexed and unpredicated vectors forms of the
FMLALB, FMLALT, FMLSLB and FMLSLT instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361935
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Cullen Rhodes [Wed, 29 May 2019 08:40:33 +0000 (08:40 +0000)]
[AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise Group
Summary:
Patch adds support for the following instructions:
SVE2 floating-point pairwise operations:
* FADDP, FMAXNMP, FMINNMP, FMAXP, FMINP
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361933
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George Rimar [Wed, 29 May 2019 08:28:47 +0000 (08:28 +0000)]
[llvm-readobj/llvm-readelf] - Simplify the elf-versioninfo.test test case.
This removes 2 precompiled objects from the test case and replaces
them with a single YAML. That allowed to simplify and clean up the test,
remove excessive checks.
Differential revision: https://reviews.llvm.org/D62529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361932
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Fangrui Song [Wed, 29 May 2019 06:18:34 +0000 (06:18 +0000)]
[llvm-readobj] -u: don't crash when dumping SHT_ARM_EXIDX if .symtab doesn't exist
Reviewed By: kongyi
Differential Revision: https://reviews.llvm.org/D62567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361929
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Richard Trieu [Wed, 29 May 2019 04:09:32 +0000 (04:09 +0000)]
Inline a variable into debug section to fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361927
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Richard Trieu [Wed, 29 May 2019 03:43:01 +0000 (03:43 +0000)]
Inline value into debug statement to avoid unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361924
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Peter Collingbourne [Wed, 29 May 2019 03:29:01 +0000 (03:29 +0000)]
Add IR support, ELF section and user documentation for partitioning feature.
The partitioning feature was proposed here:
http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html
This is mostly just documentation. The feature itself will be contributed
in subsequent patches.
Differential Revision: https://reviews.llvm.org/D60242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361923
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Peter Collingbourne [Wed, 29 May 2019 03:28:51 +0000 (03:28 +0000)]
IR: Give the TypeAllocator a more generic name and start using it for section names as well. NFCI.
This prepares us to start using it for partition names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361922
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Jinsong Ji [Wed, 29 May 2019 03:02:59 +0000 (03:02 +0000)]
Support resource tracking with InstrSchedModel
The current design use DFA to do resource tracking in SMS,
and DFA only support InstrItins, and also has scaling limitation.
This patch extend SMS to allow Subtarget to use ProcResource in
InstrSchedModel instead.
Differential Revision: https://reviews.llvm.org/D62163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361919
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Pengfei Wang [Wed, 29 May 2019 02:49:59 +0000 (02:49 +0000)]
Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"
This reverts commit
c1b3716614bc0a107e6f41a7d3d503baefad8a5b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361918
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Pengfei Wang [Wed, 29 May 2019 02:20:37 +0000 (02:20 +0000)]
[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to
avoid static check fail
RegClassOrBank is an object of RegClassOrRegBank, which is defined as
using llvm::RegClassOrRegBank = typedef PointerUnion<const
TargetRegisterClass *, const RegisterBank *>
so control flow can not get here. Use ""llvm_unreachable" here to avoid
"null pointer" confusion.
Patch by Shengchen Kan (skan)
Differential Revision: https://reviews.llvm.org/D62006
Signed-off-by: pengfei <pengfei.wang@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361912
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Fangrui Song [Wed, 29 May 2019 02:02:59 +0000 (02:02 +0000)]
[X86] Fix x86-64 call *foo@tlsdesc(%rax) and support R_386_TLSGOTDESC R_386_TLS_DESC_CALL
D18885 emitted 5 bytes for call *foo@tlsdesc(%rax). It should use the
2-byte form instead and let R_X86_64_TLSDESC_CALL apply to the beginning
of the call instruction.
The 2-byte form was deliberately chosen to make ->LE and ->IE relaxation work:
0: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # 7 <.text+0x7>
3: R_X86_64_GOTPC32_TLSDESC a-0x4
7: ff 10 callq *(%rax)
7: R_X86_64_TLSDESC_CALL a
=>
0: 48 c7 c0 fc ff ff ff mov $0xfffffffffffffffc,%rax
7: 66 90 xchg %ax,%ax
Also change the symbol type to STT_TLS when VK_TLSCALL or VK_TLSDESC is
seen.
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D62512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361910
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Sanjay Patel [Wed, 29 May 2019 01:37:44 +0000 (01:37 +0000)]
[AArch64] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361908
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Sanjay Patel [Wed, 29 May 2019 01:35:10 +0000 (01:35 +0000)]
[AArch64] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361906
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Thomas Lively [Wed, 29 May 2019 01:06:00 +0000 (01:06 +0000)]
[WebAssembly] Add signatures for RINT builtins
Reviewers: azakai, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361904
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Quentin Colombet [Tue, 28 May 2019 23:43:12 +0000 (23:43 +0000)]
[RegUsageInfoCollector] Don't mark as saved registers that don't have subregister lanes
To determine the list of clobbered registers, the RegUsageInfoCollector pass
uses the list of callee saved registers provided by the target and then augments
it with the list of registers which have all their subregisters saved. It then
basically does the difference between all the registers and the saved registers
to come up with what is clobbered (plus it checks that the register is defined
within that functions).
The patch fixes a bug where when register does not have any subregister lane,
hence when checking if any of its subregister are not saved, we would find none
and think the register is saved as well.
That's obviously wrong.
The code was actually kind of checking for something like that with the
CoveredBySubRegs bit. What this bit says is that a register is completely
covered by its subregisters.
We required that this bit was set, to check that a register was saved by its
subregister lanes, since without this bit, we potentially would miss to check
some part of the register.
However, this bit is used de facto on registers that don't have any
subregisters (e.g., on ARM) and the code was not prepared for that.
This patch fixes this by checking that a register has subregisters before
declaring it saved when none of its lanes are modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361901
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Lang Hames [Tue, 28 May 2019 23:35:44 +0000 (23:35 +0000)]
[ORC] Track JIT symbol states more explicitly.
Prior to this patch, JITDylibs inferred symbol states (whether a symbol was
newly added, materializing, resolved, or ready to run) via a combination of (1)
bits in the JITSymbolFlags member, and (2) the state of some internal JITDylib
data structures. This patch explicitly tracks symbol states by adding a new
SymbolState member to the symbol table entries, and removing the 'Lazy' and
'Materializing' bits from JITSymbolFlags. This is a first step towards adding
additional states representing initialization phases (e.g. eh-frame registration,
registration with the language runtime, and static initialization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361899
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Alexander Shaposhnikov [Tue, 28 May 2019 23:22:12 +0000 (23:22 +0000)]
[tools] Introduce llvm-lipo
This diff starts the implementation of llvm-lipo
which is supposed to be a drop-in replacement for the well-known tool lipo.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D61927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361896
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Jessica Paquette [Tue, 28 May 2019 22:52:49 +0000 (22:52 +0000)]
[AArch64][GlobalISel] Select FCMPSri/FCMPDri when comparing against 0.0
Add support for selecting FCMPSri and FCMPDri when comparing against 0.0, and
factor out opcode selection for G_FCMP into its own function.
Add a test to show that we don't do this with other immediates.
Differential Revision: https://reviews.llvm.org/D62539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361888
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Heejin Ahn [Tue, 28 May 2019 22:09:12 +0000 (22:09 +0000)]
[WebAssembly] Support for atomic fences
Summary:
This adds support for translation of LLVM IR fence instruction. We
convert a singlethread fence to a pseudo compiler barrier which becomes
0 instructions in final binary, and a thread fence to an idempotent
atomicrmw instruction to a memory address.
Reviewers: dschuff, jfb, sunfish, tlively
Subscribers: sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D50277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361884
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Rong Xu [Tue, 28 May 2019 21:45:56 +0000 (21:45 +0000)]
[PGO] Handle cases of failing to split critical edges
Fix PR41279 where critical edges to EHPad are not split.
The fix is to not instrument those critical edges. We used to be able to know
the size of counters right after MST is computed. With this, we have to
pre-collect the instrument BBs to know the size, and then instrument them.
Differential Revision: https://reviews.llvm.org/D62439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361882
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Nikita Popov [Tue, 28 May 2019 21:28:24 +0000 (21:28 +0000)]
Revert "[CorrelatedValuePropagation] Fix prof branch_weights metadata handling for SwitchInst"
This reverts commit
53f2f3286572cb879b3861d7c15480e4d830dd3b.
As reported on D62126, this causes assertion failures if the switch
has incorrect branch_weights metadata, which may happen as a result
of other transforms not handling it correctly yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361881
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Konstantin Zhuravlyov [Tue, 28 May 2019 21:18:34 +0000 (21:18 +0000)]
AMDGPU: Temporary drop s_mul_hi_i/u32 patterns
It introduces performance regressions in several applications.
This has already been submitted downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361879
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Adhemerval Zanella [Tue, 28 May 2019 21:04:29 +0000 (21:04 +0000)]
[AArch64] Handle ISD::LRINT and ISD::LLRINT
This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.
Reviewed By: SjoerdMeijer, mstorsjo
Differential Revision: https://reviews.llvm.org/D62018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361877
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Adhemerval Zanella [Tue, 28 May 2019 20:47:44 +0000 (20:47 +0000)]
[CodeGen] Add lrint/llrint builtins
This patch add the ISD::LRINT and ISD::LLRINT along with new
intrinsics. The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an interger.
The idea is to optimize lrint/llrint generation for AArch64
in a subsequent patch. Current semantic is just route it to libm
symbol.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D62017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361875
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Roman Lebedev [Tue, 28 May 2019 20:40:10 +0000 (20:40 +0000)]
[DAGCombine] (x - C) - y -> (x - y) - C fold. Try 2
Summary:
Again only vectors affected. Frustrating. Let me take a look into that..
https://rise4fun.com/Alive/AAq
This is a recommit, originally committed in rL361856, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: javed.absar, JDevlieghere, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361874
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Roman Lebedev [Tue, 28 May 2019 20:40:03 +0000 (20:40 +0000)]
[DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 2
Summary:
This prevents regressions in next patch,
and somewhat recovers from the regression to AMDGPU test in D62223.
It is indeed not great that we leave vector decrement,
don't transform it into vector add all-ones..
https://rise4fun.com/Alive/ZRl
This is a recommit, originally committed in rL361855, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel, arsenm
Reviewed By: RKSimon, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361873
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Roman Lebedev [Tue, 28 May 2019 20:39:55 +0000 (20:39 +0000)]
[DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold. Try 2
Summary:
Direct sibling of D62223 patch.
While i don't have a direct motivational pattern for this,
it would seem to make sense to handle both patterns (or none),
for symmetry?
The aarch64 changes look neutral;
sparc and systemz look like improvement (one less instruction each);
x86 changes - 32bit case improves, 64bit case shows that LEA no longer
gets constructed, which may be because that whole test is `-mattr=+slow-lea,+slow-3ops-lea`
https://rise4fun.com/Alive/ffh
This is a recommit, originally committed in rL361853, but reverted
to investigate test-suite compile-time hangs.
Reviewers: RKSimon, craig.topper, spatel, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, jyknight, javed.absar, kristof.beyls, fedor.sergeev, jrtc27, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361872
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