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Hiroshi Yamauchi [Mon, 31 Mar 2014 22:14:47 +0000 (15:14 -0700)]
Make the support code for read barriers a bit more general.
Add an option for Baker in addition to Brooks.
Bug:
12687968
Change-Id: I8a31db817ff6686c72951b6534f588228e270b11
Hiroshi Yamauchi [Mon, 31 Mar 2014 18:34:45 +0000 (18:34 +0000)]
Merge "Fix a DCHECK failure when causing GC from DDMS."
Vladimir Marko [Mon, 31 Mar 2014 16:36:03 +0000 (16:36 +0000)]
Merge "Mark ScopedArenaAllocator's allocations undefined for Valgrind."
Vladimir Marko [Mon, 31 Mar 2014 16:16:36 +0000 (16:16 +0000)]
Merge "Faster AssembleLIR for ARM."
Vladimir Marko [Mon, 31 Mar 2014 14:32:56 +0000 (15:32 +0100)]
Mark ScopedArenaAllocator's allocations undefined for Valgrind.
Bug:
13659516
Change-Id: Id538c1bb1d256173a1f3db5ae0be920420da6d5d
Vladimir Marko [Tue, 7 Jan 2014 18:21:20 +0000 (18:21 +0000)]
Faster AssembleLIR for ARM.
This also reduces sizeof(LIR) by 4 bytes (32-bit builds).
Change-Id: I0cb81f9bf098dfc50050d5bc705c171af26464ce
Nicolas Geoffray [Mon, 31 Mar 2014 10:44:46 +0000 (10:44 +0000)]
Merge "Add support for adding two integers in optimizing compiler."
Nicolas Geoffray [Fri, 28 Mar 2014 15:43:40 +0000 (15:43 +0000)]
Add support for adding two integers in optimizing compiler.
Change-Id: I5524e193cd07f2692a57c6b4f8069904471b2928
Narayan Kamath [Mon, 31 Mar 2014 10:03:07 +0000 (10:03 +0000)]
Merge "Remove use of pthread_cond_timedwait_monotonic."
Nicolas Geoffray [Mon, 31 Mar 2014 09:15:30 +0000 (09:15 +0000)]
Merge "Add support for invoke-static in optimizing compiler."
Nicolas Geoffray [Wed, 19 Mar 2014 10:34:11 +0000 (10:34 +0000)]
Add support for invoke-static in optimizing compiler.
Support is limited to calls without parameters and returning
void. For simplicity, we currently follow the Quick ABI.
Change-Id: I54805161141b7eac5959f1cae0dc138dd0b2e8a5
Brian Carlstrom [Sun, 30 Mar 2014 23:34:51 +0000 (23:34 +0000)]
Merge "No longer restrict to -source 1.5 since it causes a warning with 1.7"
Brian Carlstrom [Sun, 30 Mar 2014 23:17:42 +0000 (16:17 -0700)]
No longer restrict to -source 1.5 since it causes a warning with 1.7
(cherry picked from commit
e17838ffedee1796920636c2f99c933aa1ce4b3c)
Change-Id: Ied11738da9621280185a62f267a5d527e6ed927b
Mathieu Chartier [Fri, 28 Mar 2014 23:34:51 +0000 (23:34 +0000)]
Merge "Fix non concurrent mark sweep ergonomics."
Mathieu Chartier [Fri, 28 Mar 2014 23:22:20 +0000 (16:22 -0700)]
Fix non concurrent mark sweep ergonomics.
Previously we would continue to do sticky GC until the sticky GC did
not free enough memory for the allocation, this was excessive since it
could do one sticky GC per allocation. The new logic uses the next GC
type before trying all the GCs in the plan.
Before memalloc benchmark (non concurrent mark sweep):
Total time spent in GC: 11.212701s
Score: 7790
After:
Total time spent in GC: 9.422676s
Score: 6870
Change-Id: Iba75b70ea825ef3fd4b3e064d4f12c2fe5a3b176
Jeff Hao [Fri, 28 Mar 2014 23:03:21 +0000 (23:03 +0000)]
Merge "Some fixes for comments and implied conversions."
Jeff Hao [Fri, 28 Mar 2014 22:43:37 +0000 (15:43 -0700)]
Some fixes for comments and implied conversions.
Addresses comments in:
https://android-review.googlesource.com/#/c/89148/3
Change-Id: If21cfaa541210c8702371efd1e6d4f071a7b9ec3
Hiroshi Yamauchi [Fri, 28 Mar 2014 22:26:48 +0000 (15:26 -0700)]
Fix a DCHECK failure when causing GC from DDMS.
Bug:
13647069
Change-Id: Iae2746b2b7b4493fcf5f0d40d2bf36a9b2d2efc8
Mathieu Chartier [Fri, 28 Mar 2014 22:20:25 +0000 (22:20 +0000)]
Merge "Swap allocation stacks in pause."
Jeff Hao [Fri, 28 Mar 2014 21:41:16 +0000 (21:41 +0000)]
Merge "Add access checks to Method and Field reflection."
Jeff Hao [Wed, 26 Mar 2014 22:08:20 +0000 (15:08 -0700)]
Add access checks to Method and Field reflection.
Art side of this change. Has a corresponding libcore change.
Bug:
13620925
Change-Id: Ie67f802a2a400e8212b489b9a261b7028422d8ba
Mathieu Chartier [Fri, 28 Mar 2014 17:05:39 +0000 (10:05 -0700)]
Swap allocation stacks in pause.
This enables us to collect objects allocated during the GC for both
sticky, partial, and full GC. This also significantly simplifies GC
code. No measured performance impact on benchmarks, but this should
slightly increase sticky GC throughput.
Changed RevokeRosAllocThreadLocalBuffers to happen at most once per
GC. Previously it occured twice if pre-cleaning was enabled.
Renamed HandleDirtyObjectsPhase to PausePhase and enabled it for
non-concurrent GC. This helps reduce duplicated code which was in
both HandleDirtyObjectsPhase for concurrent GC and ReclaimPhase for
non-concurrent GC.
Change-Id: I533414b5c2cd2800f00724418e0ff90e7fdb0252
Mathieu Chartier [Fri, 28 Mar 2014 18:54:08 +0000 (18:54 +0000)]
Merge "Refactor some GC code."
Hiroshi Yamauchi [Fri, 28 Mar 2014 18:35:27 +0000 (18:35 +0000)]
Merge "An empty collector skeleton for a read barrier-based collector."
Mathieu Chartier [Thu, 27 Mar 2014 23:09:46 +0000 (16:09 -0700)]
Refactor some GC code.
Reduced amount of code in mark sweep / semi space by moving
common logic to garbage_collector.cc. Cleaned up mod union tables
and deleted an unused implementation.
Change-Id: I4bcc6ba41afd96d230cfbaf4d6636f37c52e37ea
Andreas Gampe [Fri, 28 Mar 2014 17:44:50 +0000 (17:44 +0000)]
Merge "x86_64: JNI compiler"
Sebastien Hertz [Fri, 28 Mar 2014 14:14:12 +0000 (14:14 +0000)]
Merge "Properly dump register type in verifier failure messages"
Sebastien Hertz [Fri, 28 Mar 2014 13:34:28 +0000 (14:34 +0100)]
Properly dump register type in verifier failure messages
Fixes failure messages where we miss to dereference pointer to RegType. This
caused to dump the address of the reg type instead of the reg type itself.
Also moves merging tests of primitive types from RegTypeReferenceTest to
RegTypeTest class.
Change-Id: I71cea419fdaa9ac46d7c011eb23e8746a14fb378
Bill Buzbee [Fri, 28 Mar 2014 13:02:49 +0000 (13:02 +0000)]
Merge "Annotate Dalvik VR access as both use and def if we use it in this way"
Dmitry Petrochenko [Fri, 21 Mar 2014 04:21:37 +0000 (11:21 +0700)]
x86_64: JNI compiler
Passed all tests from jni_compiler_test and art/test on host with jni_copiler.
Incoming argument spill is enabled, entry_spills refactored. Now each entry spill
contains data type size (4 or 8) and offset which should be used for spill.
Assembler REX support implemented in opcodes used in JNI compiler.
Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875).
Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Serguei Katkov [Thu, 27 Mar 2014 07:41:56 +0000 (14:41 +0700)]
Annotate Dalvik VR access as both use and def if we use it in this way
Some 2addr operations use direct access to VR in memory as both def and use but
annotate its only as def. It results in later optimizations like reorder
of LIRs can re-order this operation with other mov.
Change-Id: I04ac40c9f229af6f1e5c5f91f4901b1452509582
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Hiroshi Yamauchi [Fri, 28 Mar 2014 04:07:51 +0000 (21:07 -0700)]
An empty collector skeleton for a read barrier-based collector.
Bug:
12687968
Change-Id: Ic2a3a7b9943ca64e7f60f4d6ed552a316ea4a6f3
Brian Carlstrom [Fri, 28 Mar 2014 00:24:17 +0000 (00:24 +0000)]
Merge "Revert "Optimize easy multiply and easy div remainder.""
Brian Carlstrom [Fri, 28 Mar 2014 00:24:09 +0000 (00:24 +0000)]
Merge "Error when taking the modulo of the length of an array"
Brian Carlstrom [Fri, 28 Mar 2014 00:14:26 +0000 (17:14 -0700)]
Revert "Optimize easy multiply and easy div remainder."
This reverts commit
08df4b3da75366e5db37e696eaa7e855cba01deb.
Brian Carlstrom [Thu, 27 Mar 2014 23:54:27 +0000 (16:54 -0700)]
Error when taking the modulo of the length of an array
Bug:
13679511
Change-Id: I4c694a9d85727af8095091c42f1ac00a78ba4ea2
Bill Buzbee [Thu, 27 Mar 2014 22:56:48 +0000 (22:56 +0000)]
Merge "Fix CopyRegInfo to keep live/dirty flags of new registers."
Chao-ying Fu [Thu, 27 Mar 2014 21:17:28 +0000 (14:17 -0700)]
Fix CopyRegInfo to keep live/dirty flags of new registers.
CopyRegInfo should not change live/dirty flags of new registgers.
Otherwise, it will lead to incorrectly clobbering these live registers
that are not live actually, and then allocating them to another usage.
Change-Id: Ia9f055b33a11a6d70c0aca1a9fe8639ecfb09464
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Mathieu Chartier [Thu, 27 Mar 2014 22:35:27 +0000 (22:35 +0000)]
Merge "Change sticky GC ergonomics to use GC throughput."
Mathieu Chartier [Thu, 27 Mar 2014 17:55:04 +0000 (10:55 -0700)]
Change sticky GC ergonomics to use GC throughput.
The old sticky ergonomics used partial/full GC when the bytes until
the footprint limit was < min free. This was suboptimal. The new
sticky GC ergonomics do partial/full GC when the throughput
of the current sticky GC iteration is <= mean throughput of the
partial/full GC.
Total GC time on FormulaEvaluationActions.EvaluateAndApplyChanges.
Before: 26.4s
After: 24.8s
No benchmark score change measured.
Bug:
8788501
Change-Id: I90000305e93fd492a8ef5a06ec9620d830eaf90d
Ian Rogers [Thu, 27 Mar 2014 21:36:12 +0000 (21:36 +0000)]
Merge "Remove bogus DCHECK."
Ian Rogers [Thu, 27 Mar 2014 21:27:09 +0000 (14:27 -0700)]
Remove bogus DCHECK.
Bug:
13637540
Change-Id: I39f19443156cf5bdc26e3eeb0bb501a850d40dca
buzbee [Thu, 27 Mar 2014 19:24:15 +0000 (19:24 +0000)]
Merge "Fix x86 master build failure."
buzbee [Thu, 27 Mar 2014 18:22:43 +0000 (11:22 -0700)]
Fix x86 master build failure.
Replace bogus DCHECKs with logic matching pre-cleanup code.
Register pairs are considered temp, promoted, dirty or live if
either register of the pair meets criteria.
Change-Id: If2df891fdd1e3351d4cbe72aaf2a2ac5b34b2110
Sebastien Hertz [Thu, 27 Mar 2014 15:42:30 +0000 (15:42 +0000)]
Merge "Support inlining with breakpoint"
Andreas Gampe [Thu, 27 Mar 2014 15:25:32 +0000 (15:25 +0000)]
Merge "Last patch for running tests on ARM64"
Sebastien Hertz [Thu, 20 Mar 2014 15:40:17 +0000 (16:40 +0100)]
Support inlining with breakpoint
When installing/uninstalling a breakpoint in a method, we fully or selectively
deoptimize/undeoptimize depending on whether the method can be inlined. When
the method can be inlined, it requires full deoptimization. Otherwise, it only
requires selective deoptimization.
We add sanity check to control we are in a consistent state each time we add or
remove a breakpoint. We also add some comments to better describe the process
of deoptimization for breakpoint.
Bug:
12187616
Change-Id: Id15adc6e5e2fe783c83c925cbcd19ae02431b7e0
Ian Rogers [Thu, 27 Mar 2014 15:18:37 +0000 (15:18 +0000)]
Merge "Handle Array::Memmove within the same array properly."
Ian Rogers [Thu, 27 Mar 2014 05:53:56 +0000 (22:53 -0700)]
Handle Array::Memmove within the same array properly.
Motivated by discussions in:
https://android-review.googlesource.com/#/c/88940/
memcpy can't be relied upon to be a forward copy for overlapping regions of
memory.
Change-Id: I409f75e97204250546bf0b8082e2b62026bddedc
Andreas Gampe [Wed, 26 Mar 2014 21:53:21 +0000 (14:53 -0700)]
Last patch for running tests on ARM64
This allows all run-tests to succeed with the interpreter+GenJNI
setup.
Change-Id: I45734e7e57340439369a613ef4329e3be2c0c4c9
Ian Rogers [Thu, 27 Mar 2014 15:00:08 +0000 (15:00 +0000)]
Merge "Reflection tidying."
Bill Buzbee [Thu, 27 Mar 2014 13:08:19 +0000 (13:08 +0000)]
Merge "Optimize easy multiply and easy div remainder."
Sebastien Hertz [Thu, 27 Mar 2014 07:46:58 +0000 (07:46 +0000)]
Merge "Refactor deoptimization support in debugger"
Sebastien Hertz [Thu, 27 Mar 2014 07:42:07 +0000 (07:42 +0000)]
Merge "Do not suspend current thread to build stacktrace from DDMS"
Sebastien Hertz [Tue, 25 Mar 2014 16:53:48 +0000 (17:53 +0100)]
Do not suspend current thread to build stacktrace from DDMS
Avoids a failing CHECK in ThreadList::SuspendThreadByThreadId in the case we
try to suspend the current thread.
Bug:
12985512
Change-Id: I9434400a3625319855dd3841d8889117e57784e5
Sebastien Hertz [Thu, 27 Mar 2014 07:36:59 +0000 (07:36 +0000)]
Merge "Fix alloc tracker locking issue"
Ian Rogers [Thu, 27 Mar 2014 06:52:41 +0000 (23:52 -0700)]
Reflection tidying.
Move out arguments to the right and make pointer not reference types.
Remove unused unbox for argument routine.
Simplify convert primitive routine for the case of identical types.
Change-Id: I6456331b0f3f3e5f0b2c361a9f50b4ed1c9462a3
Zheng Xu [Tue, 25 Mar 2014 14:25:52 +0000 (14:25 +0000)]
Optimize easy multiply and easy div remainder.
Update OpRegRegShift and OpRegRegRegShift to use RegStorage parameters.
Add special cases for *0 and *1. Add more easy multiply special cases for
Arm.
Reuse easy multiply in SmallLiteralDivRem() to support remainder cases.
Change-Id: Icd76a993d3ac8d4988e9653c19eab4efca14fad0
buzbee [Thu, 27 Mar 2014 03:22:33 +0000 (03:22 +0000)]
Merge "Continuing register cleanup"
buzbee [Fri, 7 Mar 2014 17:46:20 +0000 (09:46 -0800)]
Continuing register cleanup
Ready for review.
Continue the process of using RegStorage rather than
ints to hold register value in the top layers of codegen.
Given the huge number of changes in this CL, I've attempted
to minimize the number of actual logic changes. With this
CL, the use of ints for registers has largely been eliminated
except in the lowest utility levels. "Wide" utility routines
have been updated to take a single RegStorage rather than
a pair of ints representing low and high registers.
Upcoming CLs will be smaller and more targeted. My expectations:
o Allocate float double registers as a single double rather than
a pair of float single registers.
o Refactor to push code which assumes long and double Dalvik
values are held in a pair of register to the target dependent
layer.
o Clean-up of the xxx_mir.h files to reduce the amount of #defines
for registers. May also do a register renumbering to bring all
of our targets' register naming more consistent. Possibly
introduce a target-independent float/non-float test at the
RegStorage level.
Change-Id: I646de7392bdec94595dd2c6f76e0f1c4331096ff
Mathieu Chartier [Thu, 27 Mar 2014 01:03:10 +0000 (01:03 +0000)]
Merge "Less redundant verification."
Mathieu Chartier [Wed, 26 Mar 2014 22:15:57 +0000 (15:15 -0700)]
Less redundant verification.
~3 less objects verified per object scanned in the GC. Helps the
irogers dogfood experience.
Change-Id: I6efeab7842a6c702adecef73fb573c19291fecf2
Ian Rogers [Wed, 26 Mar 2014 23:25:14 +0000 (23:25 +0000)]
Merge "Relaxed memory barriers for x86"
Mathieu Chartier [Wed, 26 Mar 2014 23:21:33 +0000 (23:21 +0000)]
Merge "Add valgrind support to large object map space."
Razvan A Lupusoru [Wed, 26 Feb 2014 01:41:08 +0000 (17:41 -0800)]
Relaxed memory barriers for x86
X86 provides stronger memory guarantees and thus the memory barriers can be
optimized. This patch ensures that all memory barriers for x86 are treated
as scheduling barriers. And in cases where a barrier is needed (StoreLoad case),
an mfence is used.
Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Mathieu Chartier [Wed, 26 Mar 2014 19:53:19 +0000 (12:53 -0700)]
Add valgrind support to large object map space.
Added valgrind support to large object map space.
Bug:
7392044
Change-Id: I1456f46414e1fa59ebcc2190ec00576dae26d623
Ian Rogers [Wed, 26 Mar 2014 22:07:11 +0000 (22:07 +0000)]
Merge "Reuse promoted register temporarily"
Yevgeny Rouban [Tue, 18 Mar 2014 08:55:16 +0000 (15:55 +0700)]
Reuse promoted register temporarily
AtomicLong (x86) is implemented as an intrinsic, which uses
the cmpxchng8b instruction.
This instruction requires 4 physical registers plus 2 more used for
the memory operand. On x86 we have only 4 temporaries. The code tried
to solve this by using MarkTemp utility, but this was not meant to be
used with promoted registers. The problem is that MarkTemp does not
spill anything and as a result we can lose VR.
If the registers are promoted this patch just reuses the values pushed
on the stack.
Change-Id: Ifec9183e2483cf704d0d1166a1004a9aa07b4f1d
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
Mathieu Chartier [Wed, 26 Mar 2014 16:51:02 +0000 (16:51 +0000)]
Merge "Add GC mode for stressing testing heap transitions."
Bill Buzbee [Wed, 26 Mar 2014 13:28:02 +0000 (13:28 +0000)]
Merge "x86 GenLongRegOrMemOp should be aware about xmm to core reg conversion"
Sebastien Hertz [Fri, 21 Mar 2014 16:44:46 +0000 (17:44 +0100)]
Refactor deoptimization support in debugger
This CL prepares breakpoint support for inlined methods where we'll have to
deoptimize everything.
We move deoptimization-related information to Dbg class only (deoptimization
request queue, full deoptimization event count and deoptimization lock). We
replace MethodInstrumentionRequest by DeoptimizationRequest. This is used to
know which kind of deoptimization is required for a particular event.
It also simplifies lock ordering a bit during event setup: we no longer need to
hold the deoptimization lock while holding the breakpoint lock. Moreover, the
deoptimization lock should be held only after the event list lock.
Bug:
12187616
Change-Id: Iff13f004adaeb25e5d609238bacce0b9720510e6
Sebastien Hertz [Wed, 26 Mar 2014 09:57:20 +0000 (10:57 +0100)]
Fix alloc tracker locking issue
Fixes a lock level violation where we attempt to take the thread list lock
while already holding the alloc tracker lock. We now avoid holding the alloc
tracker lock when updating allocation entrypoints.
Bug:
13646642
Change-Id: Iab505dae67d0c754031fe30d50a7cbd5e4ba5785
Serguei Katkov [Tue, 25 Mar 2014 03:51:15 +0000 (10:51 +0700)]
x86 GenLongRegOrMemOp should be aware about xmm to core reg conversion
GenLongRegOrMemOp function expects arithmetic on core regs but does not
ensure that operand in core reg.
The patch adds the conversion if it is required.
Change-Id: Ibb6928b8cc2c63ede1a20d6ee45d9a64884231b6
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Brian Carlstrom [Tue, 25 Mar 2014 23:56:15 +0000 (23:56 +0000)]
Merge "Fix host gtests compiled with gcc"
Brian Carlstrom [Tue, 25 Mar 2014 23:23:56 +0000 (16:23 -0700)]
Fix host gtests compiled with gcc
(cherry picked from commit
d016e1fab648093706f85cc78b63da0f3f487733)
Change-Id: I5d2b8061278fd5a477ec87395fca435a3da801a3
Mathieu Chartier [Tue, 25 Mar 2014 22:58:50 +0000 (15:58 -0700)]
Add GC mode for stressing testing heap transitions.
The stress testing mode does repeated heap transitions when the heap
gets a process state update. In between each transition, the heap
waits for a specified number of time.
Change-Id: Ie3f43835e539fa8da147f77b4623a432a0d858c2
Mathieu Chartier [Tue, 25 Mar 2014 21:49:35 +0000 (21:49 +0000)]
Merge "Add missing debugger root visiting."
Mathieu Chartier [Tue, 25 Mar 2014 16:29:43 +0000 (09:29 -0700)]
Add missing debugger root visiting.
Bug:
13634574
Change-Id: I2a76f6c43f1d0ad1922f06deb40a71ff651129fd
Dmitriy Ivanov [Tue, 25 Mar 2014 19:33:06 +0000 (19:33 +0000)]
Merge "Fix imm5 and shift_type detection"
Tim Murray [Tue, 25 Mar 2014 18:49:20 +0000 (18:49 +0000)]
Merge "Fix missing link line for libgtest_host."
Dmitriy Ivanov [Tue, 25 Mar 2014 17:31:04 +0000 (10:31 -0700)]
Fix imm5 and shift_type detection
Bug:
13628315
Change-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9
Andreas Gampe [Tue, 25 Mar 2014 14:58:31 +0000 (14:58 +0000)]
Merge "Trampoline and assembly fixes for ARM64"
Bill Buzbee [Tue, 25 Mar 2014 14:29:50 +0000 (14:29 +0000)]
Merge "An argument is handled incorrectly for add-int/lit8 during optimization phase"
Bill Buzbee [Tue, 25 Mar 2014 14:29:33 +0000 (14:29 +0000)]
Merge "Small update to CFG printing using DOT"
nikolay serdjuk [Tue, 25 Mar 2014 05:21:29 +0000 (12:21 +0700)]
An argument is handled incorrectly for add-int/lit8 during optimization phase
Dalvik instruction 'add-int/lit8' stores a constant in the third parameter.
But during optimization phase the compiler reads the constant from the
second parameter. This is incorrect because it leads to wrong decision that
no array bound checks are needed in our test case. As a consequence it
fails with SIGSEGV because of accessing elements which are beyond the bounds.
Change-Id: I653892514934046d31a9e4d206d9d95ebb6267ab
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
Mathieu Chartier [Tue, 25 Mar 2014 01:13:52 +0000 (01:13 +0000)]
Merge "Refactor image writer reference visiting logic."
Mathieu Chartier [Mon, 24 Mar 2014 23:54:46 +0000 (16:54 -0700)]
Refactor image writer reference visiting logic.
Now uses Object::VisitReferences.
Change-Id: I5a4557e10796d6f34596f2e8796ad9382121c567
Andreas Gampe [Mon, 24 Mar 2014 23:45:44 +0000 (16:45 -0700)]
Trampoline and assembly fixes for ARM64
Trampolines need a jump, not a call. Expose br in the ARM64
assembler to allow this.
The resolution trampoline is called with the Quick ABI, and will
continue to a Quick ABI function. Then the method pointer must be
in x0.
Change-Id: I4e383b59d6c40a659d324a7faef3fadf0c890178
Mathieu Chartier [Mon, 24 Mar 2014 23:39:22 +0000 (23:39 +0000)]
Merge "Refactor object reference visiting logic."
Mathieu Chartier [Tue, 18 Feb 2014 22:37:05 +0000 (14:37 -0800)]
Refactor object reference visiting logic.
Refactored the reference visiting logic to be in mirror::Object
instead of MarkSweep.
Change-Id: I773249478dc463d83b465e85c2402320488577c0
Andreas Gampe [Mon, 24 Mar 2014 18:53:17 +0000 (18:53 +0000)]
Merge "Fixes to mem_map wraparound and ARM64 quick_invoke assembly"
Andreas Gampe [Mon, 24 Mar 2014 18:27:39 +0000 (18:27 +0000)]
Merge "Avoid strerror until we are sure there is an error"
Brian Carlstrom [Mon, 24 Mar 2014 06:47:25 +0000 (23:47 -0700)]
Avoid strerror until we are sure there is an error
Change-Id: I8f0c5a9cb1b07bfffd5ce9f9ca33f53c8834e9f5
Mathieu Chartier [Mon, 24 Mar 2014 16:52:54 +0000 (16:52 +0000)]
Merge "Refactor and optimize GC code."
Mathieu Chartier [Thu, 20 Mar 2014 19:41:23 +0000 (12:41 -0700)]
Refactor and optimize GC code.
Fixed the reference cache mod union table, and re-enabled it by
default. Added a boolean flag to count how many null objects,
immune, fast path, slow path objects we marked.
Slight speedup in mark stack processing, large speedup in image mod
union table scanning.
EvaluateAndApplyChanges Before:
Process mark stack time for full GC only:
12.464089s, 12.357870s, 12.538028s
Time spent marking mod image union table ~240ms.
After:
Process mark stack time: 12.299375s, 12.217142s, 12.187076s
Time spent marking mod image union table ~40ms.
TODO: Refactor reference visiting logic into mirror::Object.
Change-Id: I91889ded9d3f2bf127bc0051c1b1ff77e792e94f
Andreas Gampe [Sat, 22 Mar 2014 00:25:57 +0000 (17:25 -0700)]
Fixes to mem_map wraparound and ARM64 quick_invoke assembly
There are only 6 free GPRs for passing in a non-static invoke. This
corrupted one register for long-signature methods.
The wrap-around did not actually wrap around correctly.
Change-Id: I62658dadeb83bb22960b9455e211d26ffaa20f6f
Hiroshi Yamauchi [Fri, 21 Mar 2014 23:30:33 +0000 (23:30 +0000)]
Merge "Deduplicate the code that hardcodes the array header layout."
Hiroshi Yamauchi [Fri, 21 Mar 2014 23:18:30 +0000 (16:18 -0700)]
Deduplicate the code that hardcodes the array header layout.
Get rid of HeaderSize() in array-inl.h and use DataOffset() instead.
Bug:
12687968
Change-Id: Ic81cf3fa6bb9b2440d351a73f5fd6a2d6908d15b
Hiroshi Yamauchi [Fri, 21 Mar 2014 23:25:42 +0000 (23:25 +0000)]
Merge "Revoke rosalloc thread-local buffers at the checkpoint."
Mathieu Chartier [Fri, 21 Mar 2014 22:49:00 +0000 (22:49 +0000)]
Merge "Don't return null for null utf in AllocFromModifiedUtf8."