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James Molloy [Thu, 3 Nov 2016 14:08:01 +0000 (14:08 +0000)]
Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"
This reverts commit r285893. It caused (probably) http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/83 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285912
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Rafael Espindola [Thu, 3 Nov 2016 13:58:15 +0000 (13:58 +0000)]
replace a report_fatal_error with a ErrorOr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285910
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John Brawn [Thu, 3 Nov 2016 13:55:04 +0000 (13:55 +0000)]
[CMake] Make CMAKE_INSTALL_RPATH work again
r285714 made it so that when CMAKE_INSTALL_RPATH is set _install_rpath is not
set, but that means INSTALL_RPATH gets set to an empty string which isn't what
we want. Fix this by setting INSTALL_RPATH only when _install_rpath is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285908
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Rafael Espindola [Thu, 3 Nov 2016 13:43:30 +0000 (13:43 +0000)]
Replace a report_fatal_error with an ErrorOr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285905
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Rafael Espindola [Thu, 3 Nov 2016 13:22:51 +0000 (13:22 +0000)]
Split getStringTableForSymtab.
For use in cases where we already have the section table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285903
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Rafael Espindola [Thu, 3 Nov 2016 12:23:41 +0000 (12:23 +0000)]
Split getSHNDXTable in two.
Some clients already have the section table available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285898
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James Molloy [Thu, 3 Nov 2016 10:18:20 +0000 (10:18 +0000)]
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently
This recommits r281323, which was backed out for two reasons. One, a selfhost failure, and two, it apparently caused Chromium failures. Actually, the latter was a red herring. The log has expired from the former, but I suspect that was a red herring too (actually caused by another problematic patch of mine). Therefore reapplying, and will watch the bots like a hawk.
For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).
1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.
2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.
3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).
4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.
1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285893
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George Rimar [Thu, 3 Nov 2016 08:41:46 +0000 (08:41 +0000)]
[tools/obj2yaml] - Update after LLVM change r285886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285887
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George Rimar [Thu, 3 Nov 2016 08:40:55 +0000 (08:40 +0000)]
[Object/ELF] - Make getSymbol() return Error.
That is consistent with other methods around
and helps to handle error on a caller side.
Differential revision: https://reviews.llvm.org/D26247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285886
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Jonas Hahnfeld [Thu, 3 Nov 2016 06:58:16 +0000 (06:58 +0000)]
[CMake] Disable rpath for UnitTests
This was broken since rL285714.
Differential Revision: https://reviews.llvm.org/D26246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285881
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Craig Topper [Thu, 3 Nov 2016 06:04:28 +0000 (06:04 +0000)]
[AVX-512] Use 'vnot' instead of 'not' in patterns involving vXi1 vectors.
This fixes selection of KANDN instructions and allows us to remove an extra set of patterns for KNOT and KXNOR.
Reviewers: delena, igorb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285878
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Elena Demikhovsky [Thu, 3 Nov 2016 03:23:55 +0000 (03:23 +0000)]
Expandload and Compressstore intrinsics
2 new intrinsics covering AVX-512 compress/expand functionality.
This implementation includes syntax, DAG builder, operation lowering and tests.
Does not include: handling of illegal data types, codegen prepare pass and the cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285876
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Rafael Espindola [Thu, 3 Nov 2016 02:24:59 +0000 (02:24 +0000)]
Split getSection in two.
This will allow avoiding repeated error checking in a few cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285874
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Teresa Johnson [Thu, 3 Nov 2016 01:07:16 +0000 (01:07 +0000)]
[ThinLTO] Handle distributed backend case when doing renaming
Summary:
The recent change I made to consult the summary when deciding whether to
rename (to handle inline asm) in r285513 broke the distributed build
case. In a distributed backend we will only have a portion of the
combined index, specifically for imported modules we only have the
summaries for any imported definitions. When renaming on import we were
asserting because no summary entry was found for a local reference being
linked in (def wasn't imported).
We only need to consult the summary for a renaming decision for the
exporting module. For imports, we would have prevented importing any
references to NoRename values already.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285871
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Greg Bedwell [Wed, 2 Nov 2016 23:17:05 +0000 (23:17 +0000)]
Revert "[InstCombine] allow splat vector folds in adjustMinMax()"
This reverts commit r285732.
This change introduced a new assertion failure in the following
testcase at -O2:
typedef short __v8hi __attribute__((__vector_size__(16)));
__v8hi foo(__v8hi &V1, __v8hi &V2, unsigned mask) {
__v8hi Result = V1;
if (mask & 0x80)
Result[0] = V2[0];
return Result;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285866
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Rafael Espindola [Wed, 2 Nov 2016 21:39:02 +0000 (21:39 +0000)]
Simplify some typedefs. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285863
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Adrian McCarthy [Wed, 2 Nov 2016 21:30:35 +0000 (21:30 +0000)]
Emit S_COMPILE3 record once per TU rather than once per function
This has some ripple effects in several tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285862
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Kevin Enderby [Wed, 2 Nov 2016 21:08:39 +0000 (21:08 +0000)]
Add the rest of the additional error checks for invalid Mach-O files when
the offsets and sizes of an element of the Mach-O file overlaps with
another element in the Mach-O file.
Some other tests for malformed Mach-O files now run into these
checks so their tests were also adjusted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285860
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Davide Italiano [Wed, 2 Nov 2016 21:05:42 +0000 (21:05 +0000)]
[RuntimeDyld] Move an X86 only test to the correct directory.
This is an attempt to placate the bots after r285841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285859
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Eli Friedman [Wed, 2 Nov 2016 20:48:11 +0000 (20:48 +0000)]
DCE math library calls with a constant operand.
On platforms which use -fmath-errno, math libcalls without any uses
require some extra checks to figure out if they are actually dead.
Fixes https://llvm.org/bugs/show_bug.cgi?id=30464 .
Differential Revision: https://reviews.llvm.org/D25970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285857
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Vedant Kumar [Wed, 2 Nov 2016 19:44:13 +0000 (19:44 +0000)]
[llvm-cov] Turn line numbers in html reports into clickable links
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285853
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Krzysztof Parzyszek [Wed, 2 Nov 2016 17:59:54 +0000 (17:59 +0000)]
[Hexagon] Remove registers coalesced in expand-condsets from live intervals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285846
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Artem Tamazov [Wed, 2 Nov 2016 17:45:58 +0000 (17:45 +0000)]
[AMDGPU][mc] Improve test of special asm symbols.
Test simplified. Coverage extended.
Differential Revision: https://reviews.llvm.org/D26198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285844
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Davide Italiano [Wed, 2 Nov 2016 17:32:19 +0000 (17:32 +0000)]
[lli/COFF] Set the correct alignment for common symbols
Otherwise we set it always to zero, which is not correct,
and we assert inside alignTo (Assertion failed:
Align != 0u && "Align can't be 0.").
Differential Revision: https://reviews.llvm.org/D26173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285841
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Matt Arsenault [Wed, 2 Nov 2016 17:24:54 +0000 (17:24 +0000)]
AMDGPU: Cleanup some xfailed tests
Some of these are already fixed or tested somewhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285840
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Zachary Turner [Wed, 2 Nov 2016 17:10:55 +0000 (17:10 +0000)]
Fix build due to missing definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285837
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Zachary Turner [Wed, 2 Nov 2016 17:05:19 +0000 (17:05 +0000)]
Add CodeViewRecordIO for reading and writing.
Using a pattern similar to that of YamlIO, this allows
us to have a single codepath for translating codeview
records to and from serialized byte streams. The
current patch only hooks this up to the reading of
CodeView type records. A subsequent patch will hook
it up for writing of CodeView type records, and then a
third patch will hook up the reading and writing of
CodeView symbols.
Differential Revision: https://reviews.llvm.org/D26040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285836
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Nicolai Haehnle [Wed, 2 Nov 2016 17:03:11 +0000 (17:03 +0000)]
AMDGPU: Allow additional implicit operands on MOVRELS instructions
Summary:
The post-RA scheduler occasionally uses additional implicit operands when
the vector implicit operand as a whole is killed, but some subregisters
are still live because they are directly referenced later. Unfortunately,
this seems incredibly subtle to reproduce.
Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test
and others.
Reviewers: arsenm, tstellarAMD
Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285835
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Malcolm Parsons [Wed, 2 Nov 2016 16:43:50 +0000 (16:43 +0000)]
Fix Clang-tidy readability-redundant-string-cstr warnings
Reviewers: beanz, lattner, jlebar
Subscribers: jholewinski, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D26235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285832
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Nirav Dave [Wed, 2 Nov 2016 16:22:51 +0000 (16:22 +0000)]
[ARM][MC] Cleanup ARM Target Assembly Parser
Summary:
Correctly parse end-of-statement tokens and handle preprocessor
end-of-line comments in ARM assembly processor.
Reviewers: rnk, majnemer
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D26152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285830
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Adrian Prantl [Wed, 2 Nov 2016 16:20:37 +0000 (16:20 +0000)]
Improve and cleanup comments in DwarfExpression.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285829
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Matt Arsenault [Wed, 2 Nov 2016 16:18:29 +0000 (16:18 +0000)]
BranchRelaxation: Fix computing indirect branch block size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285828
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Adrian Prantl [Wed, 2 Nov 2016 16:12:20 +0000 (16:12 +0000)]
Simplify control flow in the the DWARF expression compiler
by refactoring common code into a DwarfExpressionCursor wrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285827
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Adrian Prantl [Wed, 2 Nov 2016 16:12:16 +0000 (16:12 +0000)]
Emit DW_OP_piece also if the previous value was a constant.
This fixes a bug in the DWARF backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285826
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Simon Pilgrim [Wed, 2 Nov 2016 15:41:15 +0000 (15:41 +0000)]
Use !operator to test if APInt is zero/non-zero. NFCI.
Avoids APInt construction and slower comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285822
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Rafael Espindola [Wed, 2 Nov 2016 15:33:59 +0000 (15:33 +0000)]
Simplify typedefs. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285819
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Rafael Espindola [Wed, 2 Nov 2016 15:23:32 +0000 (15:23 +0000)]
Inline a version of getSectionStringTable into the only use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285817
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Rafael Espindola [Wed, 2 Nov 2016 15:15:59 +0000 (15:15 +0000)]
Compute the section table lazily.
As a consequence this move a bunch of error checking out of the constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285815
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Vasileios Kalintiris [Wed, 2 Nov 2016 15:11:27 +0000 (15:11 +0000)]
[mips] Always run the MipsOptimizePICCall pass.
Summary:
Remove this pass from addMachineSSAOptimization() and register it unconditionally in through addPreRegAlloc(). This pass is required for generating correct PIC calls.
Reviewers: sdardis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285814
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Joerg Sonnenberger [Wed, 2 Nov 2016 15:00:31 +0000 (15:00 +0000)]
Create the virtual register for the global base in the intersection of
GPRC and GPRC_NOR0 (or the 64bit equivalent) and not just the latter.
GPRC_NOR0 contains ZERO as alternative meaning of r0 and is therefore
not a true subclass of GPRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285813
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Rafael Espindola [Wed, 2 Nov 2016 14:52:50 +0000 (14:52 +0000)]
Inline getSectionStringTableIndex() into only caller. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285812
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Rafael Espindola [Wed, 2 Nov 2016 14:10:57 +0000 (14:10 +0000)]
Avoid a report_fatal_error in sections().
Have it return a ErrorOr<Range> and delete section_begin and
section_end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285807
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Aaron Ballman [Wed, 2 Nov 2016 13:58:57 +0000 (13:58 +0000)]
Removing a switch statement that contains a default label, but no case labels. Silences an MSVC warning; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285806
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Rafael Espindola [Wed, 2 Nov 2016 13:07:38 +0000 (13:07 +0000)]
getNumSections should return a uintX_t. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285804
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Rafael Espindola [Wed, 2 Nov 2016 12:49:55 +0000 (12:49 +0000)]
Simplify getSection. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285803
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Joerg Sonnenberger [Wed, 2 Nov 2016 12:45:28 +0000 (12:45 +0000)]
Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285802
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Ulrich Weigand [Wed, 2 Nov 2016 11:32:28 +0000 (11:32 +0000)]
[SystemZ] Fix compiler warnings introduced by r285574
SystemZAsmParser::parseOperand returns a bool, not an enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285800
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Kirill Bobyrev [Wed, 2 Nov 2016 10:00:40 +0000 (10:00 +0000)]
[llvm] FIx if-clause -Wmisleading-indentation issue.
While bootstrapping Clang with recent `gcc 6.2.0` I found a bug related to misleading indentation.
I believe, a pair of `{}` was forgotten, especially given the above similar piece of code:
```
if (!RDef || !HII->isPredicable(*RDef)) {
Done = coalesceRegisters(RD, RegisterRef(S1));
if (Done) {
UpdRegs.insert(RD.Reg);
UpdRegs.insert(S1.getReg());
}
}
```
Reviewers: kparzysz
Differential Revision: https://reviews.llvm.org/D26204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285794
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Bjorn Pettersson [Wed, 2 Nov 2016 08:55:19 +0000 (08:55 +0000)]
[Reassociate] Skip analysis of dead code to avoid infinite loop.
Summary:
It was detected that the reassociate pass could enter an inifite
loop when analysing dead code. Simply skipping to analyse basic
blocks that are dead avoids such problems (and as a side effect
we avoid spending time on optimising dead code).
The solution is using the same Reverse Post Order ordering of the
basic blocks when doing the optimisations, as when building the
precalculated rank map. A nice side-effect of this solution is
that we now know that we only try to do optimisations for blocks
with ranked instructions.
Fixes https://llvm.org/bugs/show_bug.cgi?id=30818
Reviewers: llvm-commits, davide, eli.friedman, mehdi_amini
Subscribers: dberlin
Differential Revision: https://reviews.llvm.org/D26154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285793
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Dylan McKay [Wed, 2 Nov 2016 06:47:40 +0000 (06:47 +0000)]
[AVR] Add instruction selection lowering code
Summary: This adds AVRISelLowering.cpp
Reviewers: arsenm, kparzysz
Subscribers: llvm-commits, modocache, japaric, wdng, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285790
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Shoaib Meenai [Wed, 2 Nov 2016 06:10:03 +0000 (06:10 +0000)]
[CMake] Set default build type correctly
At least with cmake 3.6.1, the default build type setting was having no
effect; the generated CMakeCache.txt still had an empty CMAKE_BUILD_TYPE.
Force the variable to be set to achieve the desired behavior.
Differential Revision: https://reviews.llvm.org/D26200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285789
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Peter Collingbourne [Wed, 2 Nov 2016 02:58:47 +0000 (02:58 +0000)]
Bitcode: Fix short read implementation.
We need to zero extend the byte in order to correctly shift it into a
64-bit value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285785
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Brad Smith [Wed, 2 Nov 2016 01:39:01 +0000 (01:39 +0000)]
Disable the use of std::call_once on OpenBSD with libstdc++.
It was noticed this caused performance regressions and deadlocks. PR30768.
Reorder the code to make it clearer what is tested.
PPC now disables the use of std::call_once only with libstdc++ with
the reordering of the code, as was the original intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285782
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Michael Gottesman [Wed, 2 Nov 2016 00:59:58 +0000 (00:59 +0000)]
[ilist_node] Add a getReverseIterator() method and a unittest for it.
This is the reverse_iterator analogue of getIterator().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285780
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Peter Collingbourne [Wed, 2 Nov 2016 00:39:11 +0000 (00:39 +0000)]
Bitcode: Check file size before reading bitcode header.
Should unbreak ocaml binding tests.
Also added an llvm-dis test that checks for the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285777
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Peter Collingbourne [Wed, 2 Nov 2016 00:08:37 +0000 (00:08 +0000)]
Support: Remove MemoryObject and DataStreamer interfaces.
These interfaces are no longer used.
Differential Revision: https://reviews.llvm.org/D26222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285774
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Peter Collingbourne [Wed, 2 Nov 2016 00:08:19 +0000 (00:08 +0000)]
Bitcode: Change reader interface to take memory buffers.
As proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-October/106595.html
This change also fixes an API oddity where BitstreamCursor::Read() would
return zero for the first read past the end of the bitstream, but would
report_fatal_error for subsequent reads. Now we always report_fatal_error
for all reads past the end. Updated clients to check for the end of the
bitstream before reading from it.
I also needed to add padding to the invalid bitcode tests in
test/Bitcode/. This is because the streaming interface was not checking that
the file size is a multiple of 4.
Differential Revision: https://reviews.llvm.org/D26219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285773
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Vedant Kumar [Tue, 1 Nov 2016 23:55:50 +0000 (23:55 +0000)]
[docs] Fix some typos. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285772
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Alex Bradbury [Tue, 1 Nov 2016 23:47:30 +0000 (23:47 +0000)]
[RISCV] Add bare-bones RISC-V MCTargetDesc
This is enough to compile and link but doesn't yet do anything particularly
useful. Once an ASM parser and printer are added in the next two patches, the
whole thing can be usefully tested.
Differential Revision: https://reviews.llvm.org/D23562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285770
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Alex Bradbury [Tue, 1 Nov 2016 23:40:28 +0000 (23:40 +0000)]
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
For now, only add instruction definitions for basic ALU operations. Our
initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D23561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285769
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Matt Arsenault [Tue, 1 Nov 2016 23:22:17 +0000 (23:22 +0000)]
AMDGPU: Handle CopyToReg in getOperandRegClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285768
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Matt Arsenault [Tue, 1 Nov 2016 23:14:20 +0000 (23:14 +0000)]
AMDGPU: Use brev for materializing SGPR constants
This is already done with VGPR immediates and saves 4 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285765
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Matt Arsenault [Tue, 1 Nov 2016 22:55:07 +0000 (22:55 +0000)]
AMDGPU: Default to using scalar mov to materialize immediate
This is the conservatively correct way because it's easy to
move or replace a scalar immediate. This was incorrect in the case
when the register class wasn't known from the static instruction
definition, but still needed to be an SGPR. The main example of this
is inlineasm has an SGPR constraint.
Also start verifying the register classes of inlineasm operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285762
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Eric Christopher [Tue, 1 Nov 2016 22:15:50 +0000 (22:15 +0000)]
Move the initialization of PreferredLoopExit into runOnMachineFunction to be near the other function specific initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285758
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Sam McCall [Tue, 1 Nov 2016 22:02:14 +0000 (22:02 +0000)]
Fix uninitialized access in MachineBlockPlacement.
Summary:
Currently PreferredLoopExit is set only in buildLoopChains, which is
never called if there are no MachineLoops.
MSan is currently broken by this:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/145/steps/check-llvm%20msan/logs/stdio
This is a naive fix to get things green again. iteratee: you may have a better fix.
This change will also mean PreferredLoopExit will not carry over if
buildCFGChains() is called a second time in runOnMachineFunction, this
appears to be the right thing.
Reviewers: bkramer, iteratee, echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285757
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Matt Arsenault [Tue, 1 Nov 2016 21:58:07 +0000 (21:58 +0000)]
AMDGPU: Stop creating unused virtual registers
These are only used in the spill to VMEM path. Move them to
the one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285756
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Rafael Espindola [Tue, 1 Nov 2016 21:33:55 +0000 (21:33 +0000)]
Don't compute DotShstrtab eagerly.
This saves a field that is not always used. It also avoids failing a
program that doesn't need the section names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285753
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George Burgess IV [Tue, 1 Nov 2016 21:17:46 +0000 (21:17 +0000)]
[MemorySSA] Tighten up types to make our API prettier. NFC.
Patch by bryant.
Differential Revision: https://reviews.llvm.org/D26126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285750
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Rafael Espindola [Tue, 1 Nov 2016 20:56:15 +0000 (20:56 +0000)]
Simplify getStringTableIndex.
The description in the ELF spec is just
---------------------------
If the section name string table section index is greater than or
equal to SHN_LORESERVE (0xff00), this member has the value SHN_XINDEX
(0xffff) and the actual index of the section name string table section
is contained in the sh_link field of the section header at index 0.
---------------------------
So we only have to check for it being SHN_XINDEX. Also, sh_link is
always 32 bits, so don't return an uintX_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285747
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Sanjay Patel [Tue, 1 Nov 2016 20:43:00 +0000 (20:43 +0000)]
[ValueTracking] remove TODO comment; NFC
InstCombine should always canonicalize patterns like the one shown in the comment
when visiting 'select' insts in adjustMinMax().
Scalars were already handled there, and vector splats are handled after:
https://reviews.llvm.org/rL285732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285744
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Matt Arsenault [Tue, 1 Nov 2016 20:42:24 +0000 (20:42 +0000)]
AMDGPU: Workaround for instruction size with literals
Instructions with a 32-bit base encoding with an optional
32-bit literal encoded after them report their size as 4
for the disassembler. Consider these when computing the
MachineInstr size. This fixes problems caused by size estimate
consistency in BranchRelaxation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285743
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Rafael Espindola [Tue, 1 Nov 2016 20:24:22 +0000 (20:24 +0000)]
Use the existing std::error_code out parameter.
This avoids calling exit with a partially constructed object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285738
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Chris Bieneman [Tue, 1 Nov 2016 20:19:33 +0000 (20:19 +0000)]
Fix llvm-shlib cmake build
Summary:
This fixes a few things that used to work with a Makefile build, but were broken in cmake.
1. Treat MINGW like a Linux system.
2. The shlib should never contain other shared libraries.
Patch By: Valentin Churavy
Reviewers: axw, beanz
Subscribers: modocache, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285737
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Joerg Sonnenberger [Tue, 1 Nov 2016 20:09:41 +0000 (20:09 +0000)]
GC empty subdirectories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285734
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Sanjay Patel [Tue, 1 Nov 2016 20:08:02 +0000 (20:08 +0000)]
[InstCombine] allow splat vector folds in adjustMinMax()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285732
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Alex Bradbury [Tue, 1 Nov 2016 19:31:30 +0000 (19:31 +0000)]
[RISCV] Add RISCV.def to module.modulemap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285730
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Sanjay Patel [Tue, 1 Nov 2016 19:19:29 +0000 (19:19 +0000)]
[InstCombine] Fold nuw left-shifts in `ugt`/`ule` comparisons.
This transforms
%a = shl nuw %x, c1
%b = icmp {ugt|ule} %a, c0
into
%b = icmp {ugt|ule} %x, (c0 >> c1)
z3:
(declare-const x (_ BitVec 64))
(declare-const c0 (_ BitVec 64))
(declare-const c1 (_ BitVec 64))
(push)
(assert (= x (bvlshr (bvshl x c1) c1))) ; nuw
(assert (not (= (bvugt (bvshl x c1) c0)
(bvugt x
(bvlshr c0 c1)))))
(check-sat)
(get-model)
(pop)
(push)
(assert (= x (bvlshr (bvshl x c1) c1))) ; nuw
(assert (not (= (bvule (bvshl x c1) c0)
(bvule x
(bvlshr c0 c1)))))
(check-sat)
(get-model)
(pop)
Patch by bryant!
Differential Revision: https://reviews.llvm.org/D25913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285729
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Krzysztof Parzyszek [Tue, 1 Nov 2016 19:02:10 +0000 (19:02 +0000)]
[Hexagon] Rename operand/predicate names for unshifted integers
For example, rename s6Ext to s6_0Ext. The names for shifted integers
include the underscore and this will make the naming consistent. It
also exposed a few duplicates that were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285728
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Matt Arsenault [Tue, 1 Nov 2016 18:34:00 +0000 (18:34 +0000)]
BranchRelaxation: Expand unconditional branches first
It's likely if a conditional branch needs to be expanded, the following
unconditional branch will also need expansion. By expanding the
unconditional branch first, the conditional branch can be simply
inverted to jump over the inserted indirect branch block. If the
conditional branch is expanded first, it results in an additional
branch.
This avoids test regressions in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285722
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Sanjay Patel [Tue, 1 Nov 2016 18:15:03 +0000 (18:15 +0000)]
[InstCombine] clean up adjustMinMax(); NFCI
1. Change param names for readability
2. Change pointer param to ref
3. Early exit to reduce indent
4. Change switch to if/else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285718
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Erich Keane [Tue, 1 Nov 2016 17:54:05 +0000 (17:54 +0000)]
Test Commit, removed extraneous newline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285717
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Konstantin Zhuravlyov [Tue, 1 Nov 2016 17:49:33 +0000 (17:49 +0000)]
[AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32
This will prevent following regression when enabling i16 support (D18049):
test/CodeGen/AMDGPU/ctlz.ll
test/CodeGen/AMDGPU/ctlz_zero_undef.ll
Differential Revision: https://reviews.llvm.org/D25802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285716
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Sanjay Patel [Tue, 1 Nov 2016 17:46:08 +0000 (17:46 +0000)]
[InstCombine] add helper function for adjustMinMax(); NFCI
This is just a cut and paste; clean-up and enhancements to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285715
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Chris Bieneman [Tue, 1 Nov 2016 17:44:58 +0000 (17:44 +0000)]
[CMake] Fix rpath construction for out-of-tree builds
This patch was produced in conjunction with Michał Górny. It should resolve the issues that were trying to be solved by D25304.
This moves rpath handling into `llvm_add_library` and `add_llvm_executable` so that it is available to all projects using AddLLVM whether built in-tree or out-of-tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285714
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Sanjay Patel [Tue, 1 Nov 2016 17:34:29 +0000 (17:34 +0000)]
[InstCombine] add vector tests for ext+adjust min/max
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285713
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Alex Bradbury [Tue, 1 Nov 2016 17:27:54 +0000 (17:27 +0000)]
[RISCV] Add stub backend
This contains just enough for lib/Target/RISCV to compile. Notably a basic
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc
-march=riscv32 myinput.ll and will find it fails due to the lack of
MCAsmInfo.
See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for
further discussion
Differential Revision: https://reviews.llvm.org/D23560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285712
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Tom Stellard [Tue, 1 Nov 2016 17:20:03 +0000 (17:20 +0000)]
AMDGPU: Fix buildbots broken by r285704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285711
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Alex Bradbury [Tue, 1 Nov 2016 17:09:49 +0000 (17:09 +0000)]
[RISCV] Add missing RISCV.def
Fix rL285708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285709
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Alex Bradbury [Tue, 1 Nov 2016 16:59:37 +0000 (16:59 +0000)]
[RISCV] Add RISC-V ELF defines
Add the necessary definitions for RISC-V ELF files, including relocs. Also
make necessary trivial change to ELFYaml, llvm-objdump, and llvm-readobj in
order to work with RISC-V ELFs.
Differential Revision: https://reviews.llvm.org/D23557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285708
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Alex Bradbury [Tue, 1 Nov 2016 16:47:54 +0000 (16:47 +0000)]
[RISCV] Recognise riscv32 and riscv64 in triple parsing code
This is the first in a series of 10 initial patches that incrementally add an
MC layer for RISC-V to LLVM. See
<http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> for more
discussion.
Differential Revision: https://reviews.llvm.org/D23557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285707
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Sanjay Patel [Tue, 1 Nov 2016 16:39:30 +0000 (16:39 +0000)]
[InstCombine] move/fix tests for adjusted min/max
I think the former 'test50' had a typo making it functionally equivalent
to the former 'test49'; changed the predicate to provide more coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285706
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Alex Bradbury [Tue, 1 Nov 2016 16:32:05 +0000 (16:32 +0000)]
[TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h
As it stands, the OperandMatchResultTy is only included in the generated
header if there is custom operand parsing. However, almost all backends
make use of MatchOperand_Success and friends from OperandMatchResultTy for
e.g. parseRegister. This is a pain when starting an AsmParser for a new
backend that doesn't yet have custom operand parsing. Move the enum to
MCTargetAsmParser.h.
This patch is a prerequisite for D23563
Differential Revision: https://reviews.llvm.org/D23496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285705
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Tom Stellard [Tue, 1 Nov 2016 16:31:48 +0000 (16:31 +0000)]
AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64
I wanted to implement this as a target independent expansion, however when
targets say they want to expand FP_TO_FP16 what they actually want is
the unsafe math expansion when possible and expansion to a libcall in all
other cases.
The only way to make this work as a target independent would be to add logic
to target's TargetLowering construction to mark theses nodes as Expand when
LegalizeDAG can use the unsafe expansion and mark them as LibCall when it
cannot. I think this would be possible, but I think it would be too fragile
and complex as it would require targets to keep their expansion logic up
to date with the code in LegalizeDAG.
Reviewers: bogner, ab, t.p.northover, arsenm
Subscribers: wdng, llvm-commits, nhaehnle
Differential Revision: https://reviews.llvm.org/D25999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285704
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Sjoerd Meijer [Tue, 1 Nov 2016 15:59:37 +0000 (15:59 +0000)]
This is a 1 character fix for an ARM build attribute test (r284571): the
purpose of the test was to have 2 different function attribute sets, but due
to a typo there was only one both with number #0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285701
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Sanjay Patel [Tue, 1 Nov 2016 15:48:30 +0000 (15:48 +0000)]
[InstCombine] fix tests for adjusted min/max
1. Delete identical tests
2. Rename tests to reflect actual functionality
3. Add comments
4. Add unsigned variants
5. Add vector variants with FIXME comments
6. Rename test file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285699
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Simon Pilgrim [Tue, 1 Nov 2016 15:40:30 +0000 (15:40 +0000)]
[InstCombine] Folding of shifts by the sum of positive values
This patch introduces the combine:
(C1 shift (A add C2)) -> ((C1 shift C2) shift A)
iff A and C2 are both positive
If both A and C2 are know to be positive then we can safely split into 2 shifts, permitting the folding of the Inner shift.
Fix for the spec benchmark case mentioned by @nadav on PR15141 (assuming we can prove that the inputs as positive).
Differential Revision: https://reviews.llvm.org/D26000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285696
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Sanjay Patel [Tue, 1 Nov 2016 14:38:30 +0000 (14:38 +0000)]
[InstCombine] auto-generate better checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285693
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Chris Dewhurst [Tue, 1 Nov 2016 14:23:37 +0000 (14:23 +0000)]
[Sparc][LEON] Test for FixFDIVSQRT erratum fix.
Note: Test is per differential review, but the other changed code in the review was for an optimisation that din't quite work. Nevertheless, the test is valid for the unoptimised version of the fix.
Differential Review: https://reviews.llvm.org/D24658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285692
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James Molloy [Tue, 1 Nov 2016 13:37:41 +0000 (13:37 +0000)]
[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables
[Reapplying r284580 and r285917 with fix and testing to ensure emitted jump tables for Thumb-1 have 4-byte alignment]
The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions.
It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size.
TBB example:
Before: lsls r0, r0, #2 After: add r0, pc
adr r1, .LJTI0_0 ldrb r0, [r0, #6]
ldr r0, [r0, r1] lsls r0, r0, #1
mov pc, r0 add pc, r0
=> No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4.
The only case that can increase dynamic instruction count is the TBH case:
Before: lsls r0, r4, #2 After: lsls r4, r4, #1
adr r1, .LJTI0_0 add r4, pc
ldr r0, [r0, r1] ldrh r4, [r4, #6]
mov pc, r0 lsls r4, r4, #1
add pc, r4
=> 1 more instruction in prologue. Jump table shrunk by a factor of 2.
So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285690
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Valery Pykhtin [Tue, 1 Nov 2016 10:26:48 +0000 (10:26 +0000)]
[AMDGPU] Expand vector mulhu/mulhs
Differential revision: https://reviews.llvm.org/D26077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285684
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