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Nico Weber [Sun, 29 Apr 2018 00:45:03 +0000 (00:45 +0000)]
s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the
default macro instead of a reinvented one.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.
This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331127
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Robert Widmann [Sat, 28 Apr 2018 22:32:07 +0000 (22:32 +0000)]
[LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331123
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Craig Topper [Sat, 28 Apr 2018 18:46:11 +0000 (18:46 +0000)]
[X86] Restrict many of the InstAliases to either to only att or intel syntax. NFCI
Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic
This patch restricts a lot of these to only one variant so we don't get the duplication.
This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331117
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Simon Pilgrim [Sat, 28 Apr 2018 18:45:16 +0000 (18:45 +0000)]
[X86] Remove unnecessary rotate-carry folded InstRW overrides.
Merge some remaining instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331116
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Daniel Sanders [Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)]
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
improve optimization of extends and truncates, this legality requirement
would spread without considerable care w.r.t when certain combines were
permitted.
* The SelectionDAG importer required some ugly and fragile pattern
rewriting to translate patterns into this style.
This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.
This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.
Depends on D45466
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331115
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Robert Widmann [Sat, 28 Apr 2018 18:13:39 +0000 (18:13 +0000)]
[LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings
Summary:
* rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes. Provide these bindings now.
* Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331114
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Roman Lebedev [Sat, 28 Apr 2018 15:45:07 +0000 (15:45 +0000)]
[InstCombine] Canonicalize variable mask in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
https://rise4fun.com/Alive/Yol
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331112
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Roman Lebedev [Sat, 28 Apr 2018 15:45:00 +0000 (15:45 +0000)]
[InstCombine][NFC] Add tests for variable mask canonicalization in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
Differential Revision: https://reviews.llvm.org/D45663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331111
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Simon Pilgrim [Sat, 28 Apr 2018 15:32:19 +0000 (15:32 +0000)]
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331110
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Simon Pilgrim [Sat, 28 Apr 2018 15:18:49 +0000 (15:18 +0000)]
[llvm-mca][X86] Add double shift resource tests to all relevant models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331109
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Simon Pilgrim [Sat, 28 Apr 2018 14:56:18 +0000 (14:56 +0000)]
[llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331108
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Simon Pilgrim [Sat, 28 Apr 2018 14:08:51 +0000 (14:08 +0000)]
[X86][SSE] Stop hard coding some instruction scheduler classes.
Make these arguments to the multiclass to allow easier specialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331107
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Simon Pilgrim [Sat, 28 Apr 2018 14:06:28 +0000 (14:06 +0000)]
[X86][HW] Cleanup Haswell model. NFCI.
Moved LAHF/SAHF to instrs instead of instregex.
Removed some unnecessary instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331106
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Craig Topper [Sat, 28 Apr 2018 06:58:27 +0000 (06:58 +0000)]
[X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331105
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Craig Topper [Sat, 28 Apr 2018 06:58:26 +0000 (06:58 +0000)]
[X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.
These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331104
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Serguei Katkov [Sat, 28 Apr 2018 06:41:35 +0000 (06:41 +0000)]
[SCEV] Touch the unsused stats variables for product build.
This is a fix by elimination compiler warnings considered as errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331103
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Craig Topper [Sat, 28 Apr 2018 06:02:40 +0000 (06:02 +0000)]
[X86] Remove REX.W from 64-bit mode BND instructions.
As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331102
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Craig Topper [Sat, 28 Apr 2018 06:02:39 +0000 (06:02 +0000)]
[X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler.
Favor the 0x1a encoding for register/register move to match gas.
The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV.
Hide the _REV encoding from the assembler but leave it for the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331101
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Max Kazantsev [Sat, 28 Apr 2018 04:38:21 +0000 (04:38 +0000)]
[NFC] Add some tests that demonstrate unrecognized three-way comparison patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331100
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Serguei Katkov [Sat, 28 Apr 2018 03:53:36 +0000 (03:53 +0000)]
[SCEV] Reduce the number of invocation to non trivial getExact function
The invocation of getExact in ScalarEvolution::getBackedgeTakenInfo is used
only for getting statistic and for assert.
Even if statistics is disabled, the code related to it will be eliminated
the invocation to getExact itself will not be eliminated
because it may have side-effects like creation of new SCEVs.
So do invocation only when we collect statistics or executes asserts.
Reviewers: mkazantsev, sanjoy, javed.absar
Reviewed By: javed.absar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331099
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Jessica Paquette [Fri, 27 Apr 2018 23:36:35 +0000 (23:36 +0000)]
[MachineOutliner] Add defs to calls + don't track liveness on outlined functions
This commit makes it so that if you outline a def of some register, then the
call instruction created by the outliner actually reflects that the register
is defined by the call. It also makes it so that outlined functions don't
have the TracksLiveness property.
Outlined calls shouldn't break liveness assumptions that someone might make.
This also un-XFAILs the noredzone test, and updates the calls test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331095
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Philip Reames [Fri, 27 Apr 2018 23:15:56 +0000 (23:15 +0000)]
[LoopGuardWidening] Make PostDomTree optional
The effect of doing so is not disrupting the LoopPassManager when mixing this pass with other loop passes. This should help locality of access substaintially and avoids the cost of computing PostDom.
The assumption here is that the full GuardWidening (which does use PostDom) is run as a canonicalization before loop opts and that this version is just catching cases exposed by other loop passes. (i.e. LoopPredication, IndVarSimplify, LoopUnswitch, etc..)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331094
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Heejin Ahn [Fri, 27 Apr 2018 22:23:11 +0000 (22:23 +0000)]
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(https://github.com/llvm-mirror/llvm/blob/
c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006).
Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.
(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)
Reviewers: RKSimon, jgravelle-google
Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331092
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Craig Topper [Fri, 27 Apr 2018 22:15:33 +0000 (22:15 +0000)]
[X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm if the mask instrinsics are also used in the same basic block.
Summary:
Previously the flag intrinsics always used the index instructions even if a mask instruction also exists.
To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction.
Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs.
I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions.
Reviewers: chandlerc, RKSimon, spatel
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331091
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Adrian Prantl [Fri, 27 Apr 2018 22:05:31 +0000 (22:05 +0000)]
Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.
rdar://problem/
39741860
This reapplies r330970 after fixing an uncovered bug in r331086 and
working around the situation caused by it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331090
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Reid Kleckner [Fri, 27 Apr 2018 21:51:25 +0000 (21:51 +0000)]
[FastISel] Actually enable local value sinking by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331088
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Reid Kleckner [Fri, 27 Apr 2018 21:48:51 +0000 (21:48 +0000)]
[FastISel] Fix local value sinking algorithmic complexity
Now local value sinking only scans and numbers instructions added
between the current flush point and the last flush point. This ensures
that ISel is overall linear in the size of the BB.
Fixes PR37010 and re-enables local value sinking by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331087
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Adrian Prantl [Fri, 27 Apr 2018 21:41:36 +0000 (21:41 +0000)]
Fix a bug in GlobalOpt's handling of DIExpressions.
This patch adds support for fragment expressions
TryToShrinkGlobalToBoolean() which were previously just dropped.
Thanks to Reid Kleckner for providing me a reproducer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331086
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Roman Lebedev [Fri, 27 Apr 2018 21:23:20 +0000 (21:23 +0000)]
[PatternMatch] Stabilize the matching order of commutative matchers
Summary:
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the `LHS` and `RHS` matchers:
1. match `RHS` matcher to the `first` operand of binary operator,
2. and then match `LHS` matcher to the `second` operand of binary operator.
This works ok.
But it complicates writing of commutative matchers, where one would like to match
(`m_Value()`) the value on one side, and use (`m_Specific()`) it on the other side.
This is additionally complicated by the fact that `m_Specific()` stores the `Value *`,
not `Value **`, so it won't work at all out of the box.
The last problem is trivially solved by adding a new `m_c_Specific()` that stores the
`Value **`, not `Value *`. I'm choosing to add a new matcher, not change the existing
one because i guess all the current users are ok with existing behavior,
and this additional pointer indirection may have performance drawbacks.
Also, i'm storing pointer, not reference, because for some mysterious-to-me reason
it did not work with the reference.
The first one appears trivial, too.
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the ~~`LHS` and `RHS` matchers~~ **operands**:
1. match ~~`RHS`~~ **`LHS`** matcher to the ~~`first`~~ **`second`** operand of binary operator,
2. and then match ~~`LHS`~~ **`RHS`** matcher to the ~~`second`~ **`first`** operand of binary operator.
Surprisingly, `$ ninja check-llvm` still passes with this.
But i expect the bots will disagree..
The motivational unittest is included.
I'd like to use this in D45664.
Reviewers: spatel, craig.topper, arsenm, RKSimon
Reviewed By: craig.topper
Subscribers: xbolva00, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331085
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Simon Pilgrim [Fri, 27 Apr 2018 21:14:19 +0000 (21:14 +0000)]
[X86] Merge some x87 instruction instregex single matches. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331084
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Sanjay Patel [Fri, 27 Apr 2018 21:14:15 +0000 (21:14 +0000)]
[Reassociate] add a test with debug info; NFC
As suggested in D45842
(although still not sure if we're going to advance that),
we must invalidate references to instructions that have
been recycled (operands were changed, so result is different).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331083
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Daniel Sanders [Fri, 27 Apr 2018 21:03:27 +0000 (21:03 +0000)]
Attempt to fix remaining build failures after r331071 by changing the tuple to a struct
Some of the bots were failing in a different way to the others. These were
unable to compare tuples. Fix this by changing to a struct, thereby avoiding
the quirks of tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331081
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Philip Reames [Fri, 27 Apr 2018 20:58:30 +0000 (20:58 +0000)]
[LICM] Reduce nesting with an early return [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331080
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Philip Reames [Fri, 27 Apr 2018 20:44:01 +0000 (20:44 +0000)]
[MustExecute/LICM] Special case first instruction in throwing header
We currently have a hard to solve analysis problem around the order of instructions within a potentially throwing block. We can't cheaply determine whether a given instruction is before the first potential throw in the block. While we're working on that in the background, special case the first instruction within the header.
why this particular special case? Well, headers are guaranteed to execute if the loop does, and it turns out we tend to produce this form in practice.
In a follow on patch, I tend to extend LICM with an alternate approach which works for any instruction in the header before the first throw, but this is the best I can come up with other users of the analysis (such as store promotion.)
Note: I can't show the difference in the analysis result since we're ORing in the expensive instruction walk used by SCEV. Using the full walk is not suitable for a general solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331079
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Vlad Tsyrklevich [Fri, 27 Apr 2018 20:32:34 +0000 (20:32 +0000)]
ELFObjectWriter: Allow one unique symver per symbol
Summary:
Only allow a single unique .symver alias per symbol. This matches the
behavior of gas. I noticed that we ignored multiple mismatched symver
directives looking at https://reviews.llvm.org/D45798
Reviewers: pcc, tejohnson, espindola
Reviewed By: pcc
Subscribers: emaste, arichardson, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D45845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331078
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Daniel Neilson [Fri, 27 Apr 2018 20:29:18 +0000 (20:29 +0000)]
[LV] Common duplicate vector load/store address calculation (NFC)
Summary:
Commoning some obviously copy/paste code in
InnerLoopVectorizer::vectorizeMemoryInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331076
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Daniel Sanders [Fri, 27 Apr 2018 20:17:44 +0000 (20:17 +0000)]
Attempt to fix build failure after r331071 using std::make_tuple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331074
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Jun Bum Lim [Fri, 27 Apr 2018 19:59:20 +0000 (19:59 +0000)]
[PostRASink] extend the live-in check for all aliased registers
Extend the live-in check for all aliased registers so that we can
allow sinking Copy instructions when only implicit def is in successor's
live-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331072
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Daniel Sanders [Fri, 27 Apr 2018 19:48:53 +0000 (19:48 +0000)]
[globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand
Summary:
Currently only the memory size is supported but others can be added as
needed.
narrowScalar for G_LOAD and G_STORE now correctly update the
MachineMemOperand and will refuse to legalize atomics since those need more
careful expansions to maintain atomicity.
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331071
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Paul Semel [Fri, 27 Apr 2018 19:16:27 +0000 (19:16 +0000)]
[llvm-objcopy] Add --weaken-symbol (-W) option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331070
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Paul Semel [Fri, 27 Apr 2018 19:09:44 +0000 (19:09 +0000)]
[llvm-objcopy] Add --globalize-symbol option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331068
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Jun Bum Lim [Fri, 27 Apr 2018 18:44:37 +0000 (18:44 +0000)]
[CodeGen] Use RegUnits to track register aliases (NFC)
Summary: Use RegUnits to track register aliases in PostRASink and AArch64LoadStoreOptimizer.
Reviewers: thegameg, mcrosier, gberry, qcolombet, sebpop, MatzeB, t.p.northover, javed.absar
Reviewed By: thegameg, sebpop
Subscribers: javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331066
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Simon Pilgrim [Fri, 27 Apr 2018 18:19:48 +0000 (18:19 +0000)]
[X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331065
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Mark Searles [Fri, 27 Apr 2018 17:59:15 +0000 (17:59 +0000)]
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
Differential Revision: https://reviews.llvm.org/D46154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331062
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Philip Reames [Fri, 27 Apr 2018 17:41:37 +0000 (17:41 +0000)]
[GuardWidening] Add some clarifying comments about heuristics [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331061
91177308-0d34-0410-b5e6-
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Philip Reames [Fri, 27 Apr 2018 17:29:10 +0000 (17:29 +0000)]
[LoopGuardWidening] Split out a loop pass version of GuardWidening
The idea is to have a pass which performs the same transformation as GuardWidening, but can be run within a loop pass manager without disrupting the pass manager structure. As demonstrated by the test case, this doesn't quite get there because of issues with post dom, but it gives a good step in the right direction. the motivation is purely to reduce compile time since we can now preserve locality during the loop walk.
This patch only includes a legacy pass. A follow up will add a new style pass as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331060
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Sanjay Patel [Fri, 27 Apr 2018 16:33:35 +0000 (16:33 +0000)]
[docs] add fp-cast-overflow-workaround options to release notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331059
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Nirav Dave [Fri, 27 Apr 2018 16:16:06 +0000 (16:16 +0000)]
[MC] Undo spurious commit added into r331052.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331055
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Simon Pilgrim [Fri, 27 Apr 2018 16:11:57 +0000 (16:11 +0000)]
[X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
This removes all the HADD/HSUB PS/PD InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331054
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Nirav Dave [Fri, 27 Apr 2018 16:11:24 +0000 (16:11 +0000)]
[MC] Provide default value for IsResolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331052
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Simon Pilgrim [Fri, 27 Apr 2018 15:50:33 +0000 (15:50 +0000)]
[X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331051
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Simon Dardis [Fri, 27 Apr 2018 15:49:49 +0000 (15:49 +0000)]
[mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331050
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Nirav Dave [Fri, 27 Apr 2018 15:45:54 +0000 (15:45 +0000)]
[MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331048
91177308-0d34-0410-b5e6-
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Nirav Dave [Fri, 27 Apr 2018 15:45:27 +0000 (15:45 +0000)]
[MC] Allow MCAssembler to be constructed without all subcomponents. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331047
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Francis Visoiu Mistrih [Fri, 27 Apr 2018 15:30:54 +0000 (15:30 +0000)]
[AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true
Put the first ldp at the end, so that the load-store optimizer can run
and merge the ldp and the add into a post-index ldp.
This didn't work in case no frame was needed and resulted in code size
regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331044
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Kostya Kortchinsky [Fri, 27 Apr 2018 15:10:50 +0000 (15:10 +0000)]
[CMake] Enable warnings for runtimes
Summary:
`HandleLLVMOptions` adds `-w` to the cflags if `LLVM_ENABLE_WARNINGS` is not on.
With `-w`, `check_cxx_compiler_flag` doesn't error out for unsupported flags
(for example `-mcrc` on x86_64), and those flags end up being detected as
working - and really they aren't.
I am not entirely sure what the best way to solve this is, but setting
`LLVM_ENABLE_WARNINGS` prior to including `HandleLLVMOptions` does the job.
Reviewers: phosek, beanz
Reviewed By: phosek
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D46079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331042
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Jonas Paulsson [Fri, 27 Apr 2018 14:09:03 +0000 (14:09 +0000)]
[SystemZ] Remove scheduling info from some Pseudo instructions (NFC).
If the MachineInstr uses a custom inserter and is then erased after
instruction selection, there is no use for mapping it to a sched class.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331040
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Florian Hahn [Fri, 27 Apr 2018 13:52:51 +0000 (13:52 +0000)]
[LoopInterchange] Allow some loops with PHI nodes in the exit block.
We currently support LCSSA PHI nodes in the outer loop exit, if their
incoming values do not come from the outer loop latch or if the
outer loop latch has a single predecessor. In that case, the outer loop latch
will be executed only if the inner loop gets executed. If we have multiple
predecessors for the outer loop latch, it may be executed even if the inner
loop does not get executed.
This is a first step to support the case described in
https://bugs.llvm.org/show_bug.cgi?id=30472
Reviewers: efriedma, karthikthecool, mcrosier
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331037
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Oliver Stannard [Fri, 27 Apr 2018 13:45:32 +0000 (13:45 +0000)]
[AArch64] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the AArch64 dot-product instructions introduced in
v8.2-A.
Differential revisioon: https://reviews.llvm.org/D46107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331036
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Benjamin Kramer [Fri, 27 Apr 2018 13:36:05 +0000 (13:36 +0000)]
[NVPTX] Turn on Loop/SLP vectorization
Since PTX has grown a <2 x half> datatype vectorization has become more
important. The late LoadStoreVectorizer intentionally only does loads
and stores, but now arithmetic has to be vectorized for optimal
throughput too.
This is still very limited, SLP vectorization happily creates <2 x half>
if it's a legal type but there's still a lot of register moving
happening to get that fed into a vectorized store. Overall it's a small
performance win by reducing the amount of arithmetic instructions.
I haven't really checked what the loop vectorizer does to PTX code, the
cost model there might need some more tweaks. I didn't see it causing
harm though.
Differential Revision: https://reviews.llvm.org/D46130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331035
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Simon Pilgrim [Fri, 27 Apr 2018 13:32:42 +0000 (13:32 +0000)]
[X86] Replace some system instruction instregex single matches with instrs entry. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331034
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Aleksandar Beserminji [Fri, 27 Apr 2018 13:30:27 +0000 (13:30 +0000)]
[mips] Fix how compiler fuse instructions to fmadd/fmsub
This patch makes compiler does not fuse fmul and fadd/fsub into
fmadd/fmsub by default. Instead, -fp-contract=fast option can
be used when such behavior is desired.
Differential Revision: https://reviews.llvm.org/D46057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331033
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Oliver Stannard [Fri, 27 Apr 2018 12:50:40 +0000 (12:50 +0000)]
[ARM] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the ARM dot-product instructions introduced in
v8.2-A.
Differential revision: https://reviews.llvm.org/D46106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331032
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Alex Bradbury [Fri, 27 Apr 2018 11:50:30 +0000 (11:50 +0000)]
[RISCV] Add remat.ll test case
This test case demonstrates suboptimal codegen due to the fact that simple
constants aren't recognised as rematerialisable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331028
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David Green [Fri, 27 Apr 2018 11:29:49 +0000 (11:29 +0000)]
[ARM] Enable misched for R52.
Back when the R52 schedule was added in rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52,
removing the need to manually specify compiler flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331027
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Mikhail Maltsev [Fri, 27 Apr 2018 09:12:12 +0000 (09:12 +0000)]
[IR] Do not assume that function pointers are aligned
Summary:
The value tracking analysis uses function alignment to infer that the
least significant bits of function pointers are known to be zero.
Unfortunately, this is not correct for ARM targets: the least
significant bit of a function pointer stores the ARM/Thumb state
information (i.e., the LSB is set for Thumb functions and cleared for
ARM functions).
The original approach (https://reviews.llvm.org/D44781) introduced a
new field for function pointer alignment in the DataLayout structure
to address this. But it seems unlikely that optimizations based on
function pointer alignment would bring much benefit in practice to
justify the additional maintenance burden, so this patch simply
assumes that function pointer alignment is always unknown.
Reviewers: javed.absar, efriedma
Reviewed By: efriedma
Subscribers: kristof.beyls, llvm-commits, hfinkel, rogfer01
Differential Revision: https://reviews.llvm.org/D46110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331025
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Petar Jovanovic [Fri, 27 Apr 2018 09:12:08 +0000 (09:12 +0000)]
[mips] Add support for Virtualization ASE
This includes
Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,
Assembler directives: .set virt, .set novirt, .module virt, .module novirt
Attribute: virt
.MIPS.abiflags: VZ (0x100)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331024
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Serguei Katkov [Fri, 27 Apr 2018 08:02:50 +0000 (08:02 +0000)]
[SCEV] Add trivial case handling for umin utilities. NFC.
Reviewers: sanjoy, mkazantsev
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331022
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Serguei Katkov [Fri, 27 Apr 2018 03:56:53 +0000 (03:56 +0000)]
[SCEV] Introduce bulk umin creation utilities
Add new umin creation method which accepts a list of operands.
SCEV does not represents umin which is required in getExact, so
it transforms umin to umax with not. As a result the transformation of
tree of max to max with several operands does not work.
We just use the new introduced method for creation umin from several operands.
Reviewers: sanjoy, mkazantsev
Reviewed By: sanjoy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331015
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Matt Morehouse [Fri, 27 Apr 2018 01:48:09 +0000 (01:48 +0000)]
Revert "[SimplifyLibcalls] Replace locked IO with unlocked IO"
This reverts r331002 due to sanitizer bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331011
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Eli Friedman [Fri, 27 Apr 2018 00:32:24 +0000 (00:32 +0000)]
[LowerTypeTests] Mark .cfi.jumptable nounwind.
It doesn't unwind, and the wrong marking leads to the creation of an
.eh_frame section when it isn't necessary.
Differential Revision: https://reviews.llvm.org/D46082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331008
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Eli Friedman [Fri, 27 Apr 2018 00:21:34 +0000 (00:21 +0000)]
[MachineOutliner] Don't outline from functions with a section marking.
The program might have unusual expectations for functions; for example,
the Linux kernel's build system warns if it finds references from .text
to .init.data.
I'm not sure this is something we actually want to make any guarantees
about (there isn't any explicit rule that would disallow outlining
in this case), but we might want to be conservative anyway.
Differential Revision: https://reviews.llvm.org/D46091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331007
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Sam Clegg [Fri, 27 Apr 2018 00:17:24 +0000 (00:17 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331006
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Sam Clegg [Fri, 27 Apr 2018 00:17:21 +0000 (00:17 +0000)]
[WebAssembly] Section symbols must have local binding
Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll.
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331005
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David Bolvansky [Thu, 26 Apr 2018 22:31:43 +0000 (22:31 +0000)]
[SimplifyLibcalls] Replace locked IO with unlocked IO
Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed,
Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer
Subscribers: lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D45736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331002
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Matt Davis [Thu, 26 Apr 2018 22:30:40 +0000 (22:30 +0000)]
[MCA] [NFC] Remove unused Index formal from ResourceManager::issueInstruction
Summary: The instruction index was never referenced in the body. Just a minor cleanup.
Reviewers: andreadb
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331001
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Matt Davis [Thu, 26 Apr 2018 21:55:45 +0000 (21:55 +0000)]
[Docs] Escape the @ symbol, so that it appears in documentation output. [NFC]
Summary:
The '@' character is a special character in Doxygen. In a handful of cases we were not escaping this character which resulted in llvm intrinsics not being rendered properly. Specifically, the @llvm part was removed.
For example, see https://llvm.org/doxygen/classllvm_1_1AssumptionCache.html. There are a few references to '.assume' without the @llvm. prefix. This patch corrects this.
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D45981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330998
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Chandler Carruth [Thu, 26 Apr 2018 21:46:01 +0000 (21:46 +0000)]
[x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsics
The LLVM commit introduces a crash in LLVM's instruction selection.
I filed http://llvm.org/PR37260 with the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330997
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Roman Lebedev [Thu, 26 Apr 2018 21:41:56 +0000 (21:41 +0000)]
[InstCombine][NFC] Regenerate checks in or-xor.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330996
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Reid Kleckner [Thu, 26 Apr 2018 21:13:59 +0000 (21:13 +0000)]
Fix WAsm dwarfdump.ll test on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330995
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Roman Lebedev [Thu, 26 Apr 2018 21:13:09 +0000 (21:13 +0000)]
[InstCombine][NFC] Regenerate checks in and-or-not.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330994
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Adrian Prantl [Thu, 26 Apr 2018 20:59:58 +0000 (20:59 +0000)]
Revert "Fix a bug that prevents global variables from having a DW_OP_deref."
This reverts commit r3309704 while investigating bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330993
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Sanjoy Das [Thu, 26 Apr 2018 20:52:28 +0000 (20:52 +0000)]
[InstCombine] Simplify Add with remainder expressions as operands.
Summary:
Simplify integer add expression X % C0 + (( X / C0 ) % C1) * C0 to
X % (C0 * C1). This is a common pattern seen in code generated by the XLA
GPU backend.
Add test cases for this new optimization.
Patch by Bixia Zheng!
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: efriedma, craig.topper, lebedev.ri, llvm-commits, jlebar
Differential Revision: https://reviews.llvm.org/D45976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330992
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Sanjoy Das [Thu, 26 Apr 2018 20:52:27 +0000 (20:52 +0000)]
Add test cases to prepare for the optimization that simplifies Add with
remainder expressions as operands.
Summary:
Add test cases to prepare for the new optimization that Simplifies integer add
expression X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1).
Patch by Bixia Zheng!
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330991
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Roman Tereshin [Thu, 26 Apr 2018 20:22:17 +0000 (20:22 +0000)]
[GlobalISel] Reporting rules covered as part of the InstructionSelect's debug-only printing
The main goal of this change is to make it much easier to track which
rules are actually covered by Testgen'erated regression tests.
Reviewers: aemerson, dsanders
Differential Revision: https://reviews.llvm.org/D46095
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330988
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Roman Lebedev [Thu, 26 Apr 2018 20:07:17 +0000 (20:07 +0000)]
[InstCombine][NFC] add2.ll: add a few commutative checks.
Fixes some missing test coverage in InstCombineAddSub.cpp, visitAdd()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330986
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Roman Lebedev [Thu, 26 Apr 2018 20:07:12 +0000 (20:07 +0000)]
[InstCombine][NFC] Autogenerate checks in add2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330985
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Simon Atanasyan [Thu, 26 Apr 2018 19:55:28 +0000 (19:55 +0000)]
[mips] Accept 32-bit offsets for lb and lbu commands
`lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts
larger offsets for these commands. If an offset does not fit in 16-bit
range, `lb` command is translated into lui/lb or lui/addu/lb series.
It's interesting that initially LLVM assembler supported this feature,
but later it was broken.
This patch restores support for 32-bit offsets. It replaces `mem_simm16`
operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand.
This operand is intended to check that offset fits to the same size as
using for pointers. Later we will be able to extend this rule and
accepts 64-bit offsets when it is possible.
Some issues remain:
- The regression also affects LD, SD, LH, LHU commands. I'm going
to fix them by a separate patch.
- GAS accepts any 32-bit values as an offset. Now LLVM accepts signed
16-bit values and this patch extends the range to signed 32-bit offsets.
In other words, the following code accepted by GAS and still triggers
an error by LLVM:
```
lb $4, 0x80000004
# gas
lui a0, 0x8000
lb a0, 4(a0)
```
- In case of 64-bit pointers GAS accepts a 64-bit offset and translates
it to the li/dsll/lb series of commands. LLVM still rejects it.
Probably this feature has never been implemented in LLVM. This issue
is for a separate patch.
```
lb $4, 0x800000001
# gas
li a0, 0x8000
dsll a0, a0, 0x14
lb a0, 4(a0)
```
Differential Revision: https://reviews.llvm.org/D45020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330983
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Sam Clegg [Thu, 26 Apr 2018 19:27:28 +0000 (19:27 +0000)]
[WebAssembly] Write DWARF data into wasm object file
- Writes ".debug_XXX" into corresponding custom sections.
- Writes relocation records into "reloc.debug_XXX" sections.
Patch by Yury Delendik!
Differential Revision: https://reviews.llvm.org/D44184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330982
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Matt Arsenault [Thu, 26 Apr 2018 19:21:37 +0000 (19:21 +0000)]
DAG: Fix not legalizing vector fcanonicalizes
If an fcanoncialize was done on a vector type that was legal,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330981
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Matt Arsenault [Thu, 26 Apr 2018 19:21:32 +0000 (19:21 +0000)]
AMDGPU: Extend extract_vector_elt fneg combine to fabs
Fixes a regression in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330980
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Matt Arsenault [Thu, 26 Apr 2018 19:21:26 +0000 (19:21 +0000)]
AMDGPU: Consolidate SubtargetPredicate definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330979
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Justin Bogner [Thu, 26 Apr 2018 19:15:25 +0000 (19:15 +0000)]
Specify REQUIRES: default_triple in a few tests
These were all failing when specifying LLVM_DEFAULT_TARGET_TRIPLE=''.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330977
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Geoff Berry [Thu, 26 Apr 2018 18:50:45 +0000 (18:50 +0000)]
[AArch64] Fix scavenged spill slot base when stack realignment required.
Summary:
Use the FP for scavenged spill slot accesses to prevent corruption of
the callee-save region when the SP is re-aligned.
Based on problem and patch reported by @paulwalker-arm
This is an alternative to solution proposed in D45770
Reviewers: t.p.northover, paulwalker-arm, thegameg, javed.absar
Subscribers: qcolombet, mcrosier, paulwalker-arm, kristof.beyls, rengolin, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330976
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Roman Lebedev [Thu, 26 Apr 2018 18:44:37 +0000 (18:44 +0000)]
[NFC][InstCombine] rem.ll: add a few commutative tests.
This closes a gap in missing test coverage in
isKnownToBeAPowerOfTwo() from ValueTracking.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330975
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Roman Lebedev [Thu, 26 Apr 2018 18:44:32 +0000 (18:44 +0000)]
[NFC][InstCombine] Regenerate rem.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330974
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Alexander Shaposhnikov [Thu, 26 Apr 2018 18:28:17 +0000 (18:28 +0000)]
[llvm-objcopy] Implement --redefine-sym option
This diff implements --redefine-sym option
for changing the name of a symbol.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D46029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330973
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Michael Berg [Thu, 26 Apr 2018 18:17:58 +0000 (18:17 +0000)]
augmenting description for fcmp fmf - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330972
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Adrian Prantl [Thu, 26 Apr 2018 18:17:04 +0000 (18:17 +0000)]
Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.
rdar://problem/
39741860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330970
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Sam Clegg [Thu, 26 Apr 2018 18:15:32 +0000 (18:15 +0000)]
[WebAssembly] Add version to object file metadata
Summary: See https://github.com/WebAssembly/tool-conventions/issues/54
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330969
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