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Hal Finkel [Wed, 3 Apr 2013 17:44:56 +0000 (17:44 +0000)]
Cleanup PPC reciprocal-estimate functionality
Incorporating review feedback from Bill Schmidt on r178617. No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672
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Vincent Lejeune [Wed, 3 Apr 2013 16:49:34 +0000 (16:49 +0000)]
R600: Factorize maximum alu per clause in a single location
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667
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Aaron Ballman [Wed, 3 Apr 2013 16:28:24 +0000 (16:28 +0000)]
Testing for Visual Studio 2010 SP1 or greater before calling the _xgetbv intrinsic. This also fixes a minor code formatting issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178666
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Vincent Lejeune [Wed, 3 Apr 2013 16:24:09 +0000 (16:24 +0000)]
R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178665
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Vincent Lejeune [Wed, 3 Apr 2013 16:24:04 +0000 (16:24 +0000)]
R600: Consider KILLGT as an ALU instruction
Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178664
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Eli Bendersky [Wed, 3 Apr 2013 15:33:45 +0000 (15:33 +0000)]
Measure time that IR parsing took as part of the -time-passes measurement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178662
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Hal Finkel [Wed, 3 Apr 2013 14:40:18 +0000 (14:40 +0000)]
PPC: Enable FRES and FRSQRTE on the default PPC64 description
I discussed this with Bill Schmidt on IRC, and it was decided that this is a
safe and reasonable default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659
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Hal Finkel [Wed, 3 Apr 2013 14:40:16 +0000 (14:40 +0000)]
PPC: Add a FIXME regarding the non-working fma+fneg Altivec pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658
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Hal Finkel [Wed, 3 Apr 2013 14:25:55 +0000 (14:25 +0000)]
Remove some obsolete PowerPC/README entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178657
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Ulrich Weigand [Wed, 3 Apr 2013 14:08:13 +0000 (14:08 +0000)]
More direct types in PowerPC AltiVec intrinsics.
This patch follows up on work done by Bill Schmidt in r178277,
and replaces most of the remaining uses of VRRC in ISEL DAG patterns.
The resulting .inc files are identical except for comments, so
no change in code generation is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656
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Bill Schmidt [Wed, 3 Apr 2013 13:05:44 +0000 (13:05 +0000)]
Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.
For this we need to use a libcall. Previously LLVM didn't implement
libcall support for frem, so I've added it in the usual
straightforward manner. A test case from the bug report is included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639
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Tim Northover [Wed, 3 Apr 2013 12:31:29 +0000 (12:31 +0000)]
AArch64: implement ETMv4 trace system registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637
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Aaron Ballman [Wed, 3 Apr 2013 12:25:06 +0000 (12:25 +0000)]
Second pass at addressing PR15351 by explicitly checking for AVX support
when getting the host processor information. It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178636
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Timur Iskhodzhanov [Wed, 3 Apr 2013 12:17:15 +0000 (12:17 +0000)]
Temporarily relax the WIN32 checks in the SRet test to fix the Atom D2700 bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178635
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Timur Iskhodzhanov [Wed, 3 Apr 2013 11:27:54 +0000 (11:27 +0000)]
Fix SRet for thiscall in i686-pc-win32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634
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Tim Northover [Wed, 3 Apr 2013 11:19:16 +0000 (11:19 +0000)]
AArch64: switch patterns to be type-based rather than RegClass-based
It's a bit of churn in the blame log, but I think there are real benefits to
the newer system so I'm making the change in one go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633
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Eric Christopher [Wed, 3 Apr 2013 05:29:58 +0000 (05:29 +0000)]
Fix grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178624
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Eric Christopher [Wed, 3 Apr 2013 05:26:07 +0000 (05:26 +0000)]
Remove ZeroOrMore from the option description. We don't need it here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178623
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Jakob Stoklund Olesen [Wed, 3 Apr 2013 04:41:44 +0000 (04:41 +0000)]
Add 64-bit compare + branch for SPARC v9.
The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.
This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178621
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Hal Finkel [Wed, 3 Apr 2013 04:03:58 +0000 (04:03 +0000)]
Remove some unsupported-feature comments from PPC.td
These refer to the reciprocal estimate support recently committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618
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Hal Finkel [Wed, 3 Apr 2013 04:01:11 +0000 (04:01 +0000)]
Use PPC reciprocal estimates with Newton iteration in fast-math mode
When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.
I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617
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Rafael Espindola [Wed, 3 Apr 2013 03:13:19 +0000 (03:13 +0000)]
Fix the fde encoding used by mips to match gas.
This finally fixes the encoding. The patch also
* Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking
the wrong value.
* Merge fde-reloc.s and eh-frame.s into a single test, since the only difference
was the run lines.
* Don't blindly test the content of the entire .eh_frame section. It makes it
hard to anyone actually fixing a bug and hitting a difference in a binary
blob. Instead, use a CHECK for each field and document what is being checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615
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Aaron Ballman [Wed, 3 Apr 2013 03:11:39 +0000 (03:11 +0000)]
Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn't understand the xgetbv instruction for some reason. Will revisit when time permits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614
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Michael Gottesman [Wed, 3 Apr 2013 02:57:24 +0000 (02:57 +0000)]
Remove an optimization where we were changing an objc_autorelease into an objc_autoreleaseReturnValue.
The semantics of ARC implies that a pointer passed into an objc_autorelease
must live until some point (potentially down the stack) where an
autorelease pool is popped. On the other hand, an
objc_autoreleaseReturnValue just signifies that the object must live
until the end of the given function at least.
Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in
terms of the semantics of ARC* implying that performing the given
strength reduction without any knowledge of how this relates to
the autorelease pool pop that is further up the stack violates the
semantics of ARC.
*Even though objc_autoreleaseReturnValue if you know that no RV
optimization will occur is more computationally expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178612
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Michael Gottesman [Wed, 3 Apr 2013 01:57:16 +0000 (01:57 +0000)]
Improved comment. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178605
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Aaron Ballman [Wed, 3 Apr 2013 01:39:37 +0000 (01:39 +0000)]
Attempting to fix the build on older GCC versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178604
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Rafael Espindola [Wed, 3 Apr 2013 01:07:53 +0000 (01:07 +0000)]
Remove anonymous namespace.
Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage":
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value':
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281: instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >'
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627: instantiated from here
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178600
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Aaron Ballman [Wed, 3 Apr 2013 00:33:32 +0000 (00:33 +0000)]
This patch addresses PR15351 by explicitly checking for AVX support
when getting the host processor information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178598
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Rafael Espindola [Tue, 2 Apr 2013 23:56:40 +0000 (23:56 +0000)]
Use yaml::IO in yaml2obj.cpp.
The generic structs and specializations will be refactored when obj2yaml is
changed to use yaml::IO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178593
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Eric Christopher [Tue, 2 Apr 2013 23:06:40 +0000 (23:06 +0000)]
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589
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Akira Hatanaka [Tue, 2 Apr 2013 23:02:07 +0000 (23:02 +0000)]
[mips] Small update to the implementation of eh.return for Mips.
This patch initializes t9 to the handler address, but only if the relocation
model is pic. This handles the case where handler to which eh.return jumps
points to the start of the function.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588
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Eric Christopher [Tue, 2 Apr 2013 22:55:56 +0000 (22:55 +0000)]
Support and test template arguments for unions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178586
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Eric Christopher [Tue, 2 Apr 2013 22:55:52 +0000 (22:55 +0000)]
Reformat arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178585
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Akira Hatanaka [Tue, 2 Apr 2013 22:53:58 +0000 (22:53 +0000)]
[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.
This patch fixes the following two tests which have been failing on
llvm-mips-linux builder since r178403:
LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll
LLVM :: Analysis/Profiling/load-branch-weights-loops.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178584
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NAKAMURA Takumi [Tue, 2 Apr 2013 22:35:08 +0000 (22:35 +0000)]
llvm/test/CodeGen/X86: Unmark them out of XFAIL:cygming, in atomic{32|64}.ll and handle-move.ll, corresponding to r178549.
This reverts r176808, r176798, and r177914.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178583
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 22:27:45 +0000 (22:27 +0000)]
Allow MachineTraceMetrics to be used when the model has no resources.
It it still possible to extract information from itineraries, for
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178582
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Jakub Staszak [Tue, 2 Apr 2013 20:02:36 +0000 (20:02 +0000)]
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178567
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Chad Rosier [Tue, 2 Apr 2013 20:02:33 +0000 (20:02 +0000)]
[ms-inline asm] Add support for parsing variables with namespace alias
qualifiers.
This patch only adds support for parsing these identifiers in the
X86AsmParser. The front-end interface isn't capable of looking up
these identifiers at this point in time. The end result is the
compiler now errors during object file emission, rather than at
parse time. Test case coming shortly.
Part of rdar://
13499009 and PR13340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178566
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Manman Ren [Tue, 2 Apr 2013 19:50:49 +0000 (19:50 +0000)]
Add MDBuilder utilities for path-aware TBAA.
Add utilities to create struct nodes in TBAA type DAG and to create path-aware
tags. The format of struct nodes in TBAA type DAG: a unique name, a list of
fields with field offsets and field types. The format of path-aware tags:
a base type in TBAA type DAG, an access type and an offset relative to the base
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178564
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Bill Schmidt [Tue, 2 Apr 2013 18:37:08 +0000 (18:37 +0000)]
Fix PR15630: Replace faulty stdcx. with stwcx.
When doing a partword atomic operation, a lwarx was being paired with
a stdcx. instead of a stwcx. when compiling for a 64-bit target. The
target has nothing to do with it in this case; we always need a stwcx.
Thanks to Kai Nacke for reporting the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 18:26:45 +0000 (18:26 +0000)]
Don't attempt MTM heuristics without a scheduling model present.
This should fix the PPC buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178558
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 17:49:51 +0000 (17:49 +0000)]
Count processor resources individually in MachineTraceMetrics.
The new instruction scheduling models provide information about the
number of cycles consumed on each processor resource. This makes it
possible to estimate ILP more accurately than simply counting
instructions / issue width.
The functions getResourceDepth() and getResourceLength() now identify
the limiting processor resource, and return a cycle count based on that.
This gives more precise resource information, particularly in traces
that use one resource a lot more than others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178553
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Chad Rosier [Tue, 2 Apr 2013 16:31:41 +0000 (16:31 +0000)]
[fast-isel] Use the correct API to disable FastLowerArguments for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549
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Arnold Schwaighofer [Tue, 2 Apr 2013 15:58:51 +0000 (15:58 +0000)]
DAGCombiner: Merge store/loads when we have extload/truncstores
This is helps on architectures where i8,i16 are not legal but we have byte, and
short loads/stores. Allowing us to merge copies like the one below on ARM.
copy(char *a, char *b, int n) {
do {
int t0 = a[0];
int t1 = a[1];
b[0] = t0;
b[1] = t1;
radar://
13536387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546
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Preston Gurd [Tue, 2 Apr 2013 14:25:06 +0000 (14:25 +0000)]
Simplify test cases for Atom preferring call register indirect over
call memory indirect (32 and 64 bit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178541
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Justin Holewinski [Tue, 2 Apr 2013 12:37:11 +0000 (12:37 +0000)]
[NVPTX] Fix a few style issues in NVVMReflect
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178536
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Bill Wendling [Tue, 2 Apr 2013 08:16:45 +0000 (08:16 +0000)]
Use a worklist to avoid a sneaky iterator invalidation.
The iterator could be invalidated when it's recursively deleting a whole bunch
of constant expressions in a constant initializer.
Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was
run on a `.ll' file, it wouldn't crash. This is why the test first pushes the
`.ll' file through `llvm-as' before feeding it to `opt'.
PR15440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178531
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:28 +0000 (04:09 +0000)]
Add 64-bit load and store instructions.
There is only a few new instructions, the rest is handled with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:23 +0000 (04:09 +0000)]
Basic 64-bit ALU operations.
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to
add patterns to use them for both i32 and i64 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:17 +0000 (04:09 +0000)]
Materialize 64-bit immediates.
The last resort pattern produces 6 instructions, and there are still
opportunities for materializing some immediates in fewer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178526
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:12 +0000 (04:09 +0000)]
Add 64-bit shift instructions.
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.
This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:06 +0000 (04:09 +0000)]
Add predicates for distinguishing 32-bit and 64-bit modes.
The 'sparc' architecture produces 32-bit code while 'sparcv9' produces
64-bit code.
It is also possible to run 32-bit code using SPARC v9 instructions with:
llc -march=sparc -mattr=+v9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178524
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:02 +0000 (04:09 +0000)]
Add support for 64-bit calling convention.
This is far from complete, but it is enough to make it possible to write
test cases using i64 arguments.
Missing features:
- Floating point arguments.
- Receiving arguments on the stack.
- Calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523
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Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:08:54 +0000 (04:08 +0000)]
Add an I64Regs register class for 64-bit registers.
We are going to use the same registers for 32-bit and 64-bit values, but
in two different register classes. The I64Regs register class has a
larger spill size and alignment.
The addition of an i64 register class confuses TableGen's type
inference, so it is necessary to clarify the type of some immediates and
the G0 register.
In 64-bit mode, pointers are i64 and should use the I64Regs register
class. Implement getPointerRegClass() to dynamically provide the pointer
register class depending on the subtarget. Use ptr_rc and iPTR for
memory operands.
Finally, add the i64 type to the IntRegs register class. This register
class is not used to hold i64 values, I64Regs is for that. The type is
required to appease TableGen's type checking in output patterns like this:
def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and
TableGen doesn't know to check the type of register sub-classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522
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Hal Finkel [Tue, 2 Apr 2013 03:29:51 +0000 (03:29 +0000)]
Fix typo in PPCISelLowering
Thanks to Bill Schmidt for finding this in review of r178480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521
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Andrew Trick [Tue, 2 Apr 2013 01:58:47 +0000 (01:58 +0000)]
The divide unit is not pipeline, but it is still buffered.
Buffered means a later divide may be executed out-of-order while a
prior divide is sitting (buffered) in a reservation station.
You can tell it's not pipelined, because operations that use it
reserve it for more than one cycle:
def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
let Latency = 25;
let ResourceCycles = [1, 10];
}
We don't currently distinguish between an unpipeline operation and one
that is split into multiple micro-ops requiring the same unit. Except
that the later may have NumMicroOps > 1 if they also consume
issue/dispatch resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519
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Chris Lattner [Mon, 1 Apr 2013 23:00:01 +0000 (23:00 +0000)]
unindent the file to follow coding standards, change class doc comment
to be correct. No functionality or behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178511
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NAKAMURA Takumi [Mon, 1 Apr 2013 22:05:58 +0000 (22:05 +0000)]
Target/R600: Fix CMake build to add missing files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178508
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Jack Carter [Mon, 1 Apr 2013 21:55:15 +0000 (21:55 +0000)]
Mips direct object exception handling regression
Revision 177141 caused a regression in all but
mips64 little endian. That is because none of the
other Mips targets had test cases checking the
contents of the .eh_frame section. This patch fixes
both the llvm code and adds an assembler test case
to include the current 4 flavors.
The test cases unfortunately rely on llvm-objdump. A
preferable method would be to use a pretty printer output
such as what readelf -wf <elf_file> would give.
I also changed the name of the test case to correct a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178506
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Vincent Lejeune [Mon, 1 Apr 2013 21:48:05 +0000 (21:48 +0000)]
R600: Add support for native control flow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178505
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Vincent Lejeune [Mon, 1 Apr 2013 21:47:53 +0000 (21:47 +0000)]
R600/SI: Share code recording ShaderTypeAttribute between generations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178504
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Vincent Lejeune [Mon, 1 Apr 2013 21:47:42 +0000 (21:47 +0000)]
R600: Emit CF_ALU and use true kcache register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503
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Eli Bendersky [Mon, 1 Apr 2013 19:47:56 +0000 (19:47 +0000)]
Fix top-comment header and some indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178492
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Hal Finkel [Mon, 1 Apr 2013 18:42:58 +0000 (18:42 +0000)]
Fix a bad assert in PPCTargetLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489
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Hal Finkel [Mon, 1 Apr 2013 18:18:44 +0000 (18:18 +0000)]
Add triple to test/CodeGen/PowerPC/stfiwx-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178486
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Shuxin Yang [Mon, 1 Apr 2013 18:13:05 +0000 (18:13 +0000)]
Correct assertion condition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178484
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Arnold Schwaighofer [Mon, 1 Apr 2013 18:12:58 +0000 (18:12 +0000)]
Merge load/store sequences with adresses: base + index + offset
We would also like to merge sequences that involve a variable index like in the
example below.
int index = *idx++
int i0 = c[index+0];
int i1 = c[index+1];
b[0] = i0;
b[1] = i1;
By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.
The dag for the code above will look something like:
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i8 load %index))))
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (add (i8 load %index)
(i8 1))))
vs
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
radar://
13536387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483
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Hal Finkel [Mon, 1 Apr 2013 17:52:07 +0000 (17:52 +0000)]
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480
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Hal Finkel [Mon, 1 Apr 2013 17:02:06 +0000 (17:02 +0000)]
Use ImmToIdxMap.count in PPCRegisterInfo
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178473
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Hal Finkel [Mon, 1 Apr 2013 16:31:56 +0000 (16:31 +0000)]
Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178472
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Hal Finkel [Mon, 1 Apr 2013 15:58:15 +0000 (15:58 +0000)]
Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470
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Nadav Rotem [Mon, 1 Apr 2013 15:53:30 +0000 (15:53 +0000)]
Add support for vector data types in the LLVM interpreter.
Patch by:
Veselov, Yuri <Yuri.Veselov@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178469
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Hal Finkel [Mon, 1 Apr 2013 15:37:53 +0000 (15:37 +0000)]
Treat PPCISD::STFIWX like the memory opcode that it is
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.
No functionality change intended (although there could be optimization benefits
from preserving the MMO information).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178468
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Duncan Sands [Mon, 1 Apr 2013 13:46:15 +0000 (13:46 +0000)]
Remove unused typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178462
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Arnold Schwaighofer [Mon, 1 Apr 2013 13:07:05 +0000 (13:07 +0000)]
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
Incooperate Andrew's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460
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Benjamin Kramer [Mon, 1 Apr 2013 10:23:49 +0000 (10:23 +0000)]
X86TTI: Add accurate costs for itofp operations, based on the actual instruction counts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178459
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Joe Abbey [Mon, 1 Apr 2013 02:28:07 +0000 (02:28 +0000)]
Whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178454
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Vincent Lejeune [Sun, 31 Mar 2013 19:33:04 +0000 (19:33 +0000)]
R600: Emit native instructions for tex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178452
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Duncan Sands [Sun, 31 Mar 2013 17:44:09 +0000 (17:44 +0000)]
There is no longer any need to silence this compiler warning as the warning has
been turned off globally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451
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Hal Finkel [Sun, 31 Mar 2013 14:43:31 +0000 (14:43 +0000)]
Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450
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Benjamin Kramer [Sun, 31 Mar 2013 12:49:15 +0000 (12:49 +0000)]
X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448
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Hal Finkel [Sun, 31 Mar 2013 10:12:51 +0000 (10:12 +0000)]
Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446
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Hal Finkel [Sun, 31 Mar 2013 01:58:02 +0000 (01:58 +0000)]
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438
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Benjamin Kramer [Sat, 30 Mar 2013 21:28:18 +0000 (21:28 +0000)]
DAGCombine: visitXOR can replace a node without returning it, bail out in that case.
Fixes the crash reported in PR15608.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429
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Justin Holewinski [Sat, 30 Mar 2013 16:41:14 +0000 (16:41 +0000)]
Add start of user documentation for NVPTX
Summary: This is the beginning of user documentation for the NVPTX back-end. I want to ensure I am integrating this properly into the rest of the LLVM documentation.
Differential Revision: http://llvm-reviews.chandlerc.com/D600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178428
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Benjamin Kramer [Sat, 30 Mar 2013 16:21:50 +0000 (16:21 +0000)]
Change '@SECREL' suffix to GAS-compatible '@SECREL32'.
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.
20120920 here).
Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427
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Sean Silva [Sat, 30 Mar 2013 15:33:02 +0000 (15:33 +0000)]
[docs] llvmbugs is not the place for patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178426
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Sean Silva [Sat, 30 Mar 2013 15:33:01 +0000 (15:33 +0000)]
[docs] Annotate mailing lists with their "name".
Nobody says "the developer's list" or "commits archive"; they always say
"llvmdev" or "llvm-commits". It makes sense for our documentation to
at least make that association explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178425
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Sean Silva [Sat, 30 Mar 2013 15:32:54 +0000 (15:32 +0000)]
[docs] Reorganize mailing lists.
Order them roughly by "which one should a newbie join first".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178424
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Sean Silva [Sat, 30 Mar 2013 15:32:51 +0000 (15:32 +0000)]
[docs] Pull IRC and Mailing Lists under a new "Community" heading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178423
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Sean Silva [Sat, 30 Mar 2013 15:32:50 +0000 (15:32 +0000)]
[docs] The GEP FAQ is not "design and overview"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178422
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Sean Silva [Sat, 30 Mar 2013 15:32:47 +0000 (15:32 +0000)]
[docs] Put DeveloperPolicy under "Development Process Documentation"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178421
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Benjamin Kramer [Sat, 30 Mar 2013 15:23:08 +0000 (15:23 +0000)]
Put private class into an anonmyous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178420
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Justin Holewinski [Sat, 30 Mar 2013 14:29:30 +0000 (14:29 +0000)]
[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417
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Justin Holewinski [Sat, 30 Mar 2013 14:29:25 +0000 (14:29 +0000)]
[NVPTX] Add NVVMReflect pass to allow compile-time selection of
specific code paths.
This allows us to write code like:
if (__nvvm_reflect("FOO"))
// Do something
else
// Do something else
and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416
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Justin Holewinski [Sat, 30 Mar 2013 14:29:21 +0000 (14:29 +0000)]
[NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415
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Benjamin Kramer [Sat, 30 Mar 2013 13:07:51 +0000 (13:07 +0000)]
Object: Turn a couple of degenerate for loops into while loops.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178413
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Shuxin Yang [Sat, 30 Mar 2013 02:15:01 +0000 (02:15 +0000)]
Implement XOR reassociation. It is based on following rules:
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
only useful when c1=c2
rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2
It reduces an application's size (in terms of # of instructions) by 8.9%.
Reviwed by Pete Cooper. Thanks a lot!
rdar://
13212115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178409
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Akira Hatanaka [Sat, 30 Mar 2013 02:14:45 +0000 (02:14 +0000)]
[mips] Add patterns for DSP indexed load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408
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Akira Hatanaka [Sat, 30 Mar 2013 02:01:48 +0000 (02:01 +0000)]
[mips] Define reg+imm load/store pattern templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407
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