hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory

The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND()
to trigger interrupt request at the right CPU HPA address.
Note that the cpu_hpa value comes out of the IRT, which doesn't store the
higher addresss bits.

Signed-off-by: Helge Deller <deller@gmx.de>

hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region

Map Astro into high F-region and add alias for 32-bit OS in low region.

Signed-off-by: Helge Deller <deller@gmx.de>

target/hppa: Improve interrupt logging

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Update IIAOQ, IIASQ for pa2.0

These registers have a different format for pa2.0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Create raise_exception_with_ior

Handle pa2.0 logic for filling in ISR+IOR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Add unwind_breg to CPUHPPAState

Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Clear upper bits in mtctl for pa1.x

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Add pa2.0 cpu local tlb flushes

The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement pa2.0 data prefetch instructions

These are aliased onto the normal integer loads to %g0.
Since we don't emulate caches, prefetch is a nop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

linux-user/hppa: Drop EXCP_DUMP from handled exceptions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

hw/hppa: Translate phys addresses for the cpu

Hack the machine to use pa2.0 physical layout when required,
using the PSW.W=0 absolute to physical mapping.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

include/hw/elf: Remove truncating signed casts

There's nothing about elf that specifically requires signed vs unsigned.
This is very much a target-specific preference.

In the meantime, casting low and high from uint64_t back to Elf_SWord
to uint64_t discards high bits that might have been set by translate_fn.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Return zero for r0 from load_gpr

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Precompute zero into DisasContext

Reduce the number of times we look for the constant 0.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix interruption based on default PSW

The default PSW is set by the operating system with the PDC_PSW
firmware call.  Use that setting to decide if wide mode is to be
enabled for interruptions and EIRR usage.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement PERMH

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement MIXH, MIXW

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement HSHLADD, HSHRADD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement HSHL, HSHR

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement HAVG

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement HSUB

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement HADD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Use tcg_temp_new_i64 not tcg_temp_new

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Adjust vmstate_env for pa2.0 tlb

Split out the tlb to a subsection so that it can be separately
versioned -- the format is only partially following the architecture
and is partially guided by the qemu implementation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove remaining TARGET_REGISTER_BITS redirections

The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove most of the TARGET_REGISTER_BITS redirections

Remove all but those intended to change type to or from i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove TARGET_REGISTER_BITS

Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

hw/hppa: Use uint32_t instead of target_ureg

The size of target_ureg is going to change.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement IDTLBT, IITLBT

Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus.  Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement STDBY

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement SHRPD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement EXTRD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement DEPD, DEPDI

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement LDD, LDCD, LDDA, STD, STDA

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode ADDB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode CMPIB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for cmpb instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for bb instructions

Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for sub instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for add instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for cmpclr instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for unit instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for logical instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove TARGET_HPPA64

Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Drop attempted gdbstub support for hppa64

There is no support for hppa64 in gdb.  Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

linux-user/hppa: Fixes for TARGET_ABI32

Avoid target_ulong and use abi_* types.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_unit_cond

Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_sed_cond

Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_log_cond

Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_sub_cond

Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_cond

Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: sar register allows only 5 bits on 32-bit CPU

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>

target/hppa: Mask inputs in copy_iaoq_entry

Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Use copy_iaoq_entry for link in do_ibranch

We need to make sure the link is masked properly along the
use_nullify_skip path.  The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]

This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass DisasContext to copy_iaoq_entry

Interface change only, no functional effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix hppa64 addressing

In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Adjust hppa_cpu_dump_state for hppa64

Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Handle absolute addresses for pa2.0

With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Update cpu_hppa_get/put_psw for hppa64

With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement hppa_cpu_class_by_name

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement cpu_list

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Make HPPA_BTLB_ENTRIES variable

Depend on hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Introduce TYPE_HPPA64_CPU

Prepare for the qemu binary supporting both pa10 and pa20
at the same time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix extrw and depw with sar for hppa64

These are 32-bit operations regardless of processor.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix bb_sar for hppa64

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix do_add, do_sub for hppa64

Select the proper carry bit for input to the arithmetic
and for output for the condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix trans_ds for hppa64

This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Truncate rotate count in trans_shrpw_sar

When forcing rotate by i32, the shift count must be as well.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix load in do_load_32

The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Fix hppa64 case in machine.c

Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove load_const

Replace with tcg_constant_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove get_temp_tl

Replace with tcg_temp_new_tl without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove get_temp

Replace with tcg_temp_new without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Populate an interval tree with valid tlb entries

Complete the data structure conversion started earlier.  This reduces
the perf overhead of hppa_get_physical_address from ~5% to ~0.25%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Split out hppa_flush_tlb_range

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Always report one page to tlb_set_page

No need to trigger the large_page_mask code unnecessarily.
Drop the now unused HPPATLBEntry.page_size field.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Use IntervalTreeNode in HPPATLBEntry

Replace the va_b and va_b fields with the interval tree node.
The actual interval tree is not yet used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Rename hppa_tlb_entry to HPPATLBEntry

Rename to CamelCase per coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Include PSW_P in tb flags and mmu index

Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes.  This turns out to be the majority
of all tlb flushes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging

target/sparc: Explicitly compute condition codes

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* tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu: (21 commits)
  target/sparc: Check for invalid cond in gen_compare_reg
  target/sparc: Implement UDIV inline
  target/sparc: Implement UDIVX and SDIVX inline
  target/sparc: Discard cpu_cond at the end of each insn
  target/sparc: Record entire jump condition in DisasContext
  target/sparc: Merge gen_op_next_insn into only caller
  target/sparc: Pass displacement to advance_jump_cond
  target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond
  target/sparc: Merge gen_branch2 into advance_pc
  target/sparc: Do flush_cond in advance_jump_cond
  target/sparc: Always copy conditions into a new temporary
  target/sparc: Change DisasCompare.c2 to int
  target/sparc: Remove DisasCompare.is_bool
  target/sparc: Remove CC_OP leftovers
  target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV
  target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB
  target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD
  target/sparc: Remove CC_OP_DIV
  target/sparc: Remove CC_OP_LOGIC
  target/sparc: Split psr and xcc into components
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

Merge tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu into staging

Migration Pull request (20231103)

Hi

In this PULL:
- dirty limit fixes (hyman)
- coverity issues (juan)

Please apply.

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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 03 Nov 2023 20:04:40 HKT
# gpg:                using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full]
# gpg:                 aka "Juan Quintela <quintela@trasno.org>" [full]
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03  4B82 F487 EF18 5872 D723

* tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu:
  migration: Unlock mutex in error case
  docs/migration: Add the dirty limit section
  tests/migration: Introduce dirty-limit into guestperf
  tests/migration: Introduce dirty-ring-size option into guestperf
  tests: Add migration dirty-limit capability test
  system/dirtylimit: Drop the reduplicative check
  system/dirtylimit: Fix a race situation

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging

dump queue

Hi

The "dump" queue, with:
- [PATCH v3 qemu 0/3] Allow dump-guest-memory to output standard kdump format
- [PATCH v2 0/5] dump: Minor fixes & improvements

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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 03 Nov 2023 15:01:21 HKT
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
  dump: Drop redundant check for empty dump
  dump: Improve some dump-guest-memory error messages
  dump: Recognize "fd:" protocols on Windows hosts
  dump: Fix g_array_unref(NULL) in dump-guest-memory
  dump: Rename qmp_dump_guest_memory() parameter to match QAPI schema
  dump: Add command interface for kdump-raw formats
  dump: Allow directly outputting raw kdump format
  dump: Pass DumpState to write_ functions

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

Merge tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20231103

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# gpg: Signature made Fri 03 Nov 2023 14:16:02 HKT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
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# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu:
  linux-user/loongarch64: Add LASX sigcontext save/restore
  linux-user/loongarch64: Add LSX sigcontext save/restore
  linux-user/loongarch64: Use abi_{ulong,uint} types
  linux-user/loongarch64: setup_sigframe() set 'end' context size 0
  linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size
  linux-user/loongarch64: Use traps to track LSX/LASX usage
  target/loongarch: Support 4K page size
  target/loongarch: Implement query-cpu-model-expansion
  target/loongarch: Allow user enable/disable LSX/LASX features
  target/loongarch: Add cpu model 'max'

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

target/sparc: Check for invalid cond in gen_compare_reg

Consolidate the test here; drop the "inverted logic".
Fix MOVr and FMOVR, which were missing the invalid test.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement UDIV inline

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement UDIVX and SDIVX inline

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Discard cpu_cond at the end of each insn

If the insn raises no exceptions, there will be no path in which
cpu_cond is used, and so the computation may be optimized away.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Record entire jump condition in DisasContext

Use the original condition instead of consuming cpu_cond,
which will now only be live along exception paths.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Merge gen_op_next_insn into only caller

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Pass displacement to advance_jump_cond

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond

Handle these via TCG_COND_{ALWAYS,NEVER}.
Allow dc->npc to be variable, using gen_mov_pc_npc.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Merge gen_branch2 into advance_pc

The function had only one caller.  Canonicalize the cpu_cond
test to TCG_COND_NE, the "natural" sense of its value.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Do flush_cond in advance_jump_cond

Do this here instead of in each caller.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Always copy conditions into a new temporary

This will allow the condition to live across changes to
the global cc variables.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Change DisasCompare.c2 to int

We don't require c2 to be variable, so emphasize that.
We don't currently require c2 to be non-zero, but that will change.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc: Remove DisasCompare.is_bool

Since we're going to feed cpu_cond to another comparison, we don't
reqire a boolean value -- anything non-zero is sufficient.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>