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Bill Wendling [Mon, 9 Apr 2012 23:16:51 +0000 (23:16 +0000)]
Revert the 'EnableInitializing' flag. There is debate on whether we should run that pass by default in LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154356
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Bill Wendling [Mon, 9 Apr 2012 22:18:01 +0000 (22:18 +0000)]
Apply the scope restrictions after parsing the command line options. There may be some which are used in that function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154348
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Akira Hatanaka [Mon, 9 Apr 2012 20:32:12 +0000 (20:32 +0000)]
Have TargetLowering::getPICJumpTableRelocBase return a node that points to the
GOT if jump table uses 64-bit gp-relative relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154341
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Chad Rosier [Mon, 9 Apr 2012 20:32:02 +0000 (20:32 +0000)]
When performing a truncating store, it's possible to rearrange the data
in-register, such that we can use a single vector store rather then a
series of scalar stores.
For func_4_8 the generated code
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vmov.u16 r0, d16[3]
strb r0, [r2, #3]
vmov.u16 r0, d16[2]
strb r0, [r2, #2]
vmov.u16 r0, d16[1]
strb r0, [r2, #1]
vmov.u16 r0, d16[0]
strb r0, [r2]
bx lr
becomes
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vuzp.8 d16, d17
vst1.32 {d16[0]}, [r2, :32]
bx lr
I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll,
but I couldn't think of a way to judiciously apply this combine.
This
ldrh r0, [r0, #4]
strh r0, [r1]
becomes
vldr d16, [r0]
vmov.u16 r0, d16[2]
vmov.32 d16[0], r0
vuzp.16 d16, d17
vst1.32 {d16[0]}, [r1, :32]
PR11158
rdar://
10703339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154340
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Lang Hames [Mon, 9 Apr 2012 20:17:30 +0000 (20:17 +0000)]
Patch r153892 for PR11861 apparently broke an external project (see PR12493).
This patch restores TwoAddressInstructionPass's pre-r153892 behaviour when
rescheduling instructions in TryInstructionTransform. Hopefully this will fix
PR12493. To refix PR11861, lowering of INSERT_SUBREGS is deferred until after
the copy that unties the operands is emitted (this seems to be a more
appropriate fix for that issue anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154338
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Chad Rosier [Mon, 9 Apr 2012 19:38:15 +0000 (19:38 +0000)]
Update comments and remove unnecessary isVolatile() check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154336
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Eric Christopher [Mon, 9 Apr 2012 17:54:34 +0000 (17:54 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154329
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David Blaikie [Mon, 9 Apr 2012 16:29:35 +0000 (16:29 +0000)]
Fix accidentally constant conditions found by uncommitted improvements to -Wconstant-conversion.
A couple of cases where we were accidentally creating constant conditions by
something like "x == a || b" instead of "x == a || x == b". In one case a
conditional & then unreachable was used - I transformed this into a direct
assert instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154324
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Rafael Espindola [Mon, 9 Apr 2012 16:06:03 +0000 (16:06 +0000)]
Pattern match a setcc of boolean value with 0 as a truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154322
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Preston Gurd [Mon, 9 Apr 2012 15:32:22 +0000 (15:32 +0000)]
This patch adds X86 instruction itineraries, which were missed by the
original patch to add itineraries, to X86InstrArithmetc.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154320
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Duncan Sands [Mon, 9 Apr 2012 14:08:00 +0000 (14:08 +0000)]
Clarify that fpaccuracy metadata is giving the compiler permission to use a
less accurate method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154319
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Nadav Rotem [Mon, 9 Apr 2012 08:33:21 +0000 (08:33 +0000)]
Lower some x86 shuffle sequences to the vblend family of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154313
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Bill Wendling [Mon, 9 Apr 2012 08:32:21 +0000 (08:32 +0000)]
s/lto_codegen_whole_program_optimization/lto_codegen_set_whole_program_optimization/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154312
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Nadav Rotem [Mon, 9 Apr 2012 07:45:58 +0000 (07:45 +0000)]
Fix a bug in the lowering of broadcasts: ConstantPools need to use the target pointer type.
Move NormalizeVectorShuffle and LowerVectorBroadcast into X86TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154310
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Craig Topper [Mon, 9 Apr 2012 07:19:09 +0000 (07:19 +0000)]
Remove unnecessary type check when combining and/or/xor of swizzles. Move some checks to allow better early out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154309
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Craig Topper [Mon, 9 Apr 2012 05:59:53 +0000 (05:59 +0000)]
Remove unnecessary 'else' on an 'if' that always returns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154308
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Craig Topper [Mon, 9 Apr 2012 05:55:33 +0000 (05:55 +0000)]
Optimize code slightly. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154307
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Bill Wendling [Mon, 9 Apr 2012 05:26:48 +0000 (05:26 +0000)]
Add a hook to turn on the internalize pass through the LTO interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154306
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Craig Topper [Mon, 9 Apr 2012 05:16:56 +0000 (05:16 +0000)]
Replace some explicit checks with asserts for conditions that should never happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154305
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Chandler Carruth [Mon, 9 Apr 2012 02:13:06 +0000 (02:13 +0000)]
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304
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Chandler Carruth [Mon, 9 Apr 2012 01:43:17 +0000 (01:43 +0000)]
Fold 15 tiny test cases into a single file that implements the
comprehensive testing of TLS codegen for x86. Convert all of the ones
that were still using grep to use FileCheck. Remove some redundancies
between them.
Perhaps most interestingly expand the test cases so that they actually
fully list the instruction snippet being tested. TLS operations are
*very* narrowly defined, and so these seem reasonably stable. More
importantly, the existing test cases already were crazy fine grained,
expecting specific registers to be allocated. This just clarifies that
no *other* instructions are expected, and fills in some crucial gaps
that weren't being tested at all.
This will make any subsequent changes to TLS much more clear during
review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154303
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Craig Topper [Sun, 8 Apr 2012 23:15:04 +0000 (23:15 +0000)]
Optimize code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154299
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Benjamin Kramer [Sun, 8 Apr 2012 19:04:45 +0000 (19:04 +0000)]
Silence sign-compare warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154297
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Duncan Sands [Sun, 8 Apr 2012 18:08:12 +0000 (18:08 +0000)]
Only have codegen turn fdiv by a constant into fmul by the reciprocal
when -ffast-math, i.e. don't just always do it if the reciprocal can
be formed exactly. There is already an IR level transform that does
that, and it does it more carefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154296
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Craig Topper [Sun, 8 Apr 2012 17:53:33 +0000 (17:53 +0000)]
Simplify code that tries to do vector extracts for shuffles when the mask width and the input vector widths don't match. No need to check the min and max are in range before calculating the start index. The range check after having the start index is sufficient. Also no need to check for an extract from the beginning differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154295
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Chandler Carruth [Sun, 8 Apr 2012 17:51:45 +0000 (17:51 +0000)]
Teach LLVM about a PIE option which, when enabled on top of PIC, makes
optimizations which are valid for position independent code being linked
into a single executable, but not for such code being linked into
a shared library.
I discussed the design of this with Eric Christopher, and the decision
was to support an optional bit rather than a completely separate
relocation model. Fundamentally, this is still PIC relocation, its just
that certain optimizations are only valid under a PIC relocation model
when the resulting code won't be in a shared library. The simplest path
to here is to expose a single bit option in the TargetOptions. If folks
have different/better designs, I'm all ears. =]
I've included the first optimization based upon this: changing TLS
models to the *Exec models when PIE is enabled. This is the LLVM
component of PR12380 and is all of the hard work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154294
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Chandler Carruth [Sun, 8 Apr 2012 17:20:55 +0000 (17:20 +0000)]
Move the TLSModel information into the TargetMachine rather than hiding
in TargetLowering. There was already a FIXME about this location being
odd. The interface is simplified as a consequence. This will also make
it easier to change TLS models when compiling with PIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154292
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Benjamin Kramer [Sun, 8 Apr 2012 14:53:14 +0000 (14:53 +0000)]
EngineBuilder::create is expected to take ownership of the TargetMachine passed to it. Delete it on error or when we create an interpreter that doesn't need it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154288
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Chandler Carruth [Sun, 8 Apr 2012 14:37:02 +0000 (14:37 +0000)]
Remove an over zealous assert. The assert was trying to catch places
where a chain outside of the loop block-set ended up in the worklist for
scheduling as part of the contiguous loop. However, asserting the first
block in the chain is in the loop-set isn't a valid check -- we may be
forced to drag a chain into the worklist due to one block in the chain
being part of the loop even though the first block is *not* in the loop.
This occurs when we have been forced to form a chain early due to
un-analyzable branches.
No test case here as I have no idea how to even begin reducing one, and
it will be hopelessly fragile. We have to somehow end up with a loop
header of an inner loop which is a successor of a basic block with an
unanalyzable pair of branch instructions. Ow. Self-host triggers it so
it is unlikely it will regress.
This at least gets block placement back to passing selfhost and the test
suite. There are still a lot of slowdown that I don't like coming out of
block placement, although there are now also a lot of speedups. =[ I'm
seeing swings in both directions up to 10%. I'm going to try to find
time to dig into this and see if we can turn this on for 3.1 as it does
a really good job of cleaning up after some loops that degraded with the
inliner changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154287
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Chandler Carruth [Sun, 8 Apr 2012 14:37:01 +0000 (14:37 +0000)]
Add a debug-only 'dump' method to the BlockChain structure to ease
debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154286
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Chandler Carruth [Sun, 8 Apr 2012 14:36:56 +0000 (14:36 +0000)]
Teach InstCombine to nuke a common alloca pattern -- an alloca which has
GEPs, bit casts, and stores reaching it but no other instructions. These
often show up during the iterative processing of the inliner, SROA, and
DCE. Once we hit this point, we can completely remove the alloca. These
were actually showing up in the final, fully optimized code in a bunch
of inliner tests I've been working on, and notably they show up after
LLVM finishes optimizing away all function calls involved in
hash_combine(a, b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154285
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Nadav Rotem [Sun, 8 Apr 2012 12:54:54 +0000 (12:54 +0000)]
AVX2: Build splat vectors by broadcasting a scalar from the constant pool.
Previously we used three instructions to broadcast an immediate value into a
vector register.
On Sandybridge we continue to load the broadcasted value from the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154284
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Bill Wendling [Sun, 8 Apr 2012 11:53:54 +0000 (11:53 +0000)]
Remove old 'grep' lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154283
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Bill Wendling [Sun, 8 Apr 2012 11:52:52 +0000 (11:52 +0000)]
Formatting changes. Don't put spaces in front of some code, which only makes it look 'off'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154282
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Bill Wendling [Sun, 8 Apr 2012 11:00:38 +0000 (11:00 +0000)]
FileCheckize these testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154281
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Bill Wendling [Sun, 8 Apr 2012 10:20:49 +0000 (10:20 +0000)]
Remove the 'Parent' pointer from the MDNodeOperand class.
An MDNode has a list of MDNodeOperands allocated directly after it as part of
its allocation. Therefore, the Parent of the MDNodeOperands can be found by
walking back through the operands to the beginning of that list. Mark the first
operand's value pointer as being the 'first' operand so that we know where the
beginning of said list is.
This saves a *lot* of space during LTO with -O0 -g flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154280
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Bill Wendling [Sun, 8 Apr 2012 10:16:43 +0000 (10:16 +0000)]
Allow subclasses of the ValueHandleBase to store information as part of the
value pointer by making the value pointer into a pointer-int pair with 2 bits
available for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154279
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Craig Topper [Sat, 7 Apr 2012 22:32:29 +0000 (22:32 +0000)]
Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154272
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Craig Topper [Sat, 7 Apr 2012 21:57:43 +0000 (21:57 +0000)]
Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154268
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Craig Topper [Sat, 7 Apr 2012 21:23:41 +0000 (21:23 +0000)]
Remove 'else' after 'if' that ends in return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154267
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Nadav Rotem [Sat, 7 Apr 2012 21:19:08 +0000 (21:19 +0000)]
1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a new
shuffle node because it could introduce new shuffle nodes that were not
supported efficiently by the target.
2. Add a more restrictive shuffle-of-shuffle optimization for cases where the
second shuffle reverses the transformation of the first shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154266
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Duncan Sands [Sat, 7 Apr 2012 20:04:00 +0000 (20:04 +0000)]
Convert floating point division by a constant into multiplication by the
reciprocal if converting to the reciprocal is exact. Do it even if inexact
if -ffast-math. This substantially speeds up ac.f90 from the polyhedron
benchmarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154265
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Chandler Carruth [Sat, 7 Apr 2012 20:01:31 +0000 (20:01 +0000)]
Perform partial SROA on the helper hashing structure. I really wish the
optimizers could do this for us, but expecting partial SROA of classes
with template methods through cloning is probably expecting too much
heroics. With this change, the begin/end pointer pairs which indicate
the status of each loop iteration are actually passed directly into each
layer of the combine_data calls, and the inliner has a chance to see
when most of the combine_data function could be deleted by inlining.
Similarly for 'length'.
We have to be careful to limit the places where in/out reference
parameters are used as those will also defeat the inliner / optimizers
from properly propagating constants.
With this change, LLVM is able to fully inline and unroll the hash
computation of small sets of values, such as two or three pointers.
These now decompose into essentially straight-line code with no loops or
function calls.
There is still one code quality problem to be solved with the hashing --
LLVM is failing to nuke the alloca. It removes all loads from the
alloca, leaving only lifetime intrinsics and dead(!!) stores to the
alloca. =/ Very unfortunate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154264
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Chandler Carruth [Sat, 7 Apr 2012 19:22:18 +0000 (19:22 +0000)]
Fix ValueTracking to conclude that debug intrinsics are safe to
speculate. Without this, loop rotate (among many other places) would
suddenly stop working in the presence of debug info. I found this
looking at loop rotate, and have augmented its tests with a reduction
out of a very hot loop in yacr2 where failing to do this rotation costs
sometimes more than 10% in runtime performance, perturbing numerous
downstream optimizations.
This should have no impact on performance without debug info, but the
change in performance when debug info is enabled can be extreme. As
a consequence (and this how I got to this yak) any profiling of
performance problems should be treated with deep suspicion -- they may
have been wildly innacurate of debug info was enabled for profiling. =/
Just a heads up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154263
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Benjamin Kramer [Sat, 7 Apr 2012 17:19:26 +0000 (17:19 +0000)]
SCEV: When expanding a GEP the final addition to the base pointer has NUW but not NSW.
Found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154262
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Bob Wilson [Sat, 7 Apr 2012 16:51:59 +0000 (16:51 +0000)]
Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/
11203543>
The tLDRr instruction with the last register operand set to the zero register
prints in assembly as if no register was specified, and the assembler encodes
it as a tLDRi instruction with a zero immediate. With the integrated assembler,
that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
is broken. Emit the instruction as tLDRi with a zero immediate. I don't
know if there's a good way to write a testcase for this. Suggestions welcome.
Opportunities for follow-up work:
1) The asm printer should complain if a non-optional register operand is set
to the zero register, instead of silently dropping it.
2) The integrated assembler should complain in the same situation, instead of
silently emitting the operand as "r0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154261
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Hongbin Zheng [Sat, 7 Apr 2012 03:56:23 +0000 (03:56 +0000)]
Refactor: Use positive field names in VectorizeConfig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154249
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NAKAMURA Takumi [Sat, 7 Apr 2012 02:24:20 +0000 (02:24 +0000)]
Target/X86/MCTargetDesc/X86MCAsmInfo.cpp: Enable DwarfCFI (aka DW2) on Cygming.
Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154247
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Sean Hunt [Sat, 7 Apr 2012 01:33:14 +0000 (01:33 +0000)]
Make the test for r154235 more platform-independent with a shorter
string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154243
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Sean Hunt [Sat, 7 Apr 2012 00:37:53 +0000 (00:37 +0000)]
Output UTF-8-encoded characters as identifier characters into assembly
by default.
This is a behaviour configurable in the MCAsmInfo. I've decided to turn
it on by default in (possibly optimistic) hopes that most assemblers are
reasonably sane. If this proves a problem, switching to default seems
reasonable.
I'm not sure if this is the opportune place to test, but it seemed good
to make sure it was tested somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154235
91177308-0d34-0410-b5e6-
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Jim Grosbach [Fri, 6 Apr 2012 23:43:50 +0000 (23:43 +0000)]
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Fri, 6 Apr 2012 21:21:59 +0000 (21:21 +0000)]
ARMPat is equivalent to Requires<[IsARM]>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154210
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Fri, 6 Apr 2012 21:17:42 +0000 (21:17 +0000)]
Eliminate iOS-specific tail call instructions.
After register masks were introdruced to represent the call clobbers, it
is no longer necessary to have duplicate instruction for iOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154209
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Fri, 6 Apr 2012 20:23:36 +0000 (20:23 +0000)]
Add lines in global-address.ll to test N32 and N64 code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154202
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 6 Apr 2012 20:10:52 +0000 (20:10 +0000)]
There is no portable std::abs overload for int64_t, use the llvm::abs64
which exists for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154199
91177308-0d34-0410-b5e6-
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Sean Callanan [Fri, 6 Apr 2012 18:21:09 +0000 (18:21 +0000)]
Fixed two leaks in the MC disassembler. The MC
disassembler requires a MCSubtargetInfo and a
MCInstrInfo to exist in order to initialize the
instruction printer and disassembler; however,
although the printer and disassembler keep
references to these objects they do not own them.
Previously, the MCSubtargetInfo and MCInstrInfo
objects were just leaked.
I have extended LLVMDisasmContext to own these
objects and delete them when it is destroyed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154192
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Fri, 6 Apr 2012 17:45:04 +0000 (17:45 +0000)]
Allow negative immediates in ARM and Thumb2 compares.
ARM and Thumb2 mode can use cmn instructions to compare against negative
immediates. Thumb1 mode can't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154183
91177308-0d34-0410-b5e6-
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David Chisnall [Fri, 6 Apr 2012 17:27:41 +0000 (17:27 +0000)]
Reintroduce InlineCostAnalyzer::getInlineCost() variant with explicit callee
parameter until we have a more sensible API for doing the same thing.
Reviewed by Chandler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154180
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 6 Apr 2012 17:21:31 +0000 (17:21 +0000)]
Sink the collection of return instructions until after *all*
simplification has been performed. This is a bit less efficient
(requires another ilist walk of the basic blocks) but shouldn't matter
in practice. More importantly, it's just too much work to keep track of
all the various ways the return instructions can be mutated while
simplifying them. This fixes yet another crasher, reported by Daniel
Dunbar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154179
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 6 Apr 2012 17:21:28 +0000 (17:21 +0000)]
Tweak this test to ensure the inliner did indeed fire. Thanks to Richard
Smith for pointing this out in review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154178
91177308-0d34-0410-b5e6-
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Duncan Sands [Fri, 6 Apr 2012 15:31:09 +0000 (15:31 +0000)]
Make GVN's propagateEquality non-recursive. No intended functionality change.
The modifications are a lot more trivial than they appear to be in the diff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154174
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 6 Apr 2012 14:38:25 +0000 (14:38 +0000)]
Test case for PR12413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154172
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Fri, 6 Apr 2012 13:33:52 +0000 (13:33 +0000)]
Fix narrowing conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154171
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Fri, 6 Apr 2012 10:43:44 +0000 (10:43 +0000)]
DenseMap: Perform the pod-like object optimization when the value type is POD-like, not the DenseMapInfo for it.
Purge now unused template arguments. This has been broken since r91421. Patch by Lubos Lunak!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154170
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 6 Apr 2012 07:45:23 +0000 (07:45 +0000)]
Allow 256-bit shuffles to be split if a 128-bit lane contains elements from a single source. This is a rewrite of the 256-bit shuffle splitting code based on similar code from legalize types. Fixes PR12413.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154166
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 6 Apr 2012 07:09:59 +0000 (07:09 +0000)]
Add the tests that were supposed to go with r153935 that I forgot svn add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 6 Apr 2012 01:19:38 +0000 (01:19 +0000)]
Actually finish this sentence in the comment the way I intended. Thanks
Matt for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154158
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 6 Apr 2012 01:11:52 +0000 (01:11 +0000)]
Sink the return instruction collection until after we're done deleting
dead code, including dead return instructions in some cases. Otherwise,
we end up having a bogus poniter to a return instruction that blows up
much further down the road.
It turns out that this pattern is both simpler to code, easier to update
in the face of enhancements to the inliner cleanup, and likely cheaper
given that it won't add dead instructions to the list.
Thanks to John Regehr's numerous test cases for teasing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154157
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Fri, 6 Apr 2012 00:04:58 +0000 (00:04 +0000)]
Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144
91177308-0d34-0410-b5e6-
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Jim Grosbach [Thu, 5 Apr 2012 23:51:24 +0000 (23:51 +0000)]
ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.
The load/store optimizer splits LDRD/STRD into two instructions when the
register pairing doesn't work out. For negative offsets in Thumb2, it uses
t2STRi8 to do that. That's fine, except for the case when the offset is in
the range [-4,-1]. In that case, we'll also form a second t2STRi8 with
the original offset plus 4, resulting in a t2STRi8 with a non-negative
offset, which ends up as if it were an STRT, which is completely bogus.
Similarly for loads.
No testcase, unfortunately, as any I've been able to construct is both large
and extremely fragile.
rdar://
11193937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154141
91177308-0d34-0410-b5e6-
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Kaelyn Uhrain [Thu, 5 Apr 2012 23:06:17 +0000 (23:06 +0000)]
Fix the build breakage introduced by r154131.
The empty 1-argument operator delete is for the benefit of the
destructor. A couple of spot checks of running yaml-bench under
valgrind against a few of the files under test/YAMLParser did
not reveal any leaks introduced by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154137
91177308-0d34-0410-b5e6-
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Kaelyn Uhrain [Thu, 5 Apr 2012 22:11:12 +0000 (22:11 +0000)]
Really fix -Wnon-virtual-dtor warnings; gcc needs the dtors to be
explicitly marked as virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154131
91177308-0d34-0410-b5e6-
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Bill Wendling [Thu, 5 Apr 2012 21:26:44 +0000 (21:26 +0000)]
The internalize pass can be dangerous for LTO.
Consider the following program:
$ cat main.c
void foo(void) { }
int main(int argc, char *argv[]) {
foo();
return 0;
}
$ cat bundle.c
extern void foo(void);
void bar(void) {
foo();
}
$ clang -o main main.c
$ clang -o bundle.so bundle.c -bundle -bundle_loader ./main
$ nm -m bundle.so
0000000000000f40 (__TEXT,__text) external _bar
(undefined) external _foo (from executable)
(undefined) external dyld_stub_binder (from libSystem)
$ clang -o main main.c -O4
$ clang -o bundle.so bundle.c -bundle -bundle_loader ./main
Undefined symbols for architecture x86_64:
"_foo", referenced from:
_bar in bundle-elQN6d.o
ld: symbol(s) not found for architecture x86_64
clang: error: linker command failed with exit code 1 (use -v to see invocation)
The linker was told that the 'foo' in 'main' was 'internal' and had no uses, so
it was dead stripped.
Another situation is something like:
define void @foo() {
ret void
}
define void @bar() {
call asm volatile "call _foo" ...
ret void
}
The only use of 'foo' is inside of an inline ASM call. Since we don't look
inside those for uses of functions, we don't specify this as a "use."
Get around this by not invoking the 'internalize' pass by default. This is an
admitted hack for LTO correctness.
<rdar://problem/
11185386>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154124
91177308-0d34-0410-b5e6-
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Jim Grosbach [Thu, 5 Apr 2012 20:57:13 +0000 (20:57 +0000)]
ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://
11192734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Thu, 5 Apr 2012 20:44:35 +0000 (20:44 +0000)]
Reapply test case in 154038, this time with triple to prevent the backend
from emitting gp_rel relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154122
91177308-0d34-0410-b5e6-
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Eric Christopher [Thu, 5 Apr 2012 20:39:05 +0000 (20:39 +0000)]
Patch to set is_stmt a little better for prologue lines in a function.
This enables debuggers to see what are interesting lines for a
breakpoint rather than any line that starts a function.
rdar://
9852092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154120
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Thu, 5 Apr 2012 20:30:20 +0000 (20:30 +0000)]
Don't break the IV update in TLI::SimplifySetCC().
LSR always tries to make the ICmp in the loop latch use the incremented
induction variable. This allows the induction variable to be kept in a
single register.
When the induction variable limit is equal to the stride,
SimplifySetCC() would break LSR's hard work by transforming:
(icmp (add iv, stride), stride) --> (cmp iv, 0)
This forced us to use lea for the IC update, preventing the simpler
incl+cmp.
<rdar://problem/
7643606>
<rdar://problem/
11184260>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 5 Apr 2012 20:27:21 +0000 (20:27 +0000)]
Fix accidentally inverted logic from r152803, and make the
testcase slightly less trivial. This fixes rdar://
11171718.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154118
91177308-0d34-0410-b5e6-
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Sylvestre Ledru [Thu, 5 Apr 2012 19:34:15 +0000 (19:34 +0000)]
Fix a problem in the target detection for Debian GNU/HURD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154117
91177308-0d34-0410-b5e6-
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Sylvestre Ledru [Thu, 5 Apr 2012 18:53:09 +0000 (18:53 +0000)]
Fix a problem in the target detection for Debian GNU/kFreeBSD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154114
91177308-0d34-0410-b5e6-
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Owen Anderson [Thu, 5 Apr 2012 18:50:32 +0000 (18:50 +0000)]
Treat f16 the same as f80/f128 for the purposes of generating constants during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154113
91177308-0d34-0410-b5e6-
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Silviu Baranga [Thu, 5 Apr 2012 16:19:29 +0000 (16:19 +0000)]
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101
91177308-0d34-0410-b5e6-
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Silviu Baranga [Thu, 5 Apr 2012 16:13:15 +0000 (16:13 +0000)]
Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100
91177308-0d34-0410-b5e6-
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Hongbin Zheng [Thu, 5 Apr 2012 16:07:49 +0000 (16:07 +0000)]
BBVectorize: Add the const modifier to the VectorizeConfig because we won't
modify it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154098
91177308-0d34-0410-b5e6-
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Hongbin Zheng [Thu, 5 Apr 2012 15:46:55 +0000 (15:46 +0000)]
Introduce the VectorizeConfig class, with which we can control the behavior
of the BBVectorizePass without using command line option. As pointed out
by Hal, we can ask the TargetLoweringInfo for the architecture specific
VectorizeConfig to perform vectorizing with architecture specific
information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154096
91177308-0d34-0410-b5e6-
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James Molloy [Thu, 5 Apr 2012 10:01:12 +0000 (10:01 +0000)]
An oversight when applying the patches for r150956 and r150957 to a vanilla tree meant I forgot to svn add these testcases.
Noticed while investigating PR12274!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154090
91177308-0d34-0410-b5e6-
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Hongbin Zheng [Thu, 5 Apr 2012 08:05:16 +0000 (08:05 +0000)]
Add the function "vectorizeBasicBlock" which allow users vectorize a
BasicBlock in other passes, e.g. we can call vectorizeBasicBlock in the
loop unroll pass right after the loop is unrolled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154089
91177308-0d34-0410-b5e6-
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Jim Grosbach [Thu, 5 Apr 2012 07:23:53 +0000 (07:23 +0000)]
ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://
11189467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087
91177308-0d34-0410-b5e6-
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Argyrios Kyrtzidis [Thu, 5 Apr 2012 04:23:56 +0000 (04:23 +0000)]
In MemoryBuffer::getOpenFile() make sure that the buffer is null-terminated if
the caller requested a null-terminated one.
When mapping the file there could be a racing issue that resulted in the file being larger
than the FileSize passed by the caller. We already have an assertion
for this in MemoryBuffer::init() but have a runtime guarantee that
the buffer will be null-terminated, so do a copy that adds a null-terminator.
Protects against crash of rdar://
11161822.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154082
91177308-0d34-0410-b5e6-
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Jim Grosbach [Thu, 5 Apr 2012 03:17:53 +0000 (03:17 +0000)]
ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://
11153753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Thu, 5 Apr 2012 03:10:56 +0000 (03:10 +0000)]
Pass the right sign to TLI->isLegalICmpImmediate.
LSR can fold three addressing modes into its ICmpZero node:
ICmpZero BaseReg + Offset => ICmp BaseReg, -Offset
ICmpZero -1*ScaleReg + Offset => ICmp ScaleReg, Offset
ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg
The first two cases are only used if TLI->isLegalICmpImmediate() likes
the offset.
Make sure the right Offset sign is passed to this method in the second
case. The ARM version is not symmetric.
<rdar://problem/
11184260>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154079
91177308-0d34-0410-b5e6-
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Bob Wilson [Thu, 5 Apr 2012 00:35:55 +0000 (00:35 +0000)]
Do not include multiple -arch options in CPPFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154070
91177308-0d34-0410-b5e6-
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Michael J. Spencer [Wed, 4 Apr 2012 22:34:55 +0000 (22:34 +0000)]
Fix -Wnon-virtual-dtor warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154063
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Wed, 4 Apr 2012 22:16:36 +0000 (22:16 +0000)]
Reapply 154038 without the failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062
91177308-0d34-0410-b5e6-
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Owen Anderson [Wed, 4 Apr 2012 21:18:58 +0000 (21:18 +0000)]
Revert r154038. It was causing make check failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154054
91177308-0d34-0410-b5e6-
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Pete Cooper [Wed, 4 Apr 2012 21:03:25 +0000 (21:03 +0000)]
REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub register indices on the source registers. No simple test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154051
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Wed, 4 Apr 2012 20:33:56 +0000 (20:33 +0000)]
Fix a C++11 UDL conflict.
Still not fixed in the standard ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154044
91177308-0d34-0410-b5e6-
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Pete Cooper [Wed, 4 Apr 2012 19:36:31 +0000 (19:36 +0000)]
f16 FREM can now be legalized by promoting to f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154039
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Wed, 4 Apr 2012 19:02:38 +0000 (19:02 +0000)]
Fix LowerGlobalAddress to produce instructions with the correct relocation
types for N32 ABI. Add new test case and update existing ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154038
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Wed, 4 Apr 2012 18:31:32 +0000 (18:31 +0000)]
Fix LowerJumpTable to produce instructions with the correct relocation
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154036
91177308-0d34-0410-b5e6-
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