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Craig Topper [Fri, 21 Jun 2019 18:49:42 +0000 (18:49 +0000)]
[X86] Add avx512bw command lines to avx512-select.ll
Prep for fixing PR42355 and ensuring we have coverage of
ISD::SELECT for v64i8/v32i16 on KNL and SKX configs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364092
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Craig Topper [Fri, 21 Jun 2019 18:49:21 +0000 (18:49 +0000)]
[X86] Add a debug print of the node in the default case for unhandled opcodes in ReplaceNodeResults.
This should be unreachable, but bugs can make it reachable. This
adds a debug print so we can see the bad node in the output when
the llvm_unreachable triggers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364091
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Simon Pilgrim [Fri, 21 Jun 2019 18:35:04 +0000 (18:35 +0000)]
[X86][AVX] Combine INSERT_SUBVECTOR(SRC0, EXTRACT_SUBVECTOR(SRC1)) as shuffle
Subvector shuffling often ends up as insert/extract subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364090
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Amara Emerson [Fri, 21 Jun 2019 18:10:41 +0000 (18:10 +0000)]
[AArch64][GlobalISel] Implement selection support for the new G_JUMP_TABLE and G_BRJT ops.
With this we can now fully code generate jump tables, which is important for code size.
Differential Revision: https://reviews.llvm.org/D63223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364086
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Amara Emerson [Fri, 21 Jun 2019 18:10:38 +0000 (18:10 +0000)]
[GlobalISel][IRTranslator] Change switch table translation to generate jump tables and range checks.
This change makes use of the newly refactored SwitchLoweringUtils code from
SelectionDAG to in order to generate jump tables and range checks where appropriate.
Much of this code is ported from SDAG with some modifications. We generate
G_JUMP_TABLE and G_BRJT instructions when JT opportunities are found. This means
that targets which previously relied on the naive one MBB per case stmt
translation will now start falling back until they add support for the new opcodes.
For range checks, we don't generate any previously unused operations. This
just recognizes contiguous ranges of case values and generates a single block per
range. Single case value blocks are just a special case of ranges so we get that
support almost for free.
There are still some optimizations missing that I haven't ported over, and
bit-tests are also unimplemented. This patch series is already complex enough.
Actual arm64 support for selection of jump tables is coming in a later patch.
Differential Revision: https://reviews.llvm.org/D63169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364085
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Simon Pilgrim [Fri, 21 Jun 2019 17:57:01 +0000 (17:57 +0000)]
[SLP] Look-ahead operand reordering heuristic.
This patch introduces a new heuristic for guiding operand reordering. The new "look-ahead" heuristic can look beyond the immediate predecessors. This helps break ties when the immediate predecessors have identical opcodes (see lit test for an example).
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D60897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364084
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David Bolvansky [Fri, 21 Jun 2019 17:51:18 +0000 (17:51 +0000)]
[NFC] Update shl-sub tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364083
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Sanjay Patel [Fri, 21 Jun 2019 17:44:09 +0000 (17:44 +0000)]
[InstCombine] add tests for ctpop folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364082
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Craig Topper [Fri, 21 Jun 2019 17:24:21 +0000 (17:24 +0000)]
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
We already use vmovq for v2i64/v2f64 vzmovl. But we were using a
blendpd+xorpd for v4i64/v4f64/v8i64/v8f64 under opt speed. Or
movsd+xorpd under optsize.
I think the blend with 0 or movss/d is only needed for
vXi32 where we don't have an instruction that can move 32
bits from one xmm to another while zeroing upper bits.
movq is no worse than blendpd on any known CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364079
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Simon Pilgrim [Fri, 21 Jun 2019 16:44:51 +0000 (16:44 +0000)]
[DAGCombine] narrowExtractedVectorBinOp - pull out repeated getOpcode(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364076
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Amara Emerson [Fri, 21 Jun 2019 16:43:50 +0000 (16:43 +0000)]
[AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal.
We sometimes get poor code size because constants of types < 32b are legalized
as 32 bit G_CONSTANTs with a truncate to fit. This works but means that the
localizer can no longer sink them (although it's possible to extend it to do so).
On AArch64 however s8 and s16 constants can be selected in the same way as s32
constants, with a mov pseudo into a W register. If we make s8 and s16 constants
legal then we can avoid unnecessary truncates, they can be CSE'd, and the
localizer can sink them as normal.
There is a caveat: if the user of a smaller constant has to widen the sources,
we end up with an anyext of the smaller typed G_CONSTANT. This can cause
regressions because of the additional extend and missed pattern matching. To
remedy this, there's a new artifact combiner to generate the wider G_CONSTANT
if it's legal for the target.
Differential Revision: https://reviews.llvm.org/D63587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364075
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Stanislav Mekhanoshin [Fri, 21 Jun 2019 16:30:14 +0000 (16:30 +0000)]
[AMDGPU] hazard recognizer for fp atomic to s_denorm_mode
This requires 3 wait states unless there is a wait or VALU in
between.
Differential Revision: https://reviews.llvm.org/D63619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364074
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David Bolvansky [Fri, 21 Jun 2019 16:25:32 +0000 (16:25 +0000)]
[InstCombine] (1 << (C - x)) -> ((1 << C) >> x) if C is bitwidth - 1
Summary:
```
%a = sub i32 31, %x
%r = shl i32 1, %a
=>
%d = shl i32 1, 31
%r = lshr i32 %d, %x
Done: 1
Optimization is correct!
```
https://rise4fun.com/Alive/btZm
Reviewers: spatel, lebedev.ri, nikic
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364073
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Simon Pilgrim [Fri, 21 Jun 2019 16:23:28 +0000 (16:23 +0000)]
[X86] isBinOp - move commutative ops to isCommutativeBinOp. NFCI.
TargetLoweringBase::isBinOp checks isCommutativeBinOp as a fallback, so don't duplicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364072
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David Bolvansky [Fri, 21 Jun 2019 16:14:13 +0000 (16:14 +0000)]
[NFC] Added more tests for D63652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364069
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Simon Pilgrim [Fri, 21 Jun 2019 16:11:18 +0000 (16:11 +0000)]
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364068
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David Bolvansky [Fri, 21 Jun 2019 15:26:22 +0000 (15:26 +0000)]
[InstCombine] cttz(abs(x)) -> cttz(x)
Summary: Signedness does not change number of trailing zeros.
Reviewers: spatel, lebedev.ri, nikic
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D63546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364064
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Sanjay Patel [Fri, 21 Jun 2019 15:17:24 +0000 (15:17 +0000)]
[GVNSink] prevent crashing on mismatched instructions (PR42346)
Patch based on suggestion by James Molloy (@jmolloy) in:
https://bugs.llvm.org/show_bug.cgi?id=42346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364062
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David Bolvansky [Fri, 21 Jun 2019 15:00:31 +0000 (15:00 +0000)]
[NFC] Added tests for (1 << (C - x)) -> ((1 << C) >> x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364060
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Simon Pilgrim [Fri, 21 Jun 2019 14:46:21 +0000 (14:46 +0000)]
[DAGCombine] narrowInsertExtractVectorBinOp - reuse "extract from insert" detection code.
Move the "extract from insert detection code" into a lambda helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364059
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James Henderson [Fri, 21 Jun 2019 14:41:36 +0000 (14:41 +0000)]
[docs][llvm-objdump] Fix bad merge of docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364056
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George Rimar [Fri, 21 Jun 2019 14:15:15 +0000 (14:15 +0000)]
[llvm-objcopy] - Get rid of dynrel.elf precompiled binary from inputs.
We do not have to spread using the precompiled binaries in the tests,
when we can use YAML. This patch removes the dynrel.elf binary and adds
a few comments to the test cases.
Differential revision: https://reviews.llvm.org/D63641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364052
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Jay Foad [Fri, 21 Jun 2019 14:10:18 +0000 (14:10 +0000)]
[Scalarizer] Propagate IR flags
Summary:
The motivation for this was to propagate fast-math flags like nnan and
ninf on vector floating point operations to the corresponding scalar
operations to take advantage of follow-on optimizations. But I think
the same argument applies to all of our IR flags: if they apply to the
vector operation then they also apply to all the individual scalar
operations, and they might enable follow-on optimizations.
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364051
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George Rimar [Fri, 21 Jun 2019 14:07:35 +0000 (14:07 +0000)]
[llvm-readobj] - Inline a few yaml inputs into test cases.
There are some test that are splitted into main part + input yaml for no visible reason.
This patch inines the yaml part for the 3 test cases I found.
Differential revision: https://reviews.llvm.org/D63644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364049
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Andrea Di Biagio [Fri, 21 Jun 2019 14:05:58 +0000 (14:05 +0000)]
Set an explicit x86 triple for test bottleneck-analysis.s added by my r364045. NFC
This should unbreak the ppc64 buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364048
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Sam Elliott [Fri, 21 Jun 2019 13:36:09 +0000 (13:36 +0000)]
[RISCV] Add RISCV-specific TargetTransformInfo
Summary:
LLVM Allows Targets to provide information that guides optimisations
made to LLVM IR. This is done with callbacks on a TargetTransformInfo object.
This patch adds a TargetTransformInfo class for RISC-V. This will allow us to
implement RISC-V specific callbacks as they become necessary.
This commit also adds the getIntImmCost callbacks, and tests them with a simple
constant hoisting test. Our immediate costs are on the conservative side, for
the moment, but we prevent hoisting in most circumstances anyway.
Previous review was on D63007
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364046
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Andrea Di Biagio [Fri, 21 Jun 2019 13:32:54 +0000 (13:32 +0000)]
[MCA][Bottleneck Analysis] Teach how to compute a critical sequence of instructions based on the simulation.
This patch teaches the bottleneck analysis how to identify and print the most
expensive sequence of instructions according to the simulation. Fixes PR37494.
The goal is to help users identify the sequence of instruction which is most
critical for performance.
A dependency graph is internally used by the bottleneck analysis to describe
data dependencies and processor resource interferences between instructions.
There is one node in the graph for every instruction in the input assembly
sequence. The number of nodes in the graph is independent from the number of
iterations simulated by the tool. It means that a single node of the graph
represents all the possible instances of a same instruction contributed by the
simulated iterations.
Edges are dynamically "discovered" by the bottleneck analysis by observing
instruction state transitions and "backend pressure increase" events generated
by the Execute stage. Information from the events is used to identify critical
dependencies, and materialize edges in the graph. A dependency edge is uniquely
identified by a pair of node identifiers plus an instance of struct
DependencyEdge::Dependency (which provides more details about the actual
dependency kind).
The bottleneck analysis internally ranks dependency edges based on their impact
on the runtime (see field DependencyEdge::Dependency::Cost). To this end, each
edge of the graph has an associated cost. By default, the cost of an edge is a
function of its latency (in cycles). In practice, the cost of an edge is also a
function of the number of cycles where the dependency has been seen as
'contributing to backend pressure increases'. The idea is that the higher the
cost of an edge, the higher is the impact of the dependency on performance. To
put it in another way, the cost of an edge is a measure of criticality for
performance.
Note how a same edge may be found in multiple iteration of the simulated loop.
The logic that adds new edges to the graph checks if an equivalent dependency
already exists (duplicate edges are not allowed). If an equivalent dependency
edge is found, field DependencyEdge::Frequency of that edge is incremented by
one, and the new cost is cumulatively added to the existing edge cost.
At the end of simulation, costs are propagated to nodes through the edges of the
graph. The goal is to identify a critical sequence from a node of the root-set
(composed by node of the graph with no predecessors) to a 'sink node' with no
successors. Note that the graph is intentionally kept acyclic to minimize the
complexity of the critical sequence computation algorithm (complexity is
currently linear in the number of nodes in the graph).
The critical path is finally computed as a sequence of dependency edges. For
edges describing processor resource interferences, the view also prints a
so-called "interference probability" value (by dividing field
DependencyEdge::Frequency by the total number of iterations).
Examples of critical sequence computations can be found in tests added/modified
by this patch.
On output streams that support colored output, instructions from the critical
sequence are rendered with a different color.
Strictly speaking the analysis conducted by the bottleneck analysis view is not
a critical path analysis. The cost of an edge doesn't only depend on the
dependency latency. More importantly, the cost of a same edge may be computed
differently by different iterations.
The number of dependencies is discovered dynamically based on the events
generated by the simulator. However, their number is not fixed. This is
especially true for edges that model processor resource interferences; an
interference may not occur in every iteration. For that reason, it makes sense
to also print out a "probability of interference".
By construction, the accuracy of this analysis (as always) is strongly dependent
on the simulation (and therefore the quality of the information available in the
scheduling model).
That being said, the critical sequence effectively identifies a performance
criticality. Instructions from that sequence are expected to have a very big
impact on performance. So, users can take advantage of this information to focus
their attention on specific interactions between instructions.
In my experience, it works quite well in practice, and produces useful
output (in a reasonable amount time).
Differential Revision: https://reviews.llvm.org/D63543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364045
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Simon Tatham [Fri, 21 Jun 2019 13:17:23 +0000 (13:17 +0000)]
[ARM] Add MVE 64-bit GPR <-> vector move instructions.
These instructions let you load half a vector register at once from
two general-purpose registers, or vice versa.
The assembly syntax for these instructions mentions the vector
register name twice. For the move _into_ a vector register, the MC
operand list also has to mention the register name twice (once as the
output, and once as an input to represent where the unchanged half of
the output register comes from). So we can conveniently assign one of
the two asm operands to be the output $Qd, and the other $QdSrc, which
avoids confusing the auto-generated AsmMatcher too much. For the move
_from_ a vector register, there's no way to get round the fact that
both instances of that register name have to be inputs, so we need a
custom AsmMatchConverter to avoid generating two separate output MC
operands. (And even that wouldn't have worked if it hadn't been for
D60695.)
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364041
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Simon Tatham [Fri, 21 Jun 2019 13:17:08 +0000 (13:17 +0000)]
[ARM] Add MVE vector instructions that take a scalar input.
This adds the `MVE_qDest_rSrc` superclass and all its instances, plus
a few other instructions that also take a scalar input register or two.
I've also belatedly added custom diagnostic messages to the operand
classes for odd- and even-numbered GPRs, which required matching
changes in two of the existing MVE assembly test files.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364040
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Paul Robinson [Fri, 21 Jun 2019 13:10:19 +0000 (13:10 +0000)]
Fix a crash with assembler source and -g.
llvm-mc or clang with -g normally produces debug info describing the
assembler source itself; however, if that source already contains some
.file/.loc directives, we should instead emit the debug info described
by those directives. For certain assembler sources seen in the wild
(particularly in the Chrome build) this was causing a crash due to
incorrect assumptions about legal sequences of assembler source text.
Fixes PR38994.
Differential Revision: https://reviews.llvm.org/D63573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364039
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Simon Pilgrim [Fri, 21 Jun 2019 12:42:39 +0000 (12:42 +0000)]
[X86] X86ISD::ANDNP is a (non-commutative) binop
The sat add/sub tests still have unnecessary extract_subvector((vandnps ymm, ymm), 0) uses that should be split to (vandnps (extract_subvector(ymm, 0), extract_subvector(ymm, 0)), but its getting better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364038
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Simon Tatham [Fri, 21 Jun 2019 12:13:59 +0000 (12:13 +0000)]
[ARM] Add a batch of similarly encoded MVE instructions.
Summary:
This adds the `MVE_qDest_qSrc` superclass and all instructions that
inherit from it. It's not the complete class of _everything_ with a
q-register as both destination and source; it's a subset of them that
all have similar encodings (but it would have been hopelessly unwieldy
to call it anything like MVE_111x11100).
This category includes add/sub with carry; long multiplies; halving
multiplies; multiply and accumulate, and some more complex
instructions.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364037
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James Henderson [Fri, 21 Jun 2019 11:49:20 +0000 (11:49 +0000)]
[binutils] Add response file option to help and docs
Many LLVM-based tools already support response files (i.e. files
containing a list of options, specified with '@'). This change simply
updates the documentation and help text for some of these tools to
include it. I haven't attempted to fix all tools, just a selection that
I am interested in.
I've taken the opportunity to add some tests for --help behaviour, where
they were missing. We could expand these tests, but I don't think that's
within scope of this patch.
This fixes https://bugs.llvm.org/show_bug.cgi?id=42233 and
https://bugs.llvm.org/show_bug.cgi?id=42236.
Reviewed by: grimar, MaskRay, jkorous
Differential Revision: https://reviews.llvm.org/D63597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364036
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Simon Pilgrim [Fri, 21 Jun 2019 11:25:06 +0000 (11:25 +0000)]
[X86] createMMXBuildVector - call with BuildVectorSDNode directly. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364030
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James Henderson [Fri, 21 Jun 2019 11:22:20 +0000 (11:22 +0000)]
[llvm-dwarfdump] Remove unnecessary explicit -h behaviour
--help and -h are automatically supported by the command-line parser,
unless overridden by the tool. The behaviour of the PrintHelpMessage
being used for -h prior to this patch is subtly different to that
provided by --help automatically (it omits certain elements of help text
and options, such as --help-list), so overriding the default is not
desirable, without good reason. This patch removes the explicit
specification of -h and its behaviour, so that the default behaviour is
used.
Reviewed by: hintonda
Differential Revision: https://reviews.llvm.org/D63565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364029
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Fangrui Song [Fri, 21 Jun 2019 11:19:11 +0000 (11:19 +0000)]
[ARM] Fix -Wimplicit-fallthrough after D62675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364028
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Simon Tatham [Fri, 21 Jun 2019 11:14:51 +0000 (11:14 +0000)]
[ARM] Add MVE vector compare instructions.
Summary:
These take a pair of vector register to compare, and a comparison type
(written in the form of an Arm condition suffix); they output a vector
of booleans in the VPR register, where predication can conveniently
use them.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364027
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Simon Pilgrim [Fri, 21 Jun 2019 11:13:15 +0000 (11:13 +0000)]
[X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364026
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Fangrui Song [Fri, 21 Jun 2019 11:05:26 +0000 (11:05 +0000)]
[Symbolize] Avoid lifetime extension and simplify std::map find/insert. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364025
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96231b3b80d8
Simon Pilgrim [Fri, 21 Jun 2019 10:54:30 +0000 (10:54 +0000)]
[X86] foldVectorXorShiftIntoCmp - use isConstOrConstSplat. NFCI.
Use the isConstOrConstSplat helper instead of inspecting the build vector manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364024
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 21 Jun 2019 10:44:15 +0000 (10:44 +0000)]
[X86][AVX] isNOT - handle concat_vectors(xor X, -1, xor Y, -1) pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364022
91177308-0d34-0410-b5e6-
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James Henderson [Fri, 21 Jun 2019 10:12:53 +0000 (10:12 +0000)]
[docs][llvm-objdump] Improve llvm-objdump documentation
The llvm-objdump document was missing many options, and there were also
some style issues with it. This patches fixes all but the first issue
listed in https://bugs.llvm.org/show_bug.cgi?id=42249 by:
1. Adding missing options and commands.
2. Standardising on double dashes for long-options throughout.
3. Moving Mach-O specific options to a separate section.
4. Removing options that don't exist or aren't relevant to
llvm-objdump.
Reviewed by: MaskRay, mtrent, alexshap
Differential Revision: https://reviews.llvm.org/D63606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364019
91177308-0d34-0410-b5e6-
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Vitaly Buka [Fri, 21 Jun 2019 09:54:32 +0000 (09:54 +0000)]
[GN] Fix check-clang by disabling plugins
We can't link Analysis/plugins without -fPIC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364016
91177308-0d34-0410-b5e6-
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Vitaly Buka [Fri, 21 Jun 2019 09:54:31 +0000 (09:54 +0000)]
[GN] Put libcxx include into the same place as cmake to fix Driver/print-file-name.c test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364015
91177308-0d34-0410-b5e6-
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Simon Tatham [Fri, 21 Jun 2019 09:35:07 +0000 (09:35 +0000)]
[ARM] Add a batch of MVE floating-point instructions.
Summary:
This includes floating-point basic arithmetic (add/sub/multiply),
complex add/multiply, unary negation and absolute value, rounding to
integer value, and conversion to/from integer formats.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364013
91177308-0d34-0410-b5e6-
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Mehdi Amini [Fri, 21 Jun 2019 05:43:08 +0000 (05:43 +0000)]
Use std::iterator_traits to infer result type of llvm::enumerate iterator wrapper
Update the llvm::enumerate helper class result_pair<R> to use the 'iterator_traits<R>::reference'
type as the result of 'value()' instead 'ValueOfRange<R> &'. This enables support for iterators
that return value types, i.e. non reference. This is a common pattern for some classes of
iterators, e.g. mapped_iterator.
Patch by: River Riddle <riverriddle@google.com>
Differential Revision: https://reviews.llvm.org/D63632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364007
91177308-0d34-0410-b5e6-
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Fangrui Song [Fri, 21 Jun 2019 05:40:31 +0000 (05:40 +0000)]
Simplify std::lower_bound with llvm::{bsearch,lower_bound}. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364006
91177308-0d34-0410-b5e6-
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Yevgeny Rouban [Fri, 21 Jun 2019 04:49:40 +0000 (04:49 +0000)]
[LICM & MSSA] Fixed test to run only with assertions enabled as it uses -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364005
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Fri, 21 Jun 2019 02:15:07 +0000 (02:15 +0000)]
[GN] Fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364004
91177308-0d34-0410-b5e6-
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Fangrui Song [Fri, 21 Jun 2019 01:51:50 +0000 (01:51 +0000)]
[MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364003
91177308-0d34-0410-b5e6-
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Amara Emerson [Fri, 21 Jun 2019 00:36:19 +0000 (00:36 +0000)]
[GlobalISel][Localizer] Allow localization of G_INTTOPTR and chains of instructions.
G_INTTOPTR can prevent the localizer from moving G_CONSTANTs, but since it's
essentially a side effect free cast instruction we can remat both instructions.
This patch changes the localizer to enable localization of the chains by
iterating over the entry block instructions in reverse order. That way, uses will
localized first, and then the defs are free to be localized as well.
This also changes the previous SmallPtrSet of localized instructions to use a
SetVector instead. We're dealing with pointers and need deterministic iteration
order.
Overall, this change improves ARM64 -O0 CTMark code size by around 0.7% geomean.
Differential Revision: https://reviews.llvm.org/D63630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364001
91177308-0d34-0410-b5e6-
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Seiya Nuta [Fri, 21 Jun 2019 00:21:50 +0000 (00:21 +0000)]
[llvm-objcopy][MachO] Rebuild the symbol/string table in the writer
Summary: Build the string table using StringTableBuilder, reassign symbol indices, and update symbol indices in relocations to allow adding/modifying/removing symbols from the object.
Reviewers: alexshap, rupprecht, jhenderson
Reviewed By: alexshap
Subscribers: mgorny, jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364000
91177308-0d34-0410-b5e6-
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Cameron McInally [Thu, 20 Jun 2019 23:03:55 +0000 (23:03 +0000)]
[Reassociate] Remove bogus assert reported in PR42349.
Also, add a FIXME for the unsafe transform on a unary FNeg. A unary FNeg can only be transformed to a FMul by -1.0 when the nnan flag is present. The unary FNeg project is a WIP, so the unsafe transformation is acceptable until that work is complete.
The bogus assert with introduced in D63445.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363998
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 22:55:28 +0000 (22:55 +0000)]
[InstSimplify] simplify power-of-2 (single bit set) sequences
As discussed in PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
Improving the canonicalization for these patterns:
rL363956
...means we should adjust/enhance the related simplification.
https://rise4fun.com/Alive/w1cp
Name: isPow2 or zero
%x = and i32 %xx, 2048
%a = add i32 %x, -1
%r = and i32 %a, %x
=>
%r = i32 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363997
91177308-0d34-0410-b5e6-
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Evandro Menezes [Thu, 20 Jun 2019 22:03:54 +0000 (22:03 +0000)]
[CodeGen] Refactor check of suitability for a jump table (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363992
91177308-0d34-0410-b5e6-
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Eli Friedman [Thu, 20 Jun 2019 22:00:07 +0000 (22:00 +0000)]
[ARM GlobalISel] Tests for s64 G_ADD and G_SUB.
Forgot to commit these in r363989 (https://reviews.llvm.org/D63585)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363991
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 21:58:24 +0000 (21:58 +0000)]
AMDGPU: Always use s33 for global scratch wave offset
Every called function could possibly need this to calculate the
absolute address of stack objectst, and this avoids inserting a copy
around every call site in the kernel. It's also somewhat cleaner to
keep this in a callee saved SGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363990
91177308-0d34-0410-b5e6-
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Eli Friedman [Thu, 20 Jun 2019 21:56:47 +0000 (21:56 +0000)]
[ARM GlobalISel] Add support for s64 G_ADD and G_SUB.
Teach RegisterBankInfo to use the correct register class, and tell the
legalizer it's legal. Everything else just works.
The one thing that's slightly weird about this compared to SelectionDAG
isel is that legalization can't distinguish between i64 and <1 x i64>,
so we might end up with more NEON instructions than the user expects.
Differential Revision: https://reviews.llvm.org/D63585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363989
91177308-0d34-0410-b5e6-
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Jinsong Ji [Thu, 20 Jun 2019 21:36:06 +0000 (21:36 +0000)]
[PowerPC][NFC] Fix comments for AltVSXFMARel mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363987
91177308-0d34-0410-b5e6-
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Rainer Orth [Thu, 20 Jun 2019 21:27:06 +0000 (21:27 +0000)]
[profile] Solaris ld supports __start___llvm_prof_data etc. labels
Currently, many profiling tests on Solaris FAIL like
Command Output (stderr):
--
Undefined first referenced
symbol in file
__llvm_profile_register_names_function /tmp/lit_tmp_Nqu4eh/infinite_loop-9dc638.o
__llvm_profile_register_function /tmp/lit_tmp_Nqu4eh/infinite_loop-9dc638.o
Solaris 11.4 ld supports the non-standard GNU ld extension of adding
__start_SECNAME and __stop_SECNAME labels to sections whose names are valid
as C identifiers. Given that we already use Solaris 11.4-only features
like ld -z gnu-version-script-compat and fully working .preinit_array
support in compiler-rt, we don't need to worry about older versions of
Solaris ld.
The patch documents that support (although the comment in
lib/Transforms/Instrumentation/InstrProfiling.cpp
(needsRuntimeRegistrationOfSectionRange) is quite cryptic what it's
actually about), and adapts the affected testcase not to expect the
alternativeq __llvm_profile_register_functions and __llvm_profile_init.
It fixes all affected tests.
Tested on amd64-pc-solaris2.11.
Differential Revision: https://reviews.llvm.org/D41111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363984
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 21:11:42 +0000 (21:11 +0000)]
AMDGPU: Add intrinsics for DS GWS semaphore instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363983
91177308-0d34-0410-b5e6-
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Alina Sbirlea [Thu, 20 Jun 2019 21:09:09 +0000 (21:09 +0000)]
[LICM & MSSA] Limit unsafe sinking and hoisting.
Summary:
The getClobberingMemoryAccess API checks for clobbering accesses in a loop by walking the backedge. This may check if a memory access is being
clobbered by the loop in a previous iteration, depending how smart AA got over the course of the updates in MemorySSA (it does not occur when built from scratch).
If no clobbering access is found inside the loop, it will optimize to an access outside the loop. This however does not mean that access is safe to sink.
Given:
```
for i
load a[i]
store a[i]
```
The access corresponding to the load can be optimized to outside the loop, and the load can be hoisted. But it is incorrect to sink it.
In order to sink the load, we'd need to check no Def clobbers the Use in the same iteration. With this patch we currently restrict sinking to either
Defs not existing in the loop, or Defs preceding the load in the same block. An easy extension is to ensure the load (Use) post-dominates all Defs.
Caught by PR42294.
This issue also shed light on the converse problem: hoisting stores in this same scenario would be illegal. With this patch we restrict
hoisting of stores to the case when their corresponding Defs are dominating all Uses in the loop.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363982
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 21:04:14 +0000 (21:04 +0000)]
[InstSimplify] add tests for known-not-a-power-of-2; NFC
I added a canonicalization to create this general pattern in:
rL363956
But as noted in PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314#c11
...we have a (potentially expensive) simplification for the version
of the code that we just canonicalized away from, so we should
add/adjust that code to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363981
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 20:54:32 +0000 (20:54 +0000)]
AMDGPU: Insert mem_viol check loop around GWS pre-GFX9
It is necessary to emit this loop around GWS operations in case the
wave is preempted pre-GFX9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363979
91177308-0d34-0410-b5e6-
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Cameron McInally [Thu, 20 Jun 2019 20:53:51 +0000 (20:53 +0000)]
[NFC][SLP] Pre-commit unary FNeg test to X86/propagate_ir_flags.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363978
91177308-0d34-0410-b5e6-
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Leonard Chan [Thu, 20 Jun 2019 20:51:58 +0000 (20:51 +0000)]
Update LLVM test to not check for the EliminateAvailableExternallyPass
for lto-pre-link O2 pipeline runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363977
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 20:23:32 +0000 (20:23 +0000)]
[InstCombine] fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363974
91177308-0d34-0410-b5e6-
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Leonard Chan [Thu, 20 Jun 2019 19:44:51 +0000 (19:44 +0000)]
[clang][NewPM] Do not eliminate available_externally durng `-O2 -flto` runs
This fixes CodeGen/available-externally-suppress.c when the new pass manager is
turned on by default. available_externally was not emitted during -O2 -flto
runs when it should still be retained for link time inlining purposes. This can
be fixed by checking that we aren't LTOPrelinking when adding the
EliminateAvailableExternallyPass.
Differential Revision: https://reviews.llvm.org/D63580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363971
91177308-0d34-0410-b5e6-
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David Bolvansky [Thu, 20 Jun 2019 19:39:15 +0000 (19:39 +0000)]
[NFC] Add more tests for D46262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363970
91177308-0d34-0410-b5e6-
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David Bolvansky [Thu, 20 Jun 2019 19:30:56 +0000 (19:30 +0000)]
[NFC] Updated tests for D63546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363967
91177308-0d34-0410-b5e6-
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Philip Reames [Thu, 20 Jun 2019 18:45:06 +0000 (18:45 +0000)]
[LFTR] Fix a (latent?) bug related to nested loops
I can't actually come up with a test case this triggers on without an out of tree change, but in theory, it's a bug in the recently added multiple exit LFTR support. The root issue is that an exiting block common to two loops can (in theory) have computable exit counts for both loops. Rewriting the exit of an inner loop in terms of the outer loops IV would cause the inner loop to either a) run forever, or b) terminate on the first iteration.
In practice, we appear to get lucky and not have the exit count computable for the outer loop, except when it's trivially zero. Given we bail on zero exit counts, we don't appear to ever trigger this. But I can't come up with a reason we *can't* compute an exit count for the outer loop on the common exiting block, so this may very well be triggering in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363964
91177308-0d34-0410-b5e6-
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Nico Weber [Thu, 20 Jun 2019 18:18:40 +0000 (18:18 +0000)]
gn build: Merge r363948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363960
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 20 Jun 2019 17:52:53 +0000 (17:52 +0000)]
[X86] Add BLSI to isUseDefConvertible.
Summary:
BLSI sets the C flag is the input is not zero. So if its followed
by a TEST of the input where only the Z flag is consumed, we can
replace it with the opposite check of the C flag.
We should be able to do the same for BLSMSK and BLSR, but the
naive test case for those is being optimized to a subo by
CodeGenPrepare.
Reviewers: spatel, RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363957
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 17:41:15 +0000 (17:41 +0000)]
[InstCombine] canonicalize check for power-of-2
The form that compares against 0 is better because:
1. It removes a use of the input value.
2. It's the more standard form for this pattern: https://graphics.stanford.edu/~seander/bithacks.html#DetermineIfPowerOf2
3. It results in equal or better codegen (tested with x86, AArch64, ARM, PowerPC, MIPS).
This is a root cause for PR42314, but probably doesn't completely answer the codegen request:
https://bugs.llvm.org/show_bug.cgi?id=42314
Alive proof:
https://rise4fun.com/Alive/9kG
Name: is power-of-2
%neg = sub i32 0, %x
%a = and i32 %neg, %x
%r = icmp eq i32 %a, %x
=>
%dec = add i32 %x, -1
%a2 = and i32 %dec, %x
%r = icmp eq i32 %a2, 0
Name: is not power-of-2
%neg = sub i32 0, %x
%a = and i32 %neg, %x
%r = icmp ne i32 %a, %x
=>
%dec = add i32 %x, -1
%a2 = and i32 %dec, %x
%r = icmp ne i32 %a2, 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363956
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 20 Jun 2019 17:36:23 +0000 (17:36 +0000)]
[DAGCombiner] Use getAPIntValue() instead of getZExtValue() where possible.
Better handling of out-of-i64-range values due to large integer types or from fuzz tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363955
91177308-0d34-0410-b5e6-
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Jordan Rupprecht [Thu, 20 Jun 2019 17:30:01 +0000 (17:30 +0000)]
[DAGCombiner][NFC] Remove unused var
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363954
91177308-0d34-0410-b5e6-
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Philip Reames [Thu, 20 Jun 2019 17:16:53 +0000 (17:16 +0000)]
[Tests] Add a tricky LFTR case for documentation purposes
Thought of this case while working on something else. We appear to get it right in all of the variations I tried, but that's by accident. So, add a test which would catch the potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363953
91177308-0d34-0410-b5e6-
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Amy Huang [Thu, 20 Jun 2019 17:15:21 +0000 (17:15 +0000)]
Store a pointer to the return value in a static alloca and let the debugger use that
as the variable address for NRVO variables.
Subscribers: hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D63361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363952
91177308-0d34-0410-b5e6-
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David Bolvansky [Thu, 20 Jun 2019 17:04:14 +0000 (17:04 +0000)]
[InstCombine] cttz(-x) -> cttz(x)
Summary: Signedness does not change number of trailing zeros.
Reviewers: spatel, lebedev.ri, nikic
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363951
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 17:03:27 +0000 (17:03 +0000)]
AMDGPU: Eliminate test usage of legacy FP elim attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363950
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 17:03:23 +0000 (17:03 +0000)]
AMDGPU: Fix ignoring DisableFramePointerElim in leaf functions
The attribute can specify elimination for leaf or non-leaf, so it
should always be considered. I copied this bug from AArch64, which
probably should also be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363949
91177308-0d34-0410-b5e6-
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Evandro Menezes [Thu, 20 Jun 2019 16:34:00 +0000 (16:34 +0000)]
[CodeGen] Fix formatting and comments (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363947
91177308-0d34-0410-b5e6-
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Stanislav Mekhanoshin [Thu, 20 Jun 2019 16:29:40 +0000 (16:29 +0000)]
[AMDGPU] gfx10 tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363946
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 16:27:23 +0000 (16:27 +0000)]
[InstCombine] add commuted variants for power-of-2 checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363945
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Thu, 20 Jun 2019 16:01:09 +0000 (16:01 +0000)]
AMDGPU: Treat undef as an inline immediate
This should only matter in vectors with an undef component, since a
full undef vector would have been folded out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363941
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 20 Jun 2019 15:38:30 +0000 (15:38 +0000)]
AMDGPU: Make test functions hidden
Reduces amount of code in the function from eliminating the GOT load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363940
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Jun 2019 15:25:18 +0000 (15:25 +0000)]
[InstCombine] add tests for checking power-of-2; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363938
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Thu, 20 Jun 2019 15:17:17 +0000 (15:17 +0000)]
[NFC][SLP] Pre-commit unary FNeg test to X86/phi3.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363937
91177308-0d34-0410-b5e6-
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Simon Tatham [Thu, 20 Jun 2019 15:16:56 +0000 (15:16 +0000)]
[ARM] Add a batch of MVE integer instructions.
This includes integer arithmetic of various kinds (add/sub/multiply,
saturating and not), and the immediate forms of VMOV and VMVN that
load an immediate into all lanes of a vector.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363936
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Stanislav Mekhanoshin [Thu, 20 Jun 2019 15:08:34 +0000 (15:08 +0000)]
[AMDGPU] gfx1010 core wave32 changes
Differential Revision: https://reviews.llvm.org/D63204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363934
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Stanislav Mekhanoshin [Thu, 20 Jun 2019 14:59:28 +0000 (14:59 +0000)]
Virtualize TargetInstrInfo::getRegClass()
AMDGPU target needs to override getRegClass() used during
instruction selection. We now may have either 32 or 64 bit
conditional registers used in the same instructions. For
that purpose special SReg_1 register class is created which
is dynamically resolved to either SReg_64 or SGPR_32 depending
on the subtarget attributes.
Differential Revision: https://reviews.llvm.org/D63205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363931
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George Rimar [Thu, 20 Jun 2019 14:44:48 +0000 (14:44 +0000)]
[yaml2obj] - Convert `ELFState<ELFT>::addSymbols` method to `toELFSymbols` helper. NFCI.
ELFState<ELFT>::addSymbols method looks a bit strange.
User code have to create the destination symbols vector outside,
add a null symbol and then pass it to addSymbols when it seems
the more natural logic is to isolate all work with symbols inside some
function, build the list right there and return it.
Differential revision: https://reviews.llvm.org/D63493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363930
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Simon Pilgrim [Thu, 20 Jun 2019 14:42:27 +0000 (14:42 +0000)]
[DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363929
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Simon Pilgrim [Thu, 20 Jun 2019 12:52:58 +0000 (12:52 +0000)]
[SLP][X86] Add lookahead reordering tests from D60897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363925
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Simon Pilgrim [Thu, 20 Jun 2019 12:48:49 +0000 (12:48 +0000)]
[DAGCombine] Add TODOs for some combines that should support non-uniform vectors
We tend to only test for scalar/scalar consts when really we could support non-uniform vectors using ISD::matchUnaryPredicate/matchBinaryPredicate etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363924
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Simon Pilgrim [Thu, 20 Jun 2019 11:31:54 +0000 (11:31 +0000)]
[X86] LowerAVXExtend - handle ANY_EXTEND_VECTOR_INREG lowering as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363922
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Simon Pilgrim [Thu, 20 Jun 2019 10:56:37 +0000 (10:56 +0000)]
[DAGCombine] Reduce scope of ShAmtVal variable. NFCI.
Fixes cppcheck warning.
Use the more capable getAPIntVal() instead of getZExtValue() as well since I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363921
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Fangrui Song [Thu, 20 Jun 2019 10:15:11 +0000 (10:15 +0000)]
[llvm-nm] Generalize ELF symbol types 'N' and 'n'
Reviewed By: grimar, jhenderson
Differential Revision: https://reviews.llvm.org/D63588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363918
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Serge Guelton [Thu, 20 Jun 2019 09:37:52 +0000 (09:37 +0000)]
[NFC] Update documentation for AtomicCmpXchgInst
Fix bz#42325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363914
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Sjoerd Meijer [Thu, 20 Jun 2019 09:33:11 +0000 (09:33 +0000)]
TargetParserTest.ARMExtensionFeatures run out of memory on 32-bit (PR42316)
Nothing of these tests made much sense. Loops were iterating too much, and I
also don't think it was actually testing anything. I think we simply want to
check that AEK_SOME_EXT returns "+some_ext".
I've given the AArch64 tests the same treatment as they very similarly didn't
made any sense either.
This fixes PR42316.
Differential Revision: https://reviews.llvm.org/D63569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363913
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