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Sanjay Patel [Tue, 10 Apr 2018 17:56:24 +0000 (17:56 +0000)]
[llvm-mca] fix formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329729
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Jessica Paquette [Tue, 10 Apr 2018 17:53:41 +0000 (17:53 +0000)]
Revert 329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"
This broke a bunch of bots so I'm reverting while I figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329728
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Sanjay Patel [Tue, 10 Apr 2018 17:49:45 +0000 (17:49 +0000)]
[llvm-mca] add example workflow for source code
This is copied from Andrea's text in PR36875:
https://bugs.llvm.org/show_bug.cgi?id=36875
As noted there, this is a hack...but it's a good one!
It's important to show potential workflows up-front
with examples, so customers can copy and experiment
with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329726
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Aaron Smith [Tue, 10 Apr 2018 17:33:18 +0000 (17:33 +0000)]
[DebugInfoPDB] Add DIA implementations of findSymbolByRVA and findSymbolByAddr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329724
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Jessica Paquette [Tue, 10 Apr 2018 17:32:12 +0000 (17:32 +0000)]
Fix test failure in arm64-no-section.ll
There was a missing not line. Also, tail call before ret -> call before ret.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329723
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Krzysztof Parzyszek [Tue, 10 Apr 2018 16:46:13 +0000 (16:46 +0000)]
[CodeGen] Fix printing bundles in MIR output
Delay printing the newline until after the opening bracket was
printed, e.g.
BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 {
renamable $r1 = S2_asr_i_r renamable $r1, 1
renamable $r21 = A2_tfrsi 0
}
instead of
BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1
{ renamable $r1 = S2_asr_i_r renamable $r1, 1
renamable $r21 = A2_tfrsi 0
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329719
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Peter Collingbourne [Tue, 10 Apr 2018 16:19:30 +0000 (16:19 +0000)]
Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF."
Caused a build failure in check-tsan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329718
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Jessica Paquette [Tue, 10 Apr 2018 15:53:28 +0000 (15:53 +0000)]
Add missing nullptr check to AArch64MachObjectWriter::recordRelocation
There was missing nullptr check before a call to getSection() in
recordRelocation. This would result in a segfault in code like the attached
test.
This adds the missing check and a test which makes sure we get the expected
error output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329716
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Nicolai Haehnle [Tue, 10 Apr 2018 15:46:43 +0000 (15:46 +0000)]
AMDGPU/MC: Allow disassembling without symbol info
Summary:
We would like the UMR debugging tool[0] to be able to provide
disassembly for currently live waves based on plain memory
dumps, and we want to leverage the LLVM disassembler for this.
This mostly works, except that UMR clearly can't provide real
symbol info, so it wants to set DisInfo == nullptr.
[0] https://cgit.freedesktop.org/amd/umr/
Reviewers: arsenm, rampitec, artem.tamazov, dp
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45477
Change-Id: Ibb2c5af2e66f2e100b4702fd81308e1932bc4ee6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329715
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Aaron Smith [Tue, 10 Apr 2018 15:25:04 +0000 (15:25 +0000)]
[PDB] Remove dead code and run clang format; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329712
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Andrea Di Biagio [Tue, 10 Apr 2018 15:14:15 +0000 (15:14 +0000)]
[llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329711
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Chad Rosier [Tue, 10 Apr 2018 14:57:13 +0000 (14:57 +0000)]
Fix spelling. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329709
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Andrea Di Biagio [Tue, 10 Apr 2018 14:55:14 +0000 (14:55 +0000)]
[llvm-mca] Move the logic that prints dispatch unit statistics from BackendStatistics to its own view.
This patch moves the logic that collects and analyzes dispatch events to the
DispatchStatistics view.
Added flag -dispatch-stats to print statistics related to the dispatch logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329708
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Aaron Smith [Tue, 10 Apr 2018 14:47:12 +0000 (14:47 +0000)]
[pdbutil] Print the checksum hex string when using the '-lines' option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329707
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Pavel Labath [Tue, 10 Apr 2018 14:23:41 +0000 (14:23 +0000)]
[CodeGen/Dwarf] Rename the "sizetype" synthetic type and add it to the accelerator table
Summary:
This type is created on-demand and used as the base type for array
ranges. Since it is "special", its construction did not go through the
createTypeDIE function and so it was never inserted into the accelerator
table, although it clearly belongs there.
I add an explicit addAccelType call to insert it into the table.
During review, we also decided to rename the type to something more
unique to avoid confusion in case the user has own "sizetype" type. The
new name for the type size __ARRAY_SIZE_TYPE__.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329705
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Simon Pilgrim [Tue, 10 Apr 2018 14:21:33 +0000 (14:21 +0000)]
Fix whitespace indentation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329704
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Pavel Labath [Tue, 10 Apr 2018 14:11:53 +0000 (14:11 +0000)]
[Testing/Support] Make Failed() matcher work with abstract error types
Failed<ErrorInfoBase>() did not compile, because it was attempting to
create a copy of the Error object when passing it to the nested matcher,
which was not possible because ErrorInfoBase is abstract.
This commit fixes the problem by making sure we pass the ErrorInfo
object by reference, which also improves the handling of non-abstract
objects, as we avoid potentially slicing an object during the copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329703
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Gabor Buella [Tue, 10 Apr 2018 13:58:57 +0000 (13:58 +0000)]
[X86] Disable SGX for Skylake Server
Reviewers: craig.topper, zvi, echristo
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329700
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Andrea Di Biagio [Tue, 10 Apr 2018 12:50:03 +0000 (12:50 +0000)]
[llvm-mca] Increase the default number of iterations to 100.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329694
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David Green [Tue, 10 Apr 2018 11:37:21 +0000 (11:37 +0000)]
[DA] Improve alias checking in dependence analysis
Improve the alias analysis to account for cases where we
know that src/dst pairs cannot alias due to things like
TBAA. As we know they are noalias, we know no dependency
can occur. Also fixes issues around the size parameter
to AA being incorrect.
Differential Revision: https://reviews.llvm.org/D42381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329692
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Francis Visoiu Mistrih [Tue, 10 Apr 2018 11:29:40 +0000 (11:29 +0000)]
[AArch64] Use FP to access the emergency spill slot
In the presence of variable-sized stack objects, we always picked the
base pointer when resolving frame indices if it was available.
This makes us hit an assert where we can't reach the emergency spill
slot if it's too far away from the base pointer. Since on AArch64 we
decide to place the emergency spill slot at the top of the frame, it
makes more sense to use FP to access it.
The changes here don't affect only emergency spill slots but all the
frame indices. The goal here is to try to choose between FP, BP and SP
so that we minimize the offset and avoid scavenging, or worse, asserting
when trying to access a slot allocated by the scavenger.
Previously discussed here: https://reviews.llvm.org/D40876.
Differential Revision: https://reviews.llvm.org/D45358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329691
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Tim Renouf [Tue, 10 Apr 2018 11:25:15 +0000 (11:25 +0000)]
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
Summary:
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).
This commit fixes that to use offset 0x10 instead of offset 0 for a
compute shader, per the PAL ABI spec.
V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading
scratch descriptor from GIT.
Reviewers: kzhuravl, nhaehnle, timcorringham
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm
Differential Revision: https://reviews.llvm.org/D44468
Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329690
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Tim Northover [Tue, 10 Apr 2018 11:04:29 +0000 (11:04 +0000)]
AArch64: diagnose unpredictable store-exclusive instructions
Much like any written register in load/store instructions, the status register
is not allowed to overlap with any others. So diagnose it like we already do
with the other cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329687
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Andrea Di Biagio [Tue, 10 Apr 2018 10:49:41 +0000 (10:49 +0000)]
[X86][Broadwell] HWPort5 should not be added to BroadwellModelProcResources.
The BroadwellModelProcResources had an entry for HWPort5, which is a Haswell
resource, and not a Broadwell processor resource. That entry was added to the
Broadwell model because variable blends were consuming it.
This was clearly a typo (the resource name should have been BWPort5), which
unfortunately was never caught before. It was not reported as an error because
HWPort5 is a resource defined by the Haswell model. It has been found when
testing some code with llvm-mca: the list of resources in the resource pressure
view was odd.
This patch fixes the issue; now variable blend instructions consume 2 cycles on
BWPort5 instead of HWPort5. This is enough to get rid of the extra (spurious)
entry in the BroadWellModelProcResources table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329686
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Alexandre Ganea [Tue, 10 Apr 2018 10:26:23 +0000 (10:26 +0000)]
[llvm-ar] Temporarily make the tool case detection test Windows-only to fix the build (introduced in r329658)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329683
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Sander de Smalen [Tue, 10 Apr 2018 10:03:13 +0000 (10:03 +0000)]
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329681
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Andrea Di Biagio [Tue, 10 Apr 2018 09:55:33 +0000 (09:55 +0000)]
Reapply "[llvm-mca] Do not separate iterations with a newline in the timeline view."
This reapplies r329403 with a fix for the floating point rounding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329680
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Clement Courbet [Tue, 10 Apr 2018 08:43:46 +0000 (08:43 +0000)]
[MC][TableGen] Fix r329675.
Caught by bots with -Wmissing-braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329676
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Clement Courbet [Tue, 10 Apr 2018 08:16:37 +0000 (08:16 +0000)]
[MC][TableGen] Add optional libpfm counter names for ProcResUnits.
Summary:
Subtargets can define the libpfm counter names that can be used to
measure cycles and uops issued on ProcResUnits.
This allows making llvm-exegesis available on more targets.
Fixes PR36984.
Reviewers: gchatelet, RKSimon, andreadb, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329675
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Sander de Smalen [Tue, 10 Apr 2018 07:01:53 +0000 (07:01 +0000)]
[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329674
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Chandler Carruth [Tue, 10 Apr 2018 06:40:51 +0000 (06:40 +0000)]
[x86] Model the direction flag (DF) separately from the rest of EFLAGS.
This cleans up a number of operations that only claimed te use EFLAGS
due to using DF. But no instructions which we think of us setting EFLAGS
actually modify DF (other than things like popf) and so this needlessly
creates uses of EFLAGS that aren't really there.
In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD,
and the whole-flags writes (WRFLAGS and POPF) need to model this.
I've also somewhat cleaned up some of the flag management instruction
definitions to be in the correct .td file.
Adding this extra register also uncovered a failure to use the correct
datatype to hold X86 registers, and I've corrected that as necessary
here.
Differential Revision: https://reviews.llvm.org/D45154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329673
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Craig Topper [Tue, 10 Apr 2018 03:44:15 +0000 (03:44 +0000)]
[X86] Prevent folding loads with 64-bit ANDs with immediates that fit in 32-bits.
Prefer to use the 32-bit AND with immediate instead.
Primarily I'm doing this to ensure that immediates created by shrinkAndImmediate will always get absorbed into the AND. But I do believe this would be a reduction in the number of uops that need to execute. Ideally we should shrink the 'and' and the 'load' during DAG combine to re-enable the fold.
Fixes PR37063.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329667
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Michael Zolotukhin [Tue, 10 Apr 2018 03:40:29 +0000 (03:40 +0000)]
Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
This reverts r329661. Bots are still unhappy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329666
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Michael Zolotukhin [Tue, 10 Apr 2018 02:16:45 +0000 (02:16 +0000)]
Revert "Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading.""
This reapplies commit r329644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329661
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Michael Zolotukhin [Tue, 10 Apr 2018 02:16:29 +0000 (02:16 +0000)]
[SSAUpdaterBulk] Handle CFG with unreachable from entry blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329660
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Alexandre Ganea [Tue, 10 Apr 2018 01:58:45 +0000 (01:58 +0000)]
[DebugInfo][COFF] Fix reading variable-length encoded records
While reading Codeview records which contain variable-length encoded integers,
such as LF_BCLASS, LF_ENUMERATE, LF_MEMBER, LF_VBCLASS or LF_IVBCLASS,
the record's size would be improperly calculated in cases where the value was
indeed of a variable length (>= LF_NUMERIC). This caused a bad alignement on
the next record, which would/might crash later on.
Differential Revision: https://reviews.llvm.org/D45104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329659
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Alexandre Ganea [Tue, 10 Apr 2018 01:50:25 +0000 (01:50 +0000)]
[llvm-ar] Fix lib.exe detection when running within MSVC toolchain
Differential Revision: https://reviews.llvm.org/D44808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329658
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Chandler Carruth [Tue, 10 Apr 2018 01:41:17 +0000 (01:41 +0000)]
[x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues.
The key idea is to lower COPY nodes populating EFLAGS by scanning the
uses of EFLAGS and introducing dedicated code to preserve the necessary
state in a GPR. In the vast majority of cases, these uses are cmovCC and
jCC instructions. For such cases, we can very easily save and restore
the necessary information by simply inserting a setCC into a GPR where
the original flags are live, and then testing that GPR directly to feed
the cmov or conditional branch.
However, things are a bit more tricky if arithmetic is using the flags.
This patch handles the vast majority of cases that seem to come up in
practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of
partially preserved EFLAGS as LLVM doesn't currently model that at all.
There are a large number of operations that techinaclly observe EFLAGS
currently but shouldn't in this case -- they typically are using DF.
Currently, they will not be handled by this approach. However, I have
never seen this issue come up in practice. It is already pretty rare to
have these patterns come up in practical code with LLVM. I had to resort
to writing MIR tests to cover most of the logic in this pass already.
I suspect even with its current amount of coverage of arithmetic users
of EFLAGS it will be a significant improvement over the current use of
pushf/popf. It will also produce substantially faster code in most of
the common patterns.
This patch also removes all of the old lowering for EFLAGS copies, and
the hack that forced us to use a frame pointer when EFLAGS copies were
found anywhere in a function so that the dynamic stack adjustment wasn't
a problem. None of this is needed as we now lower all of these copies
directly in MI and without require stack adjustments.
Lots of thanks to Reid who came up with several aspects of this
approach, and Craig who helped me work out a couple of things tripping
me up while working on this.
Differential Revision: https://reviews.llvm.org/D45146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329657
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Vlad Tsyrklevich [Tue, 10 Apr 2018 01:31:01 +0000 (01:31 +0000)]
ShadowCallStack/x86_64: Ignore pseudo-machine instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329656
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Vitaly Buka [Tue, 10 Apr 2018 00:53:16 +0000 (00:53 +0000)]
Object: Don't mark alias unconditionally defined
Summary:
Can't remove EmitAssignment override as llvm/test/Object/X86/nm-bitcodeweak.test
expects this behavior.
Reviewers: pcc, espindola
Subscribers: mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D44596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329651
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Michael Zolotukhin [Tue, 10 Apr 2018 00:42:43 +0000 (00:42 +0000)]
Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading."
This reverts commit r329644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329650
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Hideki Saito [Tue, 10 Apr 2018 00:38:36 +0000 (00:38 +0000)]
Fix for the buildbot failure. Now-unused private field TTI deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329649
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Fangrui Song [Tue, 10 Apr 2018 00:12:28 +0000 (00:12 +0000)]
[CachePruning] Fix comment about ext4 per-directory file limit. NFC
There is a limit on number of subdirectories if dir_nlinks is not
enabled (31998), but per-directory number of files is not limited.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329648
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Alexandre Ganea [Tue, 10 Apr 2018 00:09:15 +0000 (00:09 +0000)]
Fix line endings (CR/LF -> LF) introduced by rL329613
reviewer: zturner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329646
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Hideki Saito [Mon, 9 Apr 2018 23:45:40 +0000 (23:45 +0000)]
[NFC][LV] Move InterleaveInfo from Legal to CostModel
Summary:
Another clean up, following D43208.
Interleaved memory access analysis/optimization has nothing to do with vectorization legality. It doesn't really belong there. On the other hand, cost model certainly has to know about it.
In principle, vectorization should proceed like Legality ==> Optimization ==> CostModel ==> CodeGen, and this change just does that,
by moving the interleaved access analysis/decision out of Legal, and run it just before CostModel object is created.
After this, I can move LoopVectorizationLegality and Hints/Requirements classes into it's own header file, making it shareable within Transform tree. I have the patch already but I don't want to mix with this change. Eventual goal is to move to Analysis tree, but I first need to move RecurrenceDescriptor/InductionDescriptor from Transform/Util/LoopUtil.* to Analysis.
Reviewers: rengolin, hfinkel, mkuper, dcaballe, sguggill, fhahn, aemerson
Reviewed By: rengolin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329645
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Michael Zolotukhin [Mon, 9 Apr 2018 23:37:37 +0000 (23:37 +0000)]
[PR16756] Use SSAUpdaterBulk in JumpThreading.
Summary:
SSAUpdater is a bottleneck in JumpThreading, and this patch improves the
situation by using SSAUpdaterBulk instead.
Compile time impact: no noticable changes on CTMark, a big improvement
on the test from PR16756.
Reviewers: dberlin, davide, MatzeB
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329644
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Michael Zolotukhin [Mon, 9 Apr 2018 23:37:20 +0000 (23:37 +0000)]
[PR16756] Add SSAUpdaterBulk.
Summary:
SSAUpdater is a bottleneck in a number of passes, and one of the reasons
is that it performs a lot of unnecessary computations (DT/IDF) over and
over again. This patch adds a new SSAUpdaterBulk that uses existing DT
and avoids recomputing IDF when possible.
Reviewers: dberlin, davide, MatzeB
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329643
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George Burgess IV [Mon, 9 Apr 2018 23:09:27 +0000 (23:09 +0000)]
[MemorySSA] remove cruft; NFC.
The caching walker used to hold its own caches, which made its `reset()`
function meaningful. Since caching has been moved out of it, there's no
reason to continue to have these cache-related methods.
Similarly, the EXPENSIVE_CHECKS block that's getting removed used to
rerun the query with caching disabled. Since that's how we always do
queries now, it's redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329638
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George Burgess IV [Mon, 9 Apr 2018 22:45:14 +0000 (22:45 +0000)]
[MemorySSA] Remove redundant assert; NFC
The `if (!Def && !Use) return nullptr;` right above this assert sort of
defeats the purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329632
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Simon Pilgrim [Mon, 9 Apr 2018 21:46:57 +0000 (21:46 +0000)]
[X86] Added missing AAD/AAM immediate schedule tests
Added some more TODOs for missing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329626
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Daniel Sanders [Mon, 9 Apr 2018 21:10:09 +0000 (21:10 +0000)]
[globalisel][legalizerinfo] Add support for the Lower action in getActionDefinitionsBuilder() and use it in AArch64.
Lower is slightly odd. It often doesn't change the type but the lowerings
do use the new type to decide what code to create. Treat it like a mutation
but provide convenience functions that re-use the existing type.
Re-uses the existing tests:
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
test/CodeGen/AArch64/GlobalISel//legalize-mul.mir
test/CodeGen/AArch64/GlobalISel//legalize-cmpxchg-with-success.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329623
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Matt Arsenault [Mon, 9 Apr 2018 21:04:30 +0000 (21:04 +0000)]
Fix printing of stack id in MachineFrameInfo
uint8_t is printed as a char, so it needs to be
casted to do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329622
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Zhaoshi Zheng [Mon, 9 Apr 2018 20:55:37 +0000 (20:55 +0000)]
[MemorySSAUpdater] Mark Phi users of a node being moved as non-optimize
Fix PR36484, as suggested:
<quote>
during moves, mark the direct users of the erased things that were phis as "not to be optimized"
<quote>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329621
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Konstantin Zhuravlyov [Mon, 9 Apr 2018 20:47:22 +0000 (20:47 +0000)]
AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header
1. Remove max_scratch_backing_memory_byte_size from kernel header
2. Make it a reserved field
3. Ignore it while parsing assembly for backwards compatibility
4. Bump up minor version of kernel header
Differential Revision: https://reviews.llvm.org/D45452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329620
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Craig Topper [Mon, 9 Apr 2018 20:37:14 +0000 (20:37 +0000)]
[X86] Don't use Lower512IntUnary to split bitcasts with v32i16/v64i8 types on targets without AVX512BW.
LowerIntUnary as its name says has an assert for integer types. But for the bitcast case one side might be an FP type.
Rather than making sure the function really works for fp types and renaming it. Just do really basic splitting directly. The LowerIntUnary has the advantage that it can peek through BUILD_VECTOR because every other call is during Lowering. But these calls are during legalization and will be followed by a DAG combine round.
Revert some change to LowerVectorIntUnary that were originally made just to make these two calls work even in pure integer cases.
This was found purely by compiling the avx512f-builtins.c test from clang so I've copied over the offending function from that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329616
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Alexandre Ganea [Mon, 9 Apr 2018 20:17:56 +0000 (20:17 +0000)]
[Debuginfo][COFF] Minimal serialization support for precompiled types records
This change adds support for the LF_PRECOMP and LF_ENDPRECOMP records required
to read/write Microsoft precompiled types .objs.
See https://en.wikipedia.org/wiki/Precompiled_header#Microsoft_Visual_C_and_C++
This also adds handling for the .debug$P section, which is actually a .debug$T
section in disguise, found only in precompiled .objs.
Differential Revision: https://reviews.llvm.org/D45283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329613
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Peter Collingbourne [Mon, 9 Apr 2018 19:59:57 +0000 (19:59 +0000)]
AArch64: Allow offsets to be folded into addresses with ELF.
This is a code size win in code that takes offseted addresses
frequently, such as C++ constructors that typically need to compute
an offseted address of a vtable. It reduces the size of Chromium for
Android's .text section by 46KB, or 56KB with ThinLTO (which exposes
more opportunities to use a direct access rather than a GOT access).
Because the addend range is limited in COFF and Mach-O, this is
enabled for ELF only.
Differential Revision: https://reviews.llvm.org/D45199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329611
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Alex Shlyapnikov [Mon, 9 Apr 2018 19:47:38 +0000 (19:47 +0000)]
Revert "AMDGPU: enable 128-bit for local addr space under an option"
This reverts commit r329591.
It breaks various bots:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/16516
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/17374
http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/15992
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt
http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/11251
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329610
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Mandeep Singh Grang [Mon, 9 Apr 2018 19:38:31 +0000 (19:38 +0000)]
[WebAssembly] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: sunfish, RKSimon
Reviewed By: sunfish
Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D44873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329607
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Craig Topper [Mon, 9 Apr 2018 19:17:38 +0000 (19:17 +0000)]
[X86] Remove GCCBuiltin name from pmuldq/pmuludq intrinsics so clang can custom lower to native IR. Update fast-isel intrinsic tests for clang's new codegen.
In somes cases fast-isel fails to remove the and/shifts and uses blends or conditional moves.
But once masking gets involved, fast-isel aborts on the mask portion and we DAG combine more thorougly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329604
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Alexey Bataev [Mon, 9 Apr 2018 19:02:34 +0000 (19:02 +0000)]
[SLP] Additional tests for reorder reuse vectorization, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329603
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Daniel Sanders [Mon, 9 Apr 2018 18:42:19 +0000 (18:42 +0000)]
Fix type mismatch between MachineMemOperand constructor and accessors. NFC
This allows MachineMemOperand::getSize()'s result to be fed directly into
MachineMemOperand::MachineMemOperand() without a narrowing type conversion
warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329602
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Erik Pilkington [Mon, 9 Apr 2018 18:33:01 +0000 (18:33 +0000)]
[demangler] Support for fold expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329601
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Erik Pilkington [Mon, 9 Apr 2018 18:32:25 +0000 (18:32 +0000)]
[demangler] Support for <data-member-prefix>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329600
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Erik Pilkington [Mon, 9 Apr 2018 18:31:50 +0000 (18:31 +0000)]
[demangler] Support for partially substituted sizeof....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329599
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Aditya Nandakumar [Mon, 9 Apr 2018 17:30:56 +0000 (17:30 +0000)]
[GISel] Refactor MachineIRBuilder to allow transformations while
building.
https://reviews.llvm.org/D45067
This change attempts to do two things:
1) It separates out the state that is stored in the
MachineIRBuilder(InsertionPt, MF, MRI, InsertFunction etc) into a
separate object called MachineIRBuilderState.
2) Add the ability to constant fold operations while building instructions
(optionally). MachineIRBuilder is now refactored into a MachineIRBuilderBase
which contains lots of non foldable build methods and their implementation.
Instructions which can be constant folded/transformed are now in a class
called FoldableInstructionBuilder which uses CRTP to use the implementation
of the derived class for buildBinaryOps. Additionally buildInstr in the derived
class can be used to implement other kinds of transformations.
Also because of separation of state, given a MachineIRBuilder in an API,
if one wishes to use another MachineIRBuilder, a new one can be
constructed from the state locally. For eg,
void doFoo(MachineIRBuilder &B) {
MyCustomBuilder CustomB(B.getState());
// Use CustomB for building.
}
reviewed by : aemerson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329596
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Craig Topper [Mon, 9 Apr 2018 17:07:40 +0000 (17:07 +0000)]
[X86] Revert the SLM part of r328914.
While it appears to be correct information based on Intel's optimization manual and Agner's data, it causes perf regressions on a couple of the benchmarks in our internal list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329593
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Fangrui Song [Mon, 9 Apr 2018 17:06:57 +0000 (17:06 +0000)]
[llvm-mca] Fix MCACommentConsumer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329592
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Marek Olsak [Mon, 9 Apr 2018 16:56:32 +0000 (16:56 +0000)]
AMDGPU: enable 128-bit for local addr space under an option
Author: Samuel Pitoiset
ds_read_b128 and ds_write_b128 have been recently enabled
under the amdgpu-ds128 option because the performance benefit
is unclear.
Though, using 128-bit loads/stores for the local address space
appears to introduce regressions in tessellation shaders. Not
sure what is broken, but as ds_read_b128/ds_write_b128 are not
enabled by default, just introduce a global option and enable
128-bit only if requested (until it's fixed/used correctly).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329591
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Andrea Di Biagio [Mon, 9 Apr 2018 16:39:52 +0000 (16:39 +0000)]
[llvm-mca] Add the ability to mark regions of code for analysis (PR36875)
This patch teaches llvm-mca how to parse code comments in search for special
"markers" used to select regions of code.
Example:
# LLVM-MCA-BEGIN My Code Region
....
# LLVM-MCA-END
The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an
AsmCommentConsumer) the parsing of code comments to search for begin/end code
region markers.
A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new
region of code. A comment starting with substring "LLVM-MCA-END" marks the end
of the last region.
This implementation doesn't allow regions to overlap. Each region can have a
optional description; internally, each region is identified by a range of source
code locations (SMLoc).
MCInst objects are added to a region R only if the source location for the
MCInst is in the range of locations specified by R.
By default, the tool allocates an implicit "Default" code region which contains
every source location. See new tests llvm-mca-marker-*.s for a few examples.
A new Backend object is created for every region. So, the analysis is conducted
on every parsed code region. The final report is the union of the reports
generated for every code region. Note that empty regions are skipped.
Special "[#] Code Region - ..." strings are used in the report to mark the
portion which is specific to a code region only. For example, see
llvm-mca-markers-5.s.
Differential Revision: https://reviews.llvm.org/D45433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329590
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Tom Stellard [Mon, 9 Apr 2018 16:09:13 +0000 (16:09 +0000)]
AMDGPU: Initialize GlobalISel passes
Summary:
This fixes AMDGPU GlobalISel test failures when enabling the AMDGPU
target without any other targets that use GlobalISel.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D45353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329588
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Simon Pilgrim [Mon, 9 Apr 2018 16:01:44 +0000 (16:01 +0000)]
[X86][SSE] Add floating point add/mul strict (ordered) vector.reduce tests (PR36732)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329587
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Simon Pilgrim [Mon, 9 Apr 2018 15:44:20 +0000 (15:44 +0000)]
Support generic expansion of ordered vector reduction (PR36732)
Without the fast math flags, the llvm.experimental.vector.reduce.fadd/fmul intrinsic expansions must be expanded in order.
This patch scalarizes the reduction, applying the accumulator at the start of the sequence: ((((Acc + Scl[0]) + Scl[1]) + Scl[2]) + ) ... + Scl[NumElts-1]
Differential Revision: https://reviews.llvm.org/D45366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329585
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Max Moroz [Mon, 9 Apr 2018 15:20:35 +0000 (15:20 +0000)]
[llvm-cov] Implement -ignore-filename-regex= option for excluding source files.
Summary:
The option is helpful for large projects where it's not feasible to specify sources which
user would like to see in the report. Instead, it allows to black-list specific sources via
regular expressions (e.g. now it's possible to skip all files that have "test" in its name).
This also partially fixes https://bugs.llvm.org/show_bug.cgi?id=34277
Reviewers: vsk, morehouse, liaoyuke
Reviewed By: vsk
Subscribers: kcc, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D43907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329581
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Zaara Syeda [Mon, 9 Apr 2018 14:50:02 +0000 (14:50 +0000)]
[MachineLICM] Re-enable hoisting of constant stores
This patch fixes an issue exposed on the SystemZ build bots when committing
https://reviews.llvm.org/rL327856. The hoisting was temporarily disabled with
an option. This patch now re-enables hoisting and checks that we only hoist a
store instruction when all its operands are either constant caller preserved
registers or immediates.
Differential Revision: https://reviews.llvm.org/D45286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329577
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Pavel Labath [Mon, 9 Apr 2018 14:38:53 +0000 (14:38 +0000)]
[CodeGen/AccelTable] Don't emit zero-CU name indexes
Summary:
If an input DICompileUnit is completely empty (e.g., the result of
running "clang -g" on an empty file), we don't bother emitting an empty
DWARF CU. When we do that, we must make sure we don't also emit a DWARF v5
name index, as DWARF specifies that each index must reference at least
one compilation unit.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329575
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Krasimir Georgiev [Mon, 9 Apr 2018 14:29:23 +0000 (14:29 +0000)]
[RuntimeDyld][PowerPC] Fix a newly added test in r329355
Summary: The bit widths are wrong.
Reviewers: bkramer, lhames, hans
Reviewed By: hans
Subscribers: hans, nemanjai, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D45361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329573
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Xin Tong [Mon, 9 Apr 2018 14:29:13 +0000 (14:29 +0000)]
[MergeICmp] Update debug msg.NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329572
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Hans Wennborg [Mon, 9 Apr 2018 13:53:41 +0000 (13:53 +0000)]
Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the timeline view."
This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g.
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251
> Also, update a few tests to minimize the diff in D45369.
> No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329569
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Simon Pilgrim [Mon, 9 Apr 2018 13:52:33 +0000 (13:52 +0000)]
[X86][MMX] Fix missing itinerary for PALIGNR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329568
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Simon Pilgrim [Mon, 9 Apr 2018 13:42:14 +0000 (13:42 +0000)]
[X86][MMX] Fix missing itinerary for MOVQ2DQ instruction format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329567
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Simon Pilgrim [Mon, 9 Apr 2018 13:27:47 +0000 (13:27 +0000)]
[X86][MMX] Fix missing itinerary for CVTPI2PS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329565
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Xin Tong [Mon, 9 Apr 2018 13:14:06 +0000 (13:14 +0000)]
[MergeICmp] Split blocks that do other work.
Summary:
We do not try to move the instructions and split the block till we
know the blocks can be split, i.e. BCE-cmp-insts can be separated from
non-BCE-cmp-insts.
Reviewers: davide, courbet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329564
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Dmitry Preobrazhensky [Mon, 9 Apr 2018 13:10:33 +0000 (13:10 +0000)]
[AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32
See bugs
36841: https://bugs.llvm.org/show_bug.cgi?id=36841
36842: https://bugs.llvm.org/show_bug.cgi?id=36842
Differential Revision: https://reviews.llvm.org/D45251
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329562
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Simon Pilgrim [Mon, 9 Apr 2018 13:02:07 +0000 (13:02 +0000)]
[X86][MMX] Fix flipped reg/mem typo in MMX_MISC_FUNC_ITINS
The RR/RM itineraries were the wrong way around
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329561
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Simon Pilgrim [Mon, 9 Apr 2018 10:45:53 +0000 (10:45 +0000)]
[X86][SSE] Fix f32 mul/div itinerary groups typo
The RM folded itineraries were incorrectly using the f64 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329556
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Pavel Labath [Mon, 9 Apr 2018 09:11:40 +0000 (09:11 +0000)]
Make the test case from r329552 more portable
- when tuning for SCE debugger (default for ps4 targets), we will not emit
the DW_AT_linkage_name, which this test needs. I explicitly set the
debugger tuning parameter to get the attribute always.
- darwin targets did not like the "section .text.startup" fragment of
the test. This is not actually needed for the test, so I remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329555
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Jonas Devlieghere [Mon, 9 Apr 2018 09:10:34 +0000 (09:10 +0000)]
[dsymutil] Remove trailing colon. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329554
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Jonas Devlieghere [Mon, 9 Apr 2018 09:09:59 +0000 (09:09 +0000)]
[dsymutil] Don't try to load Swift ASTs as objects.
With the threading refactoring, loading of object files happens before
checking whether we're dealing with a swift AST. While that's not an
issue per se, it causes a warning to be printed:
warning: /path/to/a.swiftmodule: The file was not recognized as a valid object file
note: while processing /path/to/a.swiftmodule
This suppresses the warning by checking for a Swift AST before
attempting to load is as an object file.
rdar://
39240444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329553
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Pavel Labath [Mon, 9 Apr 2018 08:41:57 +0000 (08:41 +0000)]
[CodeGen/AccelTable]: Don't emit accelerator entries for functions with no names
Summary:
We were emitting accelerator entries for functions with no name, which
is contrary to the DWARF v5 spec: "All other (i.e., *not*
DW_TAG_namespace) debugging information entries without a DW_AT_name
attribute are excluded." Besides that, a name table entry with an empty
string as a key is fairly useless.
We can sometimes end up with functions which have a DW_AT_linkage_name but no
DW_AT_name. One such example is the global-constructor-initialization functions,
which C++ compilers synthesize for each compilation unit with global
constructors.
A very strict reading of the DWARF v5 spec would suggest that we should not even
emit the accelerator entry for the linkage name in this case, but I don't think
we should go that far.
I found this when running the dwarf verifier over llvm codebase compiled
with DWARF v5 accelerator tables.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: vleschuk, clayborg, echristo, probinson, llvm-commits
Differential Revision: https://reviews.llvm.org/D45367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329552
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Sam Parker [Mon, 9 Apr 2018 08:16:11 +0000 (08:16 +0000)]
[DAGCombine] Improve ReduceLoad for SRL
Recommitting r329283, third time lucky...
If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.
Differential Revision: https://reviews.llvm.org/D41350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329551
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Craig Topper [Mon, 9 Apr 2018 06:15:09 +0000 (06:15 +0000)]
[X86] Merge some of the autoupgrade handling for masked intrinsics that just need to upgrade to an unmasked version plus a select. NFCI
These are were previously grouped in small groups of similarish intrinsics. But all the intrinsics have the same number of arguments and the same order. So we can move them all into a larger group for handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329549
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Max Kazantsev [Mon, 9 Apr 2018 06:01:22 +0000 (06:01 +0000)]
[IRCE] Relax restriction on collected range checks
In IRCE, we have a very old legacy check that works when we collect comparisons that we
treat as range checks. It ensures that the value against which the indvar is compared is
loop invariant and is also positive.
This latter condition remained there since the times when IRCE was only able to handle
signed latch comparison. As the optimization evolved, it now learned how to intersect
signed or unsigned ranges, and this logic has no reliance on the fact that the right border
of each range should be positive.
The old implementation of this non-negativity check was also naive enough and just looked
into ranges (while most of other IRCE logic tries to use power of SCEV implications), so this
check did not allow to deal with the most simple case that looks like follows:
int size; // not known non-negative
int length; //known non-negative;
i = 0;
if (size != 0) {
do {
range_check(i < size);
range_check(i < length);
++i;
} while (i < size)
}
In this case, even if from some dominating conditions IRCE could parse loop
structure, it could only remove the range check against `length` and simply
ignored the check against `size`.
In this patch we remove this obsolete check. It will allow IRCE to pick comparison
against `size` as a potential range check and then let Range Intersection logic
decide whether it is OK to eliminate it or not.
Differential Revision: https://reviews.llvm.org/D45362
Reviewed By: samparker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329547
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Hiroshi Inoue [Mon, 9 Apr 2018 04:37:53 +0000 (04:37 +0000)]
[NFC] fix trivial typos in comments and error message
"is is" -> "is", "are are" -> "are"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329546
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Dean Michael Berris [Mon, 9 Apr 2018 04:02:09 +0000 (04:02 +0000)]
[XRay][llvm+clang] Consolidate attribute list files
Summary:
This change consolidates the always/never lists that may be provided to
clang to externally control which functions should be XRay instrumented
by imbuing attributes. The files follow the same format as defined in
https://clang.llvm.org/docs/SanitizerSpecialCaseList.html for the
sanitizer blacklist.
We also deprecate the existing `-fxray-instrument-always=` and
`-fxray-instrument-never=` flags, in favour of `-fxray-attr-list=`.
This fixes http://llvm.org/PR34721.
Reviewers: echristo, vlad.tsyrklevich, eugenis
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D45357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329543
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Michael Zolotukhin [Mon, 9 Apr 2018 00:54:47 +0000 (00:54 +0000)]
Remove MachineLoopInfo dependency from AsmPrinter.
Summary:
Currently MachineLoopInfo is used in only two places:
1) for computing IsBasicBlockInsideInnermostLoop field of MCCodePaddingContext, and it is never used.
2) in emitBasicBlockLoopComments, which is called only if `isVerbose()` is true.
Despite that, we currently have a dependency on MachineLoopInfo, which makes
pass manager to compute it and MachineDominator Tree. This patch removes the
use (1) and makes the use (2) lazy, thus avoiding some redundant
recomputations.
Reviewers: opaparo, gadi.haber, rafael, craig.topper, zvi
Subscribers: rengolin, javed.absar, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D44812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329542
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Sanjay Patel [Sun, 8 Apr 2018 19:56:04 +0000 (19:56 +0000)]
[TargetSchedule] shrink interface for init(); NFCI
The TargetSchedModel is always initialized using the TargetSubtargetInfo's
MCSchedModel and TargetInstrInfo, so we don't need to extract those and
pass 3 parameters to init().
Differential Revision: https://reviews.llvm.org/D44789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329540
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Craig Topper [Sun, 8 Apr 2018 17:53:18 +0000 (17:53 +0000)]
[X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.
Summary:
Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops.
This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs.
The test changes are due to fixing a missing ZnAGU dependency on the memory form of setcc.
Reviewers: RKSimon, andreadb, GGanesh
Reviewed By: RKSimon
Subscribers: GGanesh, llvm-commits
Differential Revision: https://reviews.llvm.org/D45380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329539
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Craig Topper [Sun, 8 Apr 2018 17:53:15 +0000 (17:53 +0000)]
[X86][Znver1] Remove InstRWs for BLENDVPS/PD
Summary:
This removes the InstRWs for BLENDVPS/PD in favor of WriteFVarBlend. The latency listed was 3 cycles but WriteFVarBlend is defined as 1 cycle latency. The 1 cycle latency matches Agner Fog's data.
The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx"
Reviewers: RKSimon, GGanesh
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329538
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Jonas Devlieghere [Sun, 8 Apr 2018 17:35:17 +0000 (17:35 +0000)]
[dsymutil] Don't crash on empty CU
Add some additional checks so we don't crash on empty compile units.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329537
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