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Zachary Turner [Wed, 17 May 2017 15:49:45 +0000 (15:49 +0000)]
[BitVector] Add find_[first,last]_[set,unset]_in.
A lot of code is duplicated between the first_last and the
next / prev methods. All of this code can be shared if they
are implemented in terms of find_first_in(Begin, End) etc,
in which case find_first = find_first_in(0, Size) and find_next
is find_first_in(Prev+1, Size), with similar reductions for
the other methods.
Differential Revision: https://reviews.llvm.org/D33104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303269
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Sanjay Patel [Wed, 17 May 2017 14:21:19 +0000 (14:21 +0000)]
[InstCombine] add isCanonicalPredicate() helper function and use it; NFCI
There should be a slight efficiency improvement from handling icmp/fcmp with one matcher and reducing duplicated code.
The larger motivation is that there are questions about how predicate canonicalization is handled, and the refactoring
should make it easier if we want to change any of that behavior.
1. As noted in the code comment, we've chosen 3 of the 16 FCMP preds as not canonical. Why those 3? It goes back to
rL32751 from what I can tell, but I'm not sure if there's a justification for that rule.
2. We currently do not canonicalize integer select conditions. Should we use the same rule that applies to branches
for selects?
3. We currently do canonicalize some FP select conditions, and those rules would conflict with the rule shown here.
Should one or both be changed?
No-functional-change-intended, but adding tests anyway because there's no coverage for most of the predicates.
Differential Revision: https://reviews.llvm.org/D33247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303261
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Daniel Sanders [Wed, 17 May 2017 13:39:49 +0000 (13:39 +0000)]
[globalisel][tablegen] Import rules containing intrinsic_wo_chain.
Summary:
As of this patch, 1018 out of 3938 rules are currently imported.
Depends on D32275
Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: dberris, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D32278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303259
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Sanjay Patel [Wed, 17 May 2017 13:39:16 +0000 (13:39 +0000)]
[x86] Update tests in psubus.ll; NFC
Remove unnecessary memops to minimize tests.
Patch by Yulia Koval!
Differential Revision: https://reviews.llvm.org/D32643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303258
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Krzysztof Parzyszek [Wed, 17 May 2017 13:25:09 +0000 (13:25 +0000)]
[PPC] Properly update register save area offsets
The variables MinGPR/MinG8R were not updated properly when resetting the
offsets, which in the included testcase lead to saving the CR register
in the same location as R30.
This fixes another issue reported in PR26519.
Differential Revision: https://reviews.llvm.org/D33017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303257
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Igor Breger [Wed, 17 May 2017 12:48:08 +0000 (12:48 +0000)]
[GlobalISel][X86] Support add i64 in IA32.
Summary: support G_UADDE instruction selection.
Reviewers: zvi, guyblank
Reviewed By: guyblank
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D33096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303255
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Jonas Paulsson [Wed, 17 May 2017 12:46:26 +0000 (12:46 +0000)]
[SystemZ] Modelling of costs of divisions with a constant power of 2.
Such divisions will eventually be implemented with shifts which should
be reflected in the cost function.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303254
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Daniel Sanders [Wed, 17 May 2017 12:43:30 +0000 (12:43 +0000)]
[globalisel][tablegen] Require that all registers between instructions of a match are virtual.
Summary:
Without this, it's possible to encounter multiple defs for a register.
This is triggered by the current version of D32868 when applied to trunk.
Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls
Reviewed By: qcolombet
Subscribers: llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D32869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303253
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Diana Picus [Wed, 17 May 2017 12:42:52 +0000 (12:42 +0000)]
Reland r303247: [ARM] GlobalISel: Remove dead instruction selection code
It only failed on llvm-clang-x86_64-expensive-checks-win, probably
because the TableGen stuff hasn't been regenerated.
Requires a clean build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303252
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George Rimar [Wed, 17 May 2017 12:10:51 +0000 (12:10 +0000)]
[DWARF] - Cleanup relocations proccessing.
RelocAddrMap was a pair of <width, address>, where width is relocation size (4/8/x, x < 8),
and width field was never used in code.
Relocations proccessing loop had checks for width field. Does not look like DWARF parser
should do that. There is probably no much sense to validate relocations during proccessing
them in parser.
Patch removes relocation's width relative code from DWARFContext.
Differential revision: https://reviews.llvm.org/D33194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303251
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Diana Picus [Wed, 17 May 2017 11:56:07 +0000 (11:56 +0000)]
Revert "[ARM] GlobalISel: Remove dead instruction selection code"
This reverts commit r303247 because the tests are failing on some bots.
Sorry!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303249
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Diana Picus [Wed, 17 May 2017 11:39:26 +0000 (11:39 +0000)]
[ARM] GlobalISel: Remove dead instruction selection code
We can now generate code for selecting G_ADD, G_SUB and G_MUL. Remove
the hand-written versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303247
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Daniel Cederman [Wed, 17 May 2017 11:05:20 +0000 (11:05 +0000)]
[Sparc] Remove execute permissions from non-executable text files
Reviewers: jyknight, lero_chris, venkatra
Reviewed By: jyknight
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303245
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Diana Picus [Wed, 17 May 2017 09:25:08 +0000 (09:25 +0000)]
Fixup r303240: Use llvm::to_string instead of std::to_string
It turns out some of the buildbots don't have std::to_string around,
even in this day and age...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303243
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George Rimar [Wed, 17 May 2017 09:00:10 +0000 (09:00 +0000)]
[DebugInfo/DWARF] - Make comments to be in doxygen style. NFCi.
This changes "//" to "///" in llvm/DebugInfo/DWARF folder where appropriate
and also removes few trailing whitespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303241
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Diana Picus [Wed, 17 May 2017 08:57:28 +0000 (08:57 +0000)]
[GlobalISel][TableGen] Fix handling of default operands
When looping through a destination pattern's operands to decide how many
default operands we need to introduce, we used to count the "expanded"
number of operands. So if one default operand would be rendered as 2
values, we'd count it as 2 operands, when in fact it needs to count as
only 1 operand regardless of how many values it expands to.
This turns out to be a problem only in some very specific cases, e.g.
when we have one operand with multiple default values followed by more
operands with default values (see the new test). In such a situation
we'd stop looping before looking at all the operands, and then error out
assuming that we don't have enough default operands to make up the
shortfall.
At the moment this only affects ARM.
The patch removes the loop counting default operands entirely and
assumes that we'll have to introduce values for any default operand that
we find (i.e. we're assuming it cannot be given as a child at all). It
also extracts the code for adding renderers for default operands into a
helper method.
Differential Revision: https://reviews.llvm.org/D33031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303240
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Pavel Labath [Wed, 17 May 2017 08:47:28 +0000 (08:47 +0000)]
[RuntimeDyld] Fix debug section relocation (pr20457)
Summary:
Debug info sections, (or non-SHF_ALLOC sections in general) should be
linked as if their load address was zero to emulate the behavior of the
static linker.
This bug was discovered because it was breaking lldb expression evaluation on
linux.
Reviewers: lhames
Subscribers: aprantl, eugene, clayborg, lldb-commits, llvm-commits
Differential Revision: https://reviews.llvm.org/D32899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303239
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Jonas Paulsson [Wed, 17 May 2017 07:36:03 +0000 (07:36 +0000)]
Make sure -optimize-regalloc=false is used correctly by user.
Don't allow -optimize-regalloc=false with -regalloc given for anything other
than 'fast'. The other register allocators depend on the supporting passes
added by addOptimizedRegAlloc().
Reviewers: Quentin Colombet, Matthias Braun
https://reviews.llvm.org/D33181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303238
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Craig Topper [Wed, 17 May 2017 06:45:30 +0000 (06:45 +0000)]
[APInt] Use getWord to shorten some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303236
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Max Kazantsev [Wed, 17 May 2017 04:09:14 +0000 (04:09 +0000)]
[SCEV] Always sort AddRecExprs from different loops by dominance
Sorting of AddRecExprs by loop nesting does not make sense since we only invoke
the CompareSCEVComplexity for AddRecExprs that are used by one SCEV. This
guarantees that there is always a dominance relationship between them. This
patch removes the sorting by nesting which is a dead code in current usage of
this function.
Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D33228
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303235
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Max Kazantsev [Wed, 17 May 2017 03:58:42 +0000 (03:58 +0000)]
[SCEV][NFC] Replace redundant dyn_cast with cast in getAddExpr
Replace dyn_cast which is ensured by isa just one line above with cast.
Differential Revision: https://reviews.llvm.org/D33231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303234
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Gor Nishanov [Wed, 17 May 2017 03:09:22 +0000 (03:09 +0000)]
[coroutines] Handle spills before catchswitch
If we need to spill the result of the PHI instruction, we insert the spill after
all of the PHIs and EHPads, however, in a catchswitch block there is no
room to insert the spill. Make room by splitting away catchswitch into a separate
block.
Before the fix:
catch.dispatch:
%val = phi i32 [ 1, %if.then ], [ 2, %if.else ]
%switch = catchswitch within none [label %catch] unwind label %cleanuppad
After:
catch.dispatch:
%val = phi i32 [ 1, %if.then ], [ 2, %if.else ]
%tok = cleanuppad within none []
; spill goes here
cleanupret from %tok unwind label %catch.dispatch.switch
catch.dispatch.switch:
%switch = catchswitch within none [label %catch] unwind label %cleanuppad
https://reviews.llvm.org/D31846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303232
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Galina Kistanova [Wed, 17 May 2017 02:20:05 +0000 (02:20 +0000)]
Added LLVM_DUMP_METHOD attributes for MatchableInfo::dump(). Defined it only if dump is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303229
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Francis Visoiu Mistrih [Wed, 17 May 2017 01:07:53 +0000 (01:07 +0000)]
BitVector: add iterators for set bits
Differential revision: https://reviews.llvm.org/D32060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303227
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Eugene Zelenko [Tue, 16 May 2017 23:10:25 +0000 (23:10 +0000)]
[ADT] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303221
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Zachary Turner [Tue, 16 May 2017 22:59:34 +0000 (22:59 +0000)]
Fix for compilers with older CRT header libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303220
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Zachary Turner [Tue, 16 May 2017 22:50:32 +0000 (22:50 +0000)]
[Support] Ignore OutputDebugString exceptions in our crash recovery.
Since we use AddVectoredExceptionHandler, we get notified of
every exception that gets raised by a program. Sometimes these
are not necessarily errors though, and this can be especially
true when linking against a library that we have no control
over, and may raise an exception internally which it intends
to catch.
In particular, the Windows API OutputDebugString does exactly
this. It raises an exception inside of a __try / __except,
giving the debugger a chance to handle the exception to print
the message to the debug console.
But this doesn't interoperate nicely with our vectored exception
handler, which just sees another exception and decides that we
need to terminate the program.
Add a special case for this so that we ignore ODS exceptions
and continue normally.
Note that a better fix is to simply not use vectored exception
handlers and use SEH instead, but given that MinGW doesn't support
SEH, this is the only solution for MinGW.
Differential Revision: https://reviews.llvm.org/D33260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303219
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Davide Italiano [Tue, 16 May 2017 22:38:40 +0000 (22:38 +0000)]
[IR] Prefer use_empty() to !hasNUsesOrMore(1) for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303218
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Davide Italiano [Tue, 16 May 2017 22:27:06 +0000 (22:27 +0000)]
[NewGVN] Re-enable test now that the nondeterminism has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303217
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NAKAMURA Takumi [Tue, 16 May 2017 22:19:56 +0000 (22:19 +0000)]
llvm/test/Transforms/InstCombine/debuginfo-skip.ll REQUIRES +asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303216
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Adrian McCarthy [Tue, 16 May 2017 22:11:25 +0000 (22:11 +0000)]
Add test for FixedStreamArrayIterator::operator->
The operator-> implementation comes from iterator_facade_base, so it should
just work given that the iterator has a tested operator*. But r302257 showed
that required careful handling of for the const qualifier. This patch ensures
the fix in r302257 doesn't regress.
Differential Revision: https://reviews.llvm.org/D33249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303215
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Paul Robinson [Tue, 16 May 2017 21:53:30 +0000 (21:53 +0000)]
Update doxygen description of a method. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303214
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Sanjay Patel [Tue, 16 May 2017 21:51:04 +0000 (21:51 +0000)]
[InstSimplify] add folds for constant mask of value shifted by constant
We would eventually catch these via demanded bits and computing known bits in InstCombine,
but I think it's better to handle the simple cases as soon as possible as a matter of efficiency.
This fold allows further simplifications based on distributed ops transforms. eg:
%a = lshr i8 %x, 7
%b = or i8 %a, 2
%c = and i8 %b, 1
InstSimplify can directly fold this now:
%a = lshr i8 %x, 7
Differential Revision: https://reviews.llvm.org/D33221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303213
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Evgeny Stupachenko [Tue, 16 May 2017 21:44:59 +0000 (21:44 +0000)]
The patch exclude a case from zero check skip in
CTLZ idiom recognition (r303102).
Summary:
The following case:
i = 1;
if(n)
while (n >>= 1)
i++;
use(i);
Was converted to:
i = 1;
if(n)
i += builtin_ctlz(n >> 1, false);
use(i);
Which is not correct. The patch make it:
i = 1;
if(n)
i += builtin_ctlz(n >> 1, true);
use(i);
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303212
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Amara Emerson [Tue, 16 May 2017 21:29:22 +0000 (21:29 +0000)]
Re-commit r302678, fixing PR33053.
The issue was that the AArch64 TTI hook allowed unpacked integer cmp reductions
which didn't have a lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303211
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Easwaran Raman [Tue, 16 May 2017 21:18:09 +0000 (21:18 +0000)]
[Inliner] Do not mix callsite and callee hotness based updates.
Update threshold based on callee's hotness only when BFI is not available.
Otherwise use only callsite's hotness. This makes it easier to reason about
hotness related threshold updates.
Differential revision: https://reviews.llvm.org/D33157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303210
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Tim Shen [Tue, 16 May 2017 20:58:55 +0000 (20:58 +0000)]
[PPC] Add -ppc-asm-full-reg-names to atomic-2.ll. NFC.
Differential Revisions: https://reviews.llvm.org/D32763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303209
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Matthias Braun [Tue, 16 May 2017 20:53:27 +0000 (20:53 +0000)]
Test for r303197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303208
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Tim Shen [Tue, 16 May 2017 20:18:06 +0000 (20:18 +0000)]
[PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.
Summary:
This fixes pr32392.
The lowering pipeline is:
llvm.ppc.cfence in IR -> PPC::CFENCE8 in isel -> Actual instructions in
expandPostRAPseudo.
The reason why expandPostRAPseudo is chosen is because previous passes
are likely eliminating instructions like cmpw 3, 3 (early CSE) and bne-
7, .+4 (some branch pass(s)).
Differential Revision: https://reviews.llvm.org/D32763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303205
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Easwaran Raman [Tue, 16 May 2017 20:14:39 +0000 (20:14 +0000)]
Add hasProfileSummary and has{Sample|Instrumentation}Profile methods
ProfileSummaryInfo already checks whether the module has sample profile
in determining profile counts. This will also be useful in inliner to
clean up threshold updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303204
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Sanjay Patel [Tue, 16 May 2017 20:09:32 +0000 (20:09 +0000)]
[InstCombine] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303203
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Dmitry Mikulin [Tue, 16 May 2017 20:08:49 +0000 (20:08 +0000)]
In debug builds non-trivial amount of time is spent in InstCombine processing
@llvm.dbg.* calls in visitCallInst(). They can be safely ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303202
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Daniel Berlin [Tue, 16 May 2017 20:02:45 +0000 (20:02 +0000)]
NewGVN: Only do something in verifyStoreExpressions if assertions are enabled, to avoid unused code warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303201
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Daniel Berlin [Tue, 16 May 2017 19:58:47 +0000 (19:58 +0000)]
NewGVN: Fix PR 33051 by making sure we remove old store expressions
from the ExpressionToClass mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303200
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Reid Kleckner [Tue, 16 May 2017 19:55:03 +0000 (19:55 +0000)]
Revert "[X86] Replace slow LEA instructions in X86"
This reverts commit r303183, it broke various buildbots and introduced
sanitizer errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303199
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Nirav Dave [Tue, 16 May 2017 19:43:56 +0000 (19:43 +0000)]
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303198
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Matthias Braun [Tue, 16 May 2017 18:43:30 +0000 (18:43 +0000)]
ShrinkWrap: Add skipFunction() call
ShrinkWrapping is a performance optimization that can safely be skipped,
so we can add `if (!skipFunction()) return;`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303197
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Davide Italiano [Tue, 16 May 2017 18:41:46 +0000 (18:41 +0000)]
[MetadataLoader] Remove unused Vector. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303196
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Renato Golin [Tue, 16 May 2017 17:59:07 +0000 (17:59 +0000)]
Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove"
Revert "[ARM] Mark LEApcrel as not having side effects"
This reverts commit r303054 and r303053, as they broke the ARM
self-hosting buildbots:
http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/1550
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/1349
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/1845
Offline investigation on course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303193
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Stanislav Mekhanoshin [Tue, 16 May 2017 16:31:45 +0000 (16:31 +0000)]
[AMDGPU] Use GCNRPTracker dumper methods in scheduler
Differential Revision: https://reviews.llvm.org/D33244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303186
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Sanjay Patel [Tue, 16 May 2017 16:30:46 +0000 (16:30 +0000)]
[InstCombine] add motivational comment for tests; NFC
The referenced tests are derived from:
https://bugs.llvm.org/show_bug.cgi?id=32791
and:
https://reviews.llvm.org/D33172
The motivation for including negative tests may not be clear, so I'm adding an explanatory comment here.
In the post-commit thread for r303133:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20170515/453793.html
...it was mentioned that we don't want to add redundant tests. This is a valid point. But in this case,
we have a patch under review (D33172) that demonstrates that no existing regression tests are affected by
a proposed code change, but these are. Therefore, I think these tests have value not visible in any
existing regression tests regardless of whether they show a transform.
Differential Revision: https://reviews.llvm.org/D33242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303185
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Stanislav Mekhanoshin [Tue, 16 May 2017 16:11:26 +0000 (16:11 +0000)]
[AMDGPU] Cache live-ins and register pressure in scheduler
Using LIS can be quite expensive, so caching of calculated region
live-ins and pressure is implemented. It does two things:
1. Caches the info for the second stage when we schedule with
decreased target occupancy.
2. Tracks the basic block from top to bottom thus eliminating the
need to scan whole register file liveness at every region split
in the middle of the block.
The scheduling is now done in 3 stages instead of two, with the first
one being really a no-op and only used to collect scheduling regions
as sent by the scheduler driver.
There is no functional change to the current behavior, only compilation
speed is affected. In general computeBlockPressure() could be simplified
if we switch to backward RP tracker, because scheduler sends regions
within a block starting from the last upward. We could use a natural
order of upward tracker to seamlessly change between regions of the same
block, since live reg set of a previous tracked region would become a
live-out of the next region. That however requires fixing upward tracker
to properly account defs and uses of the same instruction as both are
contributing to the current pressure. When we converge on the produced
pressure we should be able to switch between them back and forth. In
addition, backward tracker is less expensive as it uses LIS in recede
less often than forward uses it in advance.
At the moment the worst known case compilation time has improved from 26
minutes to 8.5.
Differential Revision: https://reviews.llvm.org/D33117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303184
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Lama Saba [Tue, 16 May 2017 16:01:36 +0000 (16:01 +0000)]
[X86] Replace slow LEA instructions in X86
According to Intel's Optimization Reference Manual for SNB+:
" For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
dispatch via port 1:
- LEA that has all three source operands: base, index, and offset
- LEA that uses base and index registers where the base is EBP, RBP,or R13
- LEA that uses RIP relative addressing mode
- LEA that uses 16-bit addressing mode "
This patch currently handles the first 2 cases only.
Differential Revision: https://reviews.llvm.org/D32277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303183
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Matthew Simpson [Tue, 16 May 2017 15:50:30 +0000 (15:50 +0000)]
Revert 303174, 303176, and 303178
These commits are breaking the bots. Reverting to investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303182
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Nirav Dave [Tue, 16 May 2017 15:49:02 +0000 (15:49 +0000)]
[DAG] Prune deleted nodes in TokenFactor
Fix visitTokenFactor to correctly remove deleted nodes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303181
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Stanislav Mekhanoshin [Tue, 16 May 2017 15:43:52 +0000 (15:43 +0000)]
[AMDGPU] Turn register pressure estimation into forward tracker
This factors register pressure estimation mechanism from the
GCNSchedStrategy into the forward tracker to unify interface
with other strategies and expose it to other interested phases.
Differential Revision: https://reviews.llvm.org/D33105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303179
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Matthew Simpson [Tue, 16 May 2017 15:33:22 +0000 (15:33 +0000)]
Make test target-specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303178
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Matthew Simpson [Tue, 16 May 2017 15:20:27 +0000 (15:20 +0000)]
Fix test case to unbreak bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303176
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Matthew Simpson [Tue, 16 May 2017 14:43:55 +0000 (14:43 +0000)]
[LV] Avoid potentential division by zero when selecting IC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303174
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Gor Nishanov [Tue, 16 May 2017 14:11:39 +0000 (14:11 +0000)]
[coroutines] Handle unwind edge splitting
Summary:
RewritePHIs algorithm used in building of CoroFrame inserts a placeholder
```
%placeholder = phi [%val]
```
on every edge leading to a block starting with PHI node with multiple incoming edges,
so that if one of the incoming values was spilled and need to be reloaded, we have a
place to insert a reload. We use SplitEdge helper function to split the incoming edge.
SplitEdge function does not deal with unwind edges comping into a block with an EHPad.
This patch adds an ehAwareSplitEdge function that can correctly split the unwind edge.
For landing pads, we clone the landing pad into every edge block and replace the original
landing pad with a PHI collection the values from all incoming landing pads.
For WinEH pads, we keep the original EHPad in place and insert cleanuppad/cleapret in the
edge blocks.
Reviewers: majnemer, rnk
Reviewed By: majnemer
Subscribers: EricWF, llvm-commits
Differential Revision: https://reviews.llvm.org/D31845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303172
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George Rimar [Tue, 16 May 2017 14:05:45 +0000 (14:05 +0000)]
[DWARF] - Add RelocAddrEntry for cleanup. NFCi.
Was mentioned as possible cleanup during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303171
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Igor Breger [Tue, 16 May 2017 13:37:31 +0000 (13:37 +0000)]
[GlobalISel][X86] Split memop test file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303169
91177308-0d34-0410-b5e6-
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Chad Rosier [Tue, 16 May 2017 12:43:23 +0000 (12:43 +0000)]
Fix an improperly placed curly bracket. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303165
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George Rimar [Tue, 16 May 2017 12:30:59 +0000 (12:30 +0000)]
[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector.
Recommit of r303159 "[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector"
All places were shitched to use DWARFAddressRange now.
Suggested during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303163
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George Rimar [Tue, 16 May 2017 12:05:03 +0000 (12:05 +0000)]
Revert r303159 "[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector."
Something went wrong, it broke BB.
http://green.lab.llvm.org/green//job/clang-stage1-cmake-RA-incremental_build/38477/consoleFull#-
200034420049ba4694-19c4-4d7e-bec5-
911270d8a58c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303162
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George Rimar [Tue, 16 May 2017 11:54:19 +0000 (11:54 +0000)]
[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector.
Suggested during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303159
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James Henderson [Tue, 16 May 2017 09:43:21 +0000 (09:43 +0000)]
[LTO] Print time-passes information at conclusion of LTO codegen
The information collected when requested by -time-passes is only printed when
llvm_shutdown is called at the moment. This means that when linking against the LTO
library dynamically and using the C interface, it is not possible to see the timing
information, because llvm_shutdown cannot be called. This change modifies the LTO
code generation functions for both regular LTO and thin LTO to explicitly print and
reset the timing information.
I have tested that this works with our proprietary linker. However, as this relies
on a specific method of building and linking against the LTO library, I'm not sure
how or if this can be tested in the LLVM testsuite.
Reviewed by: mehdi_amini
Differential Revision: https://reviews.llvm.org/D32803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303152
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Max Kazantsev [Tue, 16 May 2017 07:27:06 +0000 (07:27 +0000)]
[SCEV] Fix sorting order for AddRecExprs
The existing sorting order in defined CompareSCEVComplexity sorts AddRecExprs
by loop depth, but does not pay attention to dominance of loops. This can
lead us to the following buggy situation:
for (...) { // loop1
op1 = {A,+,B}
}
for (...) { // loop2
op2 = {A,+,B}
S = add op1, op2
}
In this case there is no guarantee that in operand list of S the op2 comes
before op1 (loop depth is the same, so they will be sorted just
lexicographically), so we can incorrectly treat S as a recurrence of loop1,
which is wrong.
This patch changes the sorting logic so that it places the dominated recs
before the dominating recs. This ensures that when we pick the first recurrency
in the operands order, it will be the bottom-most in terms of domination tree.
The attached test set includes some tests that produce incorrect SCEV
estimations and crashes with oldlogic.
Reviewers: sanjoy, reames, apilipenko, anna
Reviewed By: sanjoy
Subscribers: llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D33121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303148
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Craig Topper [Tue, 16 May 2017 07:05:38 +0000 (07:05 +0000)]
[CorrelatedValuePropagation] Don't use -> to call a static method of ConstantRange. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303147
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Daniel Berlin [Tue, 16 May 2017 06:06:15 +0000 (06:06 +0000)]
NewGVN: Use StoreExpression StoredValue instead of looking it up again, since it was already looked up when it was created
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303144
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Daniel Berlin [Tue, 16 May 2017 06:06:12 +0000 (06:06 +0000)]
NewGVN: Formatting fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303143
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Davide Italiano [Tue, 16 May 2017 05:51:21 +0000 (05:51 +0000)]
Revert "[NewGVN] Replace predicate info leftovers."
It's breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303142
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Davide Italiano [Tue, 16 May 2017 05:23:23 +0000 (05:23 +0000)]
[NewGVN] Replace predicate info leftovers.
Fixes PR32945.
Differential Revision: https://reviews.llvm.org/D33226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303141
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NAKAMURA Takumi [Tue, 16 May 2017 04:01:23 +0000 (04:01 +0000)]
AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303137
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Peter Collingbourne [Tue, 16 May 2017 00:39:01 +0000 (00:39 +0000)]
IR: Give function GlobalValue::getRealLinkageName() a less misleading name: dropLLVMManglingEscape().
This function gives the wrong answer on some non-ELF platforms in some
cases. The function that does the right thing lives in Mangler.h. To try to
discourage people from using this function, give it a different name.
Differential Revision: https://reviews.llvm.org/D33162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303134
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Sanjay Patel [Mon, 15 May 2017 23:59:28 +0000 (23:59 +0000)]
[InstCombine] add tests for PR32791; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303133
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Francis Visoiu Mistrih [Mon, 15 May 2017 23:13:35 +0000 (23:13 +0000)]
[ShrinkWrapping] Handle restores on no-return paths
Shrink-wrapping uses post-dominators to find a restore point that
post-dominates all the uses of CSR / stack.
The way dominator trees are modeled in LLVM today is that unreachable
blocks are not present in a generic dominator tree, so, an unreachable node is
dominated by anything: include/llvm/Support/GenericDomTree.h:467.
Since for post-dominators, a no-return block is considered
"unreachable", calling findNearestCommonDominator on an unreachable node
A and a non-unreachable node B, will return B, which can be false. If we
find such node, we bail out since there is no good restore point
available.
rdar://problem/
30186931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303130
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Kostya Serebryany [Mon, 15 May 2017 22:55:00 +0000 (22:55 +0000)]
[libFuzzer] fix tests on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303128
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 15 May 2017 22:54:37 +0000 (22:54 +0000)]
[InstSimplify] add tests for unnecessary mask of shifted values; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303127
91177308-0d34-0410-b5e6-
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Xinliang David Li [Mon, 15 May 2017 22:43:52 +0000 (22:43 +0000)]
Fix memory leak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303126
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Kostya Serebryany [Mon, 15 May 2017 22:38:29 +0000 (22:38 +0000)]
[libFuzzer] improve the afl driver and it's tests. Make it possible to run individual inputs with afl driver
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303125
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Rui Ueyama [Mon, 15 May 2017 22:32:34 +0000 (22:32 +0000)]
Fix git command line in the Getting Started guide.
By default, git creates "llvm-project-
20170507" directory,
but we want to create "llvm-project" directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303124
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Justin Bogner [Mon, 15 May 2017 22:15:22 +0000 (22:15 +0000)]
Add "REQUIRES:" to the last few tests that use target specific intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303123
91177308-0d34-0410-b5e6-
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Davide Italiano [Mon, 15 May 2017 22:10:15 +0000 (22:10 +0000)]
[AMDGPU] Kill now unused phiInfoElementGetDebugLoc(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303122
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 15 May 2017 22:01:03 +0000 (22:01 +0000)]
[APInt] Simplify a for loop initialization based on the fact that 'n' is known to be 1 by an earlier 'if'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303120
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Eugene Zelenko [Mon, 15 May 2017 21:57:41 +0000 (21:57 +0000)]
[IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303119
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Tim Northover [Mon, 15 May 2017 21:51:38 +0000 (21:51 +0000)]
AArch64: use linker-private symbols for globals in MachO.
We don't use section-relative relocations on AArch64, so all symbols must be at
least visible to the linker (i.e. properly global or l_whatever, but not
L_whatever).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303118
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David Blaikie [Mon, 15 May 2017 21:34:01 +0000 (21:34 +0000)]
PR32288: Describe a bool parameter's DWARF location with a simple register
There's no need (& a bit incorrect) to mask off the high bits of the
register reference when describing a simple bool value.
Reviewers: aprantl
Differential Revision: https://reviews.llvm.org/D31062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303117
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Adam Nemet [Mon, 15 May 2017 21:15:01 +0000 (21:15 +0000)]
[SLP] Enable 64-bit wide vectorization on AArch64
ARM Neon has native support for half-sized vector registers (64 bits). This
is beneficial for example for 2D and 3D graphics. This patch adds the option
to lower MinVecRegSize from 128 via a TTI in the SLP Vectorizer.
*** Performance Analysis
This change was motivated by some internal benchmarks but it is also
beneficial on SPEC and the LLVM testsuite.
The results are with -O3 and PGO. A negative percentage is an improvement.
The testsuite was run with a sample size of 4.
** SPEC
* CFP2006/482.sphinx3 -3.34%
A pretty hot loop is SLP vectorized resulting in nice instruction reduction.
This used to be a +22% regression before rL299482.
* CFP2000/177.mesa -3.34%
* CINT2000/256.bzip2 +6.97%
My current plan is to extend the fix in rL299482 to i16 which brings the
regression down to +2.5%. There are also other problems with the codegen in
this loop so there is further room for improvement.
** LLVM testsuite
* SingleSource/Benchmarks/Misc/ReedSolomon -10.75%
There are multiple small SLP vectorizations outside the hot code. It's a bit
surprising that it adds up to 10%. Some of this may be code-layout noise.
* MultiSource/Benchmarks/VersaBench/beamformer/beamformer -8.40%
The opt-viewer screenshot can be seen at
F3218284. We start at a colder store
but the tree leads us into the hottest loop.
* MultiSource/Applications/lambda-0.1.3/lambda -2.68%
* MultiSource/Benchmarks/Bullet/bullet -2.18%
This is using 3D vectors.
* SingleSource/Benchmarks/Shootout-C++/Shootout-C++-lists +6.67%
Noise, binary is unchanged.
* MultiSource/Benchmarks/Ptrdist/anagram/anagram +4.90%
There is an additional SLP in the cold code. The test runs for ~1sec and
prints out over 2000 lines. This is most likely noise.
* MultiSource/Applications/aha/aha +1.63%
* MultiSource/Applications/JM/lencod/lencod +1.41%
* SingleSource/Benchmarks/Misc/richards_benchmark +1.15%
Differential Revision: https://reviews.llvm.org/D31965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303116
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Hans Wennborg [Mon, 15 May 2017 20:59:32 +0000 (20:59 +0000)]
Revert r302678 "[AArch64] Enable use of reduction intrinsics."
This caused PR33053.
Original commit message:
> The new experimental reduction intrinsics can now be used, so I'm enabling this
> for AArch64. We will need this for SVE anyway, so it makes sense to do this for
> NEON reductions as well.
>
> The existing code to match shufflevector patterns are replaced with a direct
> lowering of the reductions to AArch64-specific nodes. Tests updated with the
> new, simpler, representation.
>
> Differential Revision: https://reviews.llvm.org/D32247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303115
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Evgeniy Stepanov [Mon, 15 May 2017 20:43:42 +0000 (20:43 +0000)]
[asan] Better workaround for gold PR19002.
See the comment for more details. Test in a follow-up CFE commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303113
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Jan Sjodin [Mon, 15 May 2017 20:18:37 +0000 (20:18 +0000)]
Re-submit AMDGPUMachineCFGStructurizer.
Differential Revision: https://reviews.llvm.org/D23209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303111
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Tim Northover [Mon, 15 May 2017 19:42:15 +0000 (19:42 +0000)]
AArch64: diagnose unrecognized features in .cpu directive.
We were silently ignoring any features we couldn't match up, which led to
errors in an inline asm block missing the conventional "\n\t".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303108
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Davide Italiano [Mon, 15 May 2017 19:35:40 +0000 (19:35 +0000)]
[NewGVN] Remove unused setDefiningExpr(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303107
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 15 May 2017 19:27:53 +0000 (19:27 +0000)]
[InstCombine] restrict icmp fold with 2 sdiv exact operands (PR32949)
This is the InstCombine counterpart to D32954.
I added some comments about the code duplication in:
rL302436
Alive-based verification:
http://rise4fun.com/Alive/dPw
This is a 2nd fix for the problem reported in:
https://bugs.llvm.org/show_bug.cgi?id=32949
Differential Revision: https://reviews.llvm.org/D32970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303105
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Sanjay Patel [Mon, 15 May 2017 19:16:49 +0000 (19:16 +0000)]
[InstSimplify] restrict icmp fold with 2 sdiv exact operands (PR32949)
These folds were introduced with https://reviews.llvm.org/rL127064 as part of solving:
https://bugs.llvm.org/show_bug.cgi?id=9343
As shown here:
http://rise4fun.com/Alive/C8
...however, the sdiv exact case needs a stronger predicate.
I opted for duplicated code instead of adding another fallthrough because I think that's
easier to read (and edit in case we need/want to restrict/loosen the predicates any more).
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=32949
https://bugs.llvm.org/show_bug.cgi?id=32948
Differential Revision: https://reviews.llvm.org/D32954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303104
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Evgeny Stupachenko [Mon, 15 May 2017 19:08:56 +0000 (19:08 +0000)]
The patch adds CTLZ idiom recognition.
Summary:
The following loops should be recognized:
i = 0;
while (n) {
n = n >> 1;
i++;
body();
}
use(i);
And replaced with builtin_ctlz(n) if body() is empty or
for CPUs that have CTLZ instruction converted to countable:
for (j = 0; j < builtin_ctlz(n); j++) {
n = n >> 1;
i++;
body();
}
use(builtin_ctlz(n));
Reviewers: rengolin, joerg
Differential Revision: http://reviews.llvm.org/D32605
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303102
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Davide Italiano [Mon, 15 May 2017 18:50:53 +0000 (18:50 +0000)]
[NewGVN] Fix verification of MemoryPhis in verifyMemoryCongruency().
verifyMemoryCongruency() filters out trivially dead MemoryDef(s),
as we find them immediately dead, before moving from TOP to a new
congruence class.
This fixes the same problem for PHI(s) skipping MemoryPhis if all
the operands are dead.
Differential Revision: https://reviews.llvm.org/D33044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303100
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Geoff Berry [Mon, 15 May 2017 18:50:22 +0000 (18:50 +0000)]
[AArch64][Falkor] Fix sched details for FMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303099
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Jan Sjodin [Mon, 15 May 2017 18:39:47 +0000 (18:39 +0000)]
Revert 303091.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303098
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