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Jonas Devlieghere [Sun, 11 Nov 2018 01:46:03 +0000 (01:46 +0000)]
[Support] Make error banner optional in logAllUnhandledErrors
In a lot of places an empty string was passed as the ErrorBanner to
logAllUnhandledErrors. This patch makes that argument optional to
simplify the call sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346604
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Craig Topper [Sun, 11 Nov 2018 01:40:04 +0000 (01:40 +0000)]
[X86] Replace calls to getOnesVector/getZeroVector with getConstant.
getConstant will create a BUILD_VECTOR for us and use a legal type if necessary. So just create the simple node and let BUILD_VECTOR legalization do the canonicalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346603
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Jonas Devlieghere [Sun, 11 Nov 2018 01:24:02 +0000 (01:24 +0000)]
[llvm-cxxdump] Use error reporting helpers from support
This patch makes llvm-cxxdump use the error reporting helpers from
Support/WithColor.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346602
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Craig Topper [Sat, 10 Nov 2018 23:46:03 +0000 (23:46 +0000)]
[DAGCombiner] Make tryToFoldExtendOfConstant return an SDValue instead of an SDNode*. NFC
Removes the need to call getNode internally and to recreate an SDValue after the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346600
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Sanjay Patel [Sat, 10 Nov 2018 20:29:25 +0000 (20:29 +0000)]
[InstCombine] simplify code for merging stores; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346596
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Sanjay Patel [Sat, 10 Nov 2018 20:05:31 +0000 (20:05 +0000)]
[x86] allow vector load narrowing with multi-use values
This is a long-awaited follow-up suggested in D33578. Since then, we've picked up even more
opportunities for vector narrowing from changes like D53784, so there are a lot of test diffs.
Apart from 2-3 strange cases, these are all wins.
I've structured this to be no-functional-change-intended for any target except for x86
because I couldn't tell if AArch64, ARM, and AMDGPU would improve or not. All of those
targets have existing regression tests (4, 4, 10 files respectively) that would be
affected. Also, Hexagon overrides the shouldReduceLoadWidth() hook, but doesn't show
any regression test diffs. The trade-off is deciding if an extra vector load is better
than a single wide load + extract_subvector.
For x86, this is almost always better (on paper at least) because we often can fold
loads into subsequent ops and not increase the official instruction count. There's also
some unknown -- but potentially large -- benefit from using narrower vector ops if wide
ops are implemented with multiple uops and/or frequency throttling is avoided.
Differential Revision: https://reviews.llvm.org/D54073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346595
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Sanjay Patel [Sat, 10 Nov 2018 18:51:10 +0000 (18:51 +0000)]
[InstCombine] auto-generate full checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346594
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David Carlier [Sat, 10 Nov 2018 18:47:00 +0000 (18:47 +0000)]
Fix DragonFlyBSD linkage issue.
environ global failed on LTO linkage step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346593
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Benjamin Kramer [Sat, 10 Nov 2018 18:11:11 +0000 (18:11 +0000)]
[X86] Remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346592
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Craig Topper [Sat, 10 Nov 2018 17:44:28 +0000 (17:44 +0000)]
[X86] Remove apparently unneeded code from combineVSZext.
No lit tests fail with this code removed.
This is a pre-commit for D54346.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346590
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Simon Pilgrim [Sat, 10 Nov 2018 17:37:52 +0000 (17:37 +0000)]
[CostModel][X86] SK_ExtractSubvector costs must only be tested for vector types (PR39615)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346589
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Philip Reames [Sat, 10 Nov 2018 16:08:10 +0000 (16:08 +0000)]
[GC] Rename a header for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346588
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Roman Lebedev [Sat, 10 Nov 2018 14:31:43 +0000 (14:31 +0000)]
[X86][BdVer2] Fix loads/stores throughput for Piledriver (PR39465)
There are two AGU units, and per 1cy, there can be either two loads,
or a load and a store; but not two stores, or two loads and a store.
Additionally, loads shouldn't affect the store scheduler and vice versa.
(but *should* affect the PdEX scheduler.)
Required rL346545.
Fixes https://bugs.llvm.org/show_bug.cgi?id=39465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346587
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Roman Lebedev [Sat, 10 Nov 2018 10:56:58 +0000 (10:56 +0000)]
[NFC][MCA][BdVer2] Add bdver2 runline into register-file-statistics.s test
Missed this one by accident when adding
the initial version in rL345463 / rL345462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346585
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Eugene Leviant [Sat, 10 Nov 2018 08:31:21 +0000 (08:31 +0000)]
[ThinLTO] Internalize readonly globals
This patch allows internalising globals if all accesses to them
(from live functions) are from non-volatile load instructions
Differential revision: https://reviews.llvm.org/D49362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346584
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Craig Topper [Sat, 10 Nov 2018 06:04:33 +0000 (06:04 +0000)]
[X86] Use a MOVSX instruction instead of a MOVZX instruction in isel for an any_extend of the remainder from an 8-bit sdivrem.
The sdivrem will emit its own MOVSX to move %ah to the low byte of a register. By using a MOVSX for an any_extend this allows a post-isel peephole to merge them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346581
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Craig Topper [Sat, 10 Nov 2018 06:04:09 +0000 (06:04 +0000)]
[X86] Add a test case to show scalarized vector srem to demonstrate unnecessary instructions. NFC
After the division %ah is being sign extended to move it to lower byte of a register while avoiding a partial register read. We then zero extend the low byte to the full 32 bit register. But we don't use any of the zero extended bits. In the DAG the zero extend was really an any_extend so the sign extend should have been enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346580
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David Carlier [Sat, 10 Nov 2018 01:01:03 +0000 (01:01 +0000)]
Fix DragonFlyBSD build
Reviewers: rnk, thakis
Reviewed By: krytarowski
Differential Revision: https://reviews.llvm.org/D54363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346577
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Matthias Braun [Sat, 10 Nov 2018 00:36:27 +0000 (00:36 +0000)]
RegAllocFast: Further cleanups; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346576
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Matthias Braun [Sat, 10 Nov 2018 00:34:09 +0000 (00:34 +0000)]
test/CodeGen/X86: Relax test case
No need to hardcode register or expecting totally unnecessary spills
from the allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346575
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Craig Topper [Sat, 10 Nov 2018 00:26:42 +0000 (00:26 +0000)]
[X86] In LowerHorizontalByteSum, emit vector_shuffle nodes instead of directly using X86ISD::UNPCKL/X86ISD::UNPCKH.
This gives shuffle lowering the freedom to use zero_extend_vector_inreg for the unpckl shuffle. Shuffle combining usually makes this swap later, but not when AVX512 is enabled it seems.
While there also use DAG.getConstant to create a 0 vector instead of using the helper the forces a specific BUILD_VECTOR. I don't think that helper is usually needed. We're basically free to create a constant build_vector anytime and it will be legalized on its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346574
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Thomas Lively [Sat, 10 Nov 2018 00:11:14 +0000 (00:11 +0000)]
[WebAssembly] Update bleeding-edge cpu features
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D54362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346570
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Philip Reames [Fri, 9 Nov 2018 23:56:21 +0000 (23:56 +0000)]
[GC] Simplify linking of GC builtin GC strategies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346569
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Eli Friedman [Fri, 9 Nov 2018 23:33:30 +0000 (23:33 +0000)]
[ARM64] [Windows] Handle funclets
This patch adds support for funclets in frame lowering and ISel
lowering. Together with D50288 and D50166, it enables C++ exception
handling.
Patch by Sanjin Sijaric, with some fixes by me.
Differential Revision: https://reviews.llvm.org/D51524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346568
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Dylan McKay [Fri, 9 Nov 2018 23:17:59 +0000 (23:17 +0000)]
[AVR] Reorder the CHECK lines in directmem.ll to match current trunk
In r346432 ("[DAGCombine] Improve alias analysis for chain of independent stores"),
the order of ldi/sts blocks changed.
The new IR is equivalent to the old IR.
This patch updates the test to fix the test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346565
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Craig Topper [Fri, 9 Nov 2018 23:11:30 +0000 (23:11 +0000)]
[SelectionDAG] Fix a -Wparentheses warning from gcc in an assert. NFC
gcc wants parentheses around the logical OR since there is a logical AND for the string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346564
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Eli Friedman [Fri, 9 Nov 2018 23:09:17 +0000 (23:09 +0000)]
[ARM] Add MemOperand to LDRcp to enable DCE.
LDRcp should be deleted when the dest register is dead in register
coalescing. Without MemOp, dead LDRcp will cause dead constant pool
value which references to non-existing label.
Patch by Yin Ma.
Differential Revision: https://reviews.llvm.org/D54173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346563
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Eli Friedman [Fri, 9 Nov 2018 22:35:26 +0000 (22:35 +0000)]
[JumpThreading] Fix exponential time algorithm computing known values.
ComputeValueKnownInPredecessors has a "visited" set to prevent infinite
loops, since a value can be visited more than once. However, the
implementation didn't prevent the algorithm from taking exponential
time. Instead of removing elements from the RecursionSet one at a time,
we should keep around the whole set until
ComputeValueKnownInPredecessors finishes, then discard it.
The testcase is synthetic because I was having trouble effectively
reducing the original. But it's basically the same idea.
Instead of failing, we could theoretically cache the result instead.
But I don't think it would help substantially in practice.
Differential Revision: https://reviews.llvm.org/D54239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346562
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Thomas Lively [Fri, 9 Nov 2018 22:05:51 +0000 (22:05 +0000)]
Revert "Exclude wasm target from Windows packaging due to PR39448"
Summary:
This reverts r346122 now that the failing tests have been
disabled. Depends on D54353.
Reviewers: aheejin, dschuff
Subscribers: fedor.sergeev, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346559
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Thomas Lively [Fri, 9 Nov 2018 22:04:37 +0000 (22:04 +0000)]
[WebAssembly] Disable custom NaN payload tests
Summary:
These tests fail on 32-bit builds because NaN payload bits in floating point
immediates are not necessarily preserved through compilation. This is because
the MC layer uses native doubles to store these values. The tests will be
reenabled once this problem has been fixed or deleted if we decide we don't care
about lowering payload bits.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346558
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Craig Topper [Fri, 9 Nov 2018 20:09:53 +0000 (20:09 +0000)]
[X86] Move the promotion of v16i16->v16i8 for avx512f but not avx512bw from lowering to isel. Change to use vpmovzx instead of vpmovsx.
With avx512f but not avx512bw we need to extend to v16i32 then truncate that to to v16i8. Previously we emitted both nodes during lowering, but I'm trying to switch to using target independent nodes and with that switched the extend+truncate wou
This patch changes the implementation to what will be necessary with that patch which helps minimize test diffs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346552
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James Y Knight [Fri, 9 Nov 2018 19:45:13 +0000 (19:45 +0000)]
Branch/tag all projects with a single commit in release-tagging script.
This change updates the release script to use svnmucc to create all
the branches with one commit.
This will ensure that the git tag won't bounce around if the git
migration runs in-between separate commits creating a branch.
Additionally, update the list of projects to include all of the
projects in the monorepo, plus test-suite.
Differential Revision: https://reviews.llvm.org/D53467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346550
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Bryan Chan [Fri, 9 Nov 2018 19:32:08 +0000 (19:32 +0000)]
[AArch64] Support HiSilicon's TSV110 processor
Reviewers: t.p.northover, SjoerdMeijer, kristof.beyls
Reviewed By: kristof.beyls
Subscribers: olista01, javed.absar, kristof.beyls, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346546
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Andrea Di Biagio [Fri, 9 Nov 2018 19:30:20 +0000 (19:30 +0000)]
[llvm-mca] Account for buffered resources when analyzing "Super" resources.
This was noticed when working on PR3946.
By construction, a group cannot be used as a "Super" resource. That constraint
is enforced by method `SubtargetEmitter::ExpandProcResource()`.
A Super resource S can be part of a group G. However, method
`SubtargetEmitter::ExpandProcResource()` would not update the number of
consumed resource cycles in G based on S.
In practice, this is perfectly fine because the resource usage is correctly
computed for processor resource units. However, llvm-mca should still check if G
is a buffered resource.
Before this patch, llvm-mca didn't correctly check if S was part of a group that
defines a buffer. So, the instruction descriptor was not correctly set.
For now, the semantic change introduced by this patch doesn't affect any of the
upstream scheduling models. However, it will allow to make some progress on PR3946.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346545
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Nico Weber [Fri, 9 Nov 2018 19:28:50 +0000 (19:28 +0000)]
[MS demangler] Use a slightly shorter unmangling for mangled strings.
Before: const wchar_t * {L"%"}
Now: L"%"
See also PR39593.
Differential Revision: https://reviews.llvm.org/D54294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346544
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Fangrui Song [Fri, 9 Nov 2018 19:24:48 +0000 (19:24 +0000)]
[Hexagon] Fix some -Wunused-function with LLVM_DUMP_METHOD and -Wunused-variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346543
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Ulrich Weigand [Fri, 9 Nov 2018 19:16:21 +0000 (19:16 +0000)]
[SystemZ] Add a couple of missing tests
A few fp128 tests were omitted from test/CodeGen/SystemZ/fp-round-01.ll
since in early days, LLVM couldn't handle implicitly generated library
calls to functions with long double arguments on SystemZ.
This deficiency was actually long since fixed, but those tests are
still missing. This patch adds the missing tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346541
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Paul Robinson [Fri, 9 Nov 2018 19:06:09 +0000 (19:06 +0000)]
[DWARFv5] Emit normal type units in .debug_info comdats.
Differential Revision: https://reviews.llvm.org/D54282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346540
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Craig Topper [Fri, 9 Nov 2018 19:05:51 +0000 (19:05 +0000)]
[X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.
This makes X86ISD::VSEXT more similar to ISD::SIGN_EXTEND and ISD::ZERO_EXTEND.
I'm hoping to replace X86ISD::VSEXT/VZEXT with target independent nodes. Making the target specific nodes similar to the target independent nodes helps minimize test diffs in that patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346539
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Simon Pilgrim [Fri, 9 Nov 2018 19:04:27 +0000 (19:04 +0000)]
[CostModel][X86] SK_ExtractSubvector is free if the subvector is at the start of the source vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346538
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Jordan Rupprecht [Fri, 9 Nov 2018 18:54:27 +0000 (18:54 +0000)]
[Hexagon] Fix unused variable warning in release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346537
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Fangrui Song [Fri, 9 Nov 2018 18:32:20 +0000 (18:32 +0000)]
[WebAssembly] Hotfix of WebAssemblyInstructionTableSize after rL346465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346535
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Simon Pilgrim [Fri, 9 Nov 2018 18:30:59 +0000 (18:30 +0000)]
[TTI] Flip vector types in getShuffleCost SK_ExtractSubvector call
For SK_ExtractSubvector, the default 'Ty' type is the source operand type and 'SubTy' is the destination subvector type
I got this the wrong way around when I added rL346510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346534
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Stanislav Mekhanoshin [Fri, 9 Nov 2018 18:23:39 +0000 (18:23 +0000)]
[AMDGPU] Cleanup optimize-if-exec-masking.mir test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346533
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Brendon Cahoon [Fri, 9 Nov 2018 18:16:24 +0000 (18:16 +0000)]
[Hexagon] Implement noreturn optimization
Eliminate the stack frame in functions with the noreturn nounwind
attributes, and when the noreturn-stack-elim target feature is
enabled. This reduces the code and stack space needed for noreturn
functions.
Differential Revision: https://reviews.llvm.org/D54210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346532
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Greg Clayton [Fri, 9 Nov 2018 18:10:02 +0000 (18:10 +0000)]
Add total function byte size and inline function byte size to "llvm-dwarfdump --statistics"
Differential Revision: https://reviews.llvm.org/D54217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346531
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Craig Topper [Fri, 9 Nov 2018 18:04:34 +0000 (18:04 +0000)]
[DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars
It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input.
I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used.
Differential Revision: https://reviews.llvm.org/D54283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346530
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Jordan Rupprecht [Fri, 9 Nov 2018 18:03:21 +0000 (18:03 +0000)]
[llvm-strings] Fix whitespaces to match strings output.
Summary:
The current implementation prepends a space on every line, making it difficult to compare against GNU strings.
The space appears to have come from handling --radix in rL292707. The space is for making sure there's a space between the radix and the value; however the space is still emitted even when there is no radix. This change fixes that so the space is only emitted when there is a radix.
Reviewers: jhenderson
Reviewed By: jhenderson
Subscribers: llvm-commits, compnerd
Differential Revision: https://reviews.llvm.org/D54238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346529
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Stanislav Mekhanoshin [Fri, 9 Nov 2018 17:58:59 +0000 (17:58 +0000)]
[AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
This only covers AMDGPU BE, hopefully all occurrences.
Differential Revision: https://reviews.llvm.org/D54235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346528
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Krzysztof Parzyszek [Fri, 9 Nov 2018 17:31:22 +0000 (17:31 +0000)]
[Hexagon] Place globals with explicit .sdata section in small data
Both -fPIC and -G0 disable placement of globals in small data section,
but if a global has an explicit section assigmnent placing it in small
data, it should go there anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346523
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Serge Guelton [Fri, 9 Nov 2018 17:19:45 +0000 (17:19 +0000)]
Type safe version of MachinePassRegistry
Previous version used type erasure through a `void* (*)()` pointer,
which triggered gcc warning and implied a lot of reinterpret_cast.
This version should make it harder to hit ourselves in the foot.
Differential revision: https://reviews.llvm.org/D54203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346522
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Philip Reames [Fri, 9 Nov 2018 17:09:16 +0000 (17:09 +0000)]
[docs][statepoints] Reformulate open issues list
Some have been partially resolved, so update that. And restructure to make it easie to find and search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346518
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Fangrui Song [Fri, 9 Nov 2018 16:45:37 +0000 (16:45 +0000)]
Fix -Wsign-compare warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346515
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Max Moroz [Fri, 9 Nov 2018 16:44:36 +0000 (16:44 +0000)]
[llvm-cov] Remove "default:" label in the switch covering all enum values.
Summary:
Fixing the build breakage:
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/27309
Reviewers: vsk, allevato, Dor1s
Reviewed By: Dor1s
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346514
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Philip Reames [Fri, 9 Nov 2018 16:40:34 +0000 (16:40 +0000)]
[docs][statepoint] Expand a bit on problems with mixing references and raw pointers since it keeps coming up in discussions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346513
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Zaara Syeda [Fri, 9 Nov 2018 16:36:24 +0000 (16:36 +0000)]
[Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.
Differential Revision: https://reviews.llvm.org/D39386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346512
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Simon Pilgrim [Fri, 9 Nov 2018 16:28:19 +0000 (16:28 +0000)]
[CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR39368)
Add ShuffleVectorInst::isExtractSubvectorMask helper to match shuffle masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346510
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Philip Reames [Fri, 9 Nov 2018 16:27:04 +0000 (16:27 +0000)]
[docs][statepoint] tweak a title
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346509
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Alexey Bataev [Fri, 9 Nov 2018 16:22:35 +0000 (16:22 +0000)]
Revert "[DEBUGINFO, NVPTX]DO not emit ',debug' option if no debug info or only debug directives are requested."
This reverts commit r345972. Need to update the description + possibly
to update the patch itself after discussion with Eric Christofer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346508
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Max Moroz [Fri, 9 Nov 2018 16:10:44 +0000 (16:10 +0000)]
[llvm-cov] Add lcov tracefile export format.
Summary:
lcov tracefiles are used by various coverage reporting tools and build
systems (e.g., Bazel). It is a simple text-based format to parse and
more convenient to use than the JSON export format, which needs
additional processing to map regions/segments back to line numbers.
It's a little unfortunate that "text" format is now overloaded to refer
specifically to JSON for export, but I wanted to avoid making any
breaking changes to the UI of the llvm-cov tool at this time.
Patch by Tony Allevato (@allevato).
Reviewers: Dor1s, vsk
Reviewed By: Dor1s, vsk
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D54266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346506
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Jonas Paulsson [Fri, 9 Nov 2018 15:44:28 +0000 (15:44 +0000)]
[SystemZ] Avoid inserting same value after replication
A minor improvement of buildVector() that skips creating an
INSERT_VECTOR_ELT for a Value which has already been used for the
REPLICATE.
Review: Ulrich Weigand
https://reviews.llvm.org/D54315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346504
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Nicolai Haehnle [Fri, 9 Nov 2018 15:13:12 +0000 (15:13 +0000)]
AMDGPU: Add testcase to demonstrate a condition with pre-existing waitcnt
Relevant for https://reviews.llvm.org/D54226.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346501
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Sam McCall [Fri, 9 Nov 2018 15:11:34 +0000 (15:11 +0000)]
Revert "[VFS] Add "expand tilde" argument to getRealPath."
This reverts commit r346453.
This is a complex change to a widely-used interface, and was not reviewed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346500
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Sam Parker [Fri, 9 Nov 2018 15:06:33 +0000 (15:06 +0000)]
[ARM] Don't promote i1 types in ARM CGP
Now that we have mixed type sizes, i1 values need to be explicitly
handled as we want to avoid promoting these values.
Differential Revision: https://reviews.llvm.org/D54308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346499
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Sanjay Patel [Fri, 9 Nov 2018 14:54:58 +0000 (14:54 +0000)]
[x86] try to form broadcast before widening shuffle elements
I noticed that we weren't generating broadcasts as much I thought we would with
D54271, and this is part of the problem.
Widening the shuffle elements means adding bitcasts and hiding the relationship
between a splatted scalar and the vector. If we can form a broadcast, do that
before going through the rest of the shuffle lowering because broadcasts should
be cheap and can often be load-folded.
Differential Revision: https://reviews.llvm.org/D54280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346498
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Alex Bradbury [Fri, 9 Nov 2018 14:47:36 +0000 (14:47 +0000)]
[RISCV] Avoid unnecessary XOR for seteq/setne 0
Differential Revision: https://reviews.llvm.org/D53492
Patch by James Clarke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346497
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Alex Bradbury [Fri, 9 Nov 2018 14:35:44 +0000 (14:35 +0000)]
[RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
The DAGCombiner changes led to a different schedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346496
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Petar Avramovic [Fri, 9 Nov 2018 14:21:16 +0000 (14:21 +0000)]
[MIPS GlobalISel] narrowScalar G_CONSTANT
Legalize s64 G_CONSTANT using narrowScalar on MIPS 32.
Differential Revision: https://reviews.llvm.org/D54255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346495
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Krzysztof Parzyszek [Fri, 9 Nov 2018 14:17:27 +0000 (14:17 +0000)]
[Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346494
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Clement Courbet [Fri, 9 Nov 2018 14:08:29 +0000 (14:08 +0000)]
[llvm-exegesis] Fix unit tests on PowerPC/AArch64.
We were comparing char*s and not contents. Introduced in rL346489.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346493
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Florian Hahn [Fri, 9 Nov 2018 13:28:58 +0000 (13:28 +0000)]
Revert r346483: [CallSiteSplitting] Only record conditions up to the IDom(call site).
This cause a failure with EXPENSIVE_CHECKS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346492
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Simon Pilgrim [Fri, 9 Nov 2018 13:19:03 +0000 (13:19 +0000)]
[X86] Add Subtarget to more lowerVectorShuffle functions. NFCI.
This will be necessary for an update to D54267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346490
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Clement Courbet [Fri, 9 Nov 2018 13:15:32 +0000 (13:15 +0000)]
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
Summary:
This simplifies the code and moves everything to tablegen for consistency. This
also prepares the ground for adding issue counters.
Reviewers: gchatelet, john.brawn, jsji
Subscribers: nemanjai, mgorny, javed.absar, kbarton, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D54297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346489
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Andrea Di Biagio [Fri, 9 Nov 2018 12:29:57 +0000 (12:29 +0000)]
[llvm-mca] Use a small vector for instructions in the EntryStage.
Use a simple SmallVector to track the lifetime of simulated instructions.
An ordered map was not needed because instructions are already picked in program
order. It is also much faster if we avoid searching for already retired
instructions at the end of every cycle.
The new policy only triggers a "garbage collection" when the number of retired
instructions becomes significantly big when compared with the total size of the
vector.
While working on this, I noticed that instructions were correctly retired, but
their internal state was not updated (i.e. there was no transition from the
EXECUTED state, to the RETIRED state). While this was not a problem for the
views, it prevented the EntryStage from correctly garbage collecting already
retired instructions. That was a bad oversight, and this patch fixes it.
The observed speedup on a debug build of llvm-mca after this patch is ~6%.
On a release build of llvm-mca, the observed speedup is ~%15%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346487
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Florian Hahn [Fri, 9 Nov 2018 11:52:27 +0000 (11:52 +0000)]
[IPSCCP,PM] Preserve DT in the new pass manager.
After D45330, Dominators are required for IPSCCP and can be preserved.
This patch preserves DominatorTreeAnalysis in the new pass manager. AFAIK the legacy pass manager cannot preserve function analysis required by a module analysis.
Reviewers: davide, dberlin, chandlerc, efriedma, kuhar, NutshellySima
Reviewed By: chandlerc, kuhar, NutshellySima
Differential Revision: https://reviews.llvm.org/D47259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346486
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Alexandros Lamprineas [Fri, 9 Nov 2018 11:09:40 +0000 (11:09 +0000)]
[SelectionDAG] swap select_cc operands to enable folding
The DAGCombiner tries to SimplifySelectCC as follows:
select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4)
It can't cope with the situation of reordered operands:
select_cc(x, y, 0, 16, cc)
In that case we just need to swap the operands and invert the Condition Code:
select_cc(x, y, 16, 0, ~cc)
Differential Revision: https://reviews.llvm.org/D53236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346484
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Florian Hahn [Fri, 9 Nov 2018 10:23:46 +0000 (10:23 +0000)]
[CallSiteSplitting] Only record conditions up to the IDom(call site).
We can stop recording conditions once we reached the immediate dominator
for the block containing the call site. Conditions in predecessors of the
that node will be the same for all paths to the call site and splitting
is not beneficial.
This patch makes CallSiteSplitting dependent on the DT anlysis. because
the immediate dominators seem to be the easiest way of finding the node
to stop at.
I had to update some exiting tests, because they were checking for
conditions that were true/false on all paths to the call site. Those
should now be handled by instcombine/ipsccp.
Reviewers: davide, junbuml
Reviewed By: junbuml
Differential Revision: https://reviews.llvm.org/D44627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346483
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Clement Courbet [Fri, 9 Nov 2018 09:49:06 +0000 (09:49 +0000)]
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.
Summary:
Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources.
After HSW, it also has zero latency.
This fixes PR35606.
To reproduce:
Uops:
llvm-exegesis -mode=uops -opcode-name=VZEROUPPER
Latency:
echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=-
echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=-
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D54107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346482
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Carlos Alberto Enciso [Fri, 9 Nov 2018 09:42:10 +0000 (09:42 +0000)]
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
In SimplifyCFG when given a conditional branch that goes to BB1 and BB2, the hoisted common terminator instruction in the two blocks, caused debug line records associated with subsequent select instructions to become ambiguous. It causes the debugger to display unreachable source lines.
Differential Revision: https://reviews.llvm.org/D53390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346481
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Sam Parker [Fri, 9 Nov 2018 09:28:27 +0000 (09:28 +0000)]
[ARM] Enable mixed types in ARM CGP
Previously, during the search, all values had to have the same
'TypeSize', which is equal to number of bits of the integer type of
the icmp operand. All values in the tree had to match this size;
meaning that, if we searched from i16, we wouldn't accept i8s. A
change in type size requires zext and truncs to perform the casts so,
to allow mixed narrow types, the handling of these instructions is
now slightly different:
- we allow casts if their result or operand is <= TypeSize.
- zexts are sinks if their result > TypeSize.
- truncs are still sinks if their operand == TypeSize.
- truncs are still sources if their result == TypeSize.
The transformation bails on finding an icmp that operates on data
smaller than the current TypeSize.
Differential Revision: https://reviews.llvm.org/D54108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346480
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Sam Parker [Fri, 9 Nov 2018 09:18:00 +0000 (09:18 +0000)]
[ARM] Small reorganisation in ARMParallelDSP
A few code movement things:
- AreSymmetrical is now a method of BinOpChain.
- Created a lambda in CreateParallelMACPairs to reduce loop nesting.
- A Reduction object now gets pasted in a couple of places instead,
including CreateParallelMACPairs so it doesn't need to return a
value.
I've also added RecordSequentialLoads, which is run before the
transformation begins, and caches the interesting loads. This can then
be queried later instead of cross checking many load values.
Differential Revision: https://reviews.llvm.org/D54254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346479
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Dean Michael Berris [Fri, 9 Nov 2018 06:26:48 +0000 (06:26 +0000)]
[XRay] Improve FDR trace handling and error messaging
Summary:
This change covers a number of things spanning LLVM and compiler-rt,
which are related in a non-trivial way.
In LLVM, we have a library that handles the FDR mode even log loading,
which uses C++'s runtime polymorphism feature to better faithfully
represent the events that are written down by the FDR mode runtime. We
do this by interpreting a trace that's serliased in a common format
agreed upon by both the trace loading library and the FDR mode runtime.
This library is under active development, which consists of features
allowing us to reconstitute a higher-level event log.
This event log is used by the conversion and visualisation tools we have
for interpreting XRay traces.
One of the tools we have is a diagnostic tool in llvm-xray called
`fdr-dump` which we've been using to debug our expectations of what the
FDR runtime should be writing and what the logical FDR event log
structures are. We use this fairly extensively to reason about why some
non-trivial traces we're generating with FDR mode runtimes fail to
convert or fail to parse correctly.
One of these failures we've found in manual debugging of some of the
traces we've seen involve an inconsistency between the buffer extents (a
record indicating how many bytes to follow are part of a logical
thread's event log) and the record of the bytes written into the log --
sometimes it turns out the data could be garbage, due to buffers being
recycled, but sometimes we're seeing the buffer extent indicating a log
is "shorter" than the actual records associated with the buffer. This
case happens particularly with function entry records with a call
argument.
This change for now updates the FDR mode runtime to write the bytes for
the function call and arg record before updating the buffer extents
atomically, allowing multiple threads to see a consistent view of the
data in the buffer using the atomic counter associated with a buffer.
What we're trying to prevent here is partial updates where we see the
intermediary updates to the buffer extents (function record size then
call argument record size) becoming observable from another thread, for
instance, one doing the serialization/flushing.
To do both diagnose this issue properly, we need to be able to honour
the extents being set in the `BufferExtents` records marking the
beginning of the logical buffers when reading an FDR trace. Since LLVM
doesn't use C++'s RTTI mechanism, we instead follow the advice in the
documentation for LLVM Style RTTI
(https://llvm.org/docs/HowToSetUpLLVMStyleRTTI.html). We then rely on
this RTTI feature to ensure that our file-based record producer (our
streaming "deserializer") can honour the extents of individual buffers
as we interpret traces.
This also sets us up to be able to eventually do smart
skipping/continuation of FDR logs, seeking instead to find BufferExtents
records in cases where we find potentially recoverable errors. In the
meantime, we make this change to operate in a strict mode when reading
logical buffers with extent records.
Reviewers: mboerger
Subscribers: hiraditya, llvm-commits, jfb
Differential Revision: https://reviews.llvm.org/D54201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346473
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Max Kazantsev [Fri, 9 Nov 2018 05:39:04 +0000 (05:39 +0000)]
[NFC] Add utility function for SafetyInfo updates for moveBefore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346472
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Petr Hosek [Fri, 9 Nov 2018 03:16:53 +0000 (03:16 +0000)]
[llvm-rc] Support joined or separate spelling for /fo flag
CMake invokes rc using the joined spelling which appears to be supported
by Microsoft's rc implementation, so we should support it as well.
Differential Revision: https://reviews.llvm.org/D54191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346470
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Mandeep Singh Grang [Fri, 9 Nov 2018 02:48:36 +0000 (02:48 +0000)]
[COFF, ARM64] Add support for MSVC buffer security check
Reviewers: rnk, mstorsjo, compnerd, efriedma, TomTan
Reviewed By: rnk
Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D54248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346469
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Thomas Lively [Fri, 9 Nov 2018 01:57:00 +0000 (01:57 +0000)]
[WebAssembly] Read prefixed opcodes as ULEB128s
Summary: Depends on D54126.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346465
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Thomas Lively [Fri, 9 Nov 2018 01:49:19 +0000 (01:49 +0000)]
[WebAssembly][NFC] Reorder SIMD section
Summary:
Reorders the sections in the SIMD tablegen file to roughly match the
new opcode ordering. Depends on D54126.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346464
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Thomas Lively [Fri, 9 Nov 2018 01:45:56 +0000 (01:45 +0000)]
[WebAssembly] Renumber and LEB128-encode SIMD opcodes
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346463
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Thomas Lively [Fri, 9 Nov 2018 01:38:44 +0000 (01:38 +0000)]
[WebAssembly] Lower select for vectors
Summary:
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346462
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Jonas Devlieghere [Fri, 9 Nov 2018 01:17:22 +0000 (01:17 +0000)]
[not] Improve error reporting consistency.
Makes `not` use WithColor from Support so it prints 'error' in color
when applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346460
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Jonas Devlieghere [Fri, 9 Nov 2018 00:26:10 +0000 (00:26 +0000)]
[VFS] Add "expand tilde" argument to getRealPath.
Add an optional argument to expand tildes in the path to mirror llvm's
implementation of the corresponding function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346453
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Petr Hosek [Thu, 8 Nov 2018 23:45:00 +0000 (23:45 +0000)]
[llvm-rc] Support absolute filenames in manifests
CMake generate manifests that contain absolute filenames and these
currently result in assertion error. This change ensures that we
handle these correctly.
Differential Revision: https://reviews.llvm.org/D54194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346450
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Philip Reames [Thu, 8 Nov 2018 23:20:40 +0000 (23:20 +0000)]
[docs][statepoint] Document explicitly provided stack slots
Functionality for this was added a while ago, though never documented or extensively tested. Document it with an explicit warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346448
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Philip Reames [Thu, 8 Nov 2018 23:07:04 +0000 (23:07 +0000)]
[docs][statepoints] add a section spelling out simplifications for non-relocating GCs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346447
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Philip Reames [Thu, 8 Nov 2018 22:56:41 +0000 (22:56 +0000)]
[docs] Add some subsections to make it possible to find portions of the statepoint overview
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346446
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Heejin Ahn [Thu, 8 Nov 2018 22:56:26 +0000 (22:56 +0000)]
[WebAssembly] Fix LowerEmscriptenEHSjLj when there's only longjmp
Summary:
The pass incorrectly assumed if there's a longjmp declaration in the
module, there is also a setjmp function declaration. Fixed it, and now
the pass only converts longjmp and does not do any other transformation
when there's no setjmp declaration in the module.
Fixes PR39562.
Reviewers: jgravelle-google, sbc100
Subscribers: dschuff, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346445
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Eli Friedman [Thu, 8 Nov 2018 21:20:52 +0000 (21:20 +0000)]
[ARM64] [Windows] Improve error reporting for unsupported SEH unwind.
Use report_fatal_error instead of crashing or miscompiling. (It's
currently easier than it should be to hit this case because we don't
reuse codes across epilogs.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346440
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Florian Hahn [Thu, 8 Nov 2018 20:44:19 +0000 (20:44 +0000)]
[LoopInterchange] Support reductions across inner and outer loop.
This patch adds logic to detect reductions across the inner and outer
loop by following the incoming values of PHI nodes in the outer loop. If
the incoming values take part in a reduction in the inner loop or come
from outside the outer loop, we found a reduction spanning across inner
and outer loop.
With this change, ~10% more loops are interchanged in the LLVM
test-suite + SPEC2006.
Fixes https://bugs.llvm.org/show_bug.cgi?id=30472
Reviewers: mcrosier, efriedma, karthikthecool, davide, hfinkel, dmgreen
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346438
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Craig Topper [Thu, 8 Nov 2018 20:29:17 +0000 (20:29 +0000)]
[SelectionDAG] Assert on the width of DemandedElts argument to computeKnownBits for all vector typed operations not just build_vector.
Fix AArch64 unit test that fails with the assertion added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346437
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Pirama Arumuga Nainar [Thu, 8 Nov 2018 20:10:07 +0000 (20:10 +0000)]
[LTO] Drop non-prevailing definitions only if linkage is not local or appending
Summary:
This fixes PR 37422
In ELF, non-weak symbols can also be non-prevailing. In this particular
PR, the __llvm_profile_* symbols are non-prevailing but weren't getting
dropped - causing multiply-defined errors with lld.
Also add a test, strong_non_prevailing.ll, to ensure that multiple
copies of a strong symbol are dropped.
To fix the test regressions exposed by this fix,
- do not mark prevailing copies for symbols with 'appending' linkage.
There's no one prevailing copy for such symbols.
- fix the prevailing version in dead-strip-fulllto.ll
- explicitly pass exported symbols to llvm-lto in fumcimport.ll and
funcimport_var.ll
Reviewers: tejohnson, pcc
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith,
dang, srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D54125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346436
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