OSDN Git Service
Alexandre Ganea [Tue, 12 Dec 2017 18:00:43 +0000 (18:00 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320504
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Geoff Berry [Tue, 12 Dec 2017 17:53:59 +0000 (17:53 +0000)]
[MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).
Reviewers: qcolombet, MatzeB, hfinkel
Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503
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Alexey Bataev [Tue, 12 Dec 2017 17:35:29 +0000 (17:35 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320499 again to resolve the problem with the
sanitizers bbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320501
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Alexey Bataev [Tue, 12 Dec 2017 17:19:15 +0000 (17:19 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320499
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Alexey Bataev [Tue, 12 Dec 2017 17:08:48 +0000 (17:08 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320496 to solve the problems with sanitizer
buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320498
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Don Hinton [Tue, 12 Dec 2017 17:06:08 +0000 (17:06 +0000)]
[cmake] Support moving debuginfo-tests to llvm/projects
Differential Revision: https://reviews.llvm.org/D40972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320497
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Alexey Bataev [Tue, 12 Dec 2017 16:58:48 +0000 (16:58 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320496
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Simon Pilgrim [Tue, 12 Dec 2017 16:12:53 +0000 (16:12 +0000)]
[X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636)
The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW
Raised PR35639 and PR35643 as examples
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320492
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Alex Bradbury [Tue, 12 Dec 2017 16:10:21 +0000 (16:10 +0000)]
[RISCV][NFC] Formatting fix in RISCVInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320491
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Alexey Bataev [Tue, 12 Dec 2017 16:05:52 +0000 (16:05 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320488 because of the failed asan buildbots..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320490
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Alexey Bataev [Tue, 12 Dec 2017 15:54:49 +0000 (15:54 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320488
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Alex Bradbury [Tue, 12 Dec 2017 15:46:15 +0000 (15:46 +0000)]
[RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.
Differential Revision: https://reviews.llvm.org/D40902
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320487
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Alexey Bataev [Tue, 12 Dec 2017 15:24:17 +0000 (15:24 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320483 because of the failed Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320485
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Alex Bradbury [Tue, 12 Dec 2017 15:17:45 +0000 (15:17 +0000)]
[RISCV] MC layer support for the instructions added in the privileged spec
Adds support for the instructions added in the RISC-V privileged ISA
(https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf):
uret, sret, mret, wfi, and sfence.vma.
Note from the committer: I made very minor formatting changes prior to commit,
which didn't seem worth creating another review round-trip for.
Differential Revision: https://reviews.llvm.org/D40383
Patch by David Craven.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320484
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Alexey Bataev [Tue, 12 Dec 2017 15:03:17 +0000 (15:03 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320483
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Ayman Musa [Tue, 12 Dec 2017 14:13:51 +0000 (14:13 +0000)]
[X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction.
Recognize constant arrays with the following values:
0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1
where //size// is the size of the array.
the result of a load with index //idx// from this array is equivalent to the result of the following:
(0xFFFFFFFF >> (sub 32, idx)) (assuming the array of type 32-bit integer).
And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior.
See test cases in the LIT test for better understanding.
Differential Revision: https://reviews.llvm.org/D34141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320481
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Anna Thomas [Tue, 12 Dec 2017 14:12:33 +0000 (14:12 +0000)]
[InstComineLoadStoreAlloca] Optimize stores to GEP off null base
Summary:
Currently, in InstCombineLoadStoreAlloca, we have simplification
rules for the following cases:
1. load off a null
2. load off a GEP with null base
3. store to a null
This patch adds support for the fourth case which is store into a
GEP with null base. Since this is UB as well (and directly analogous to
the load off a GEP with null base), we can substitute the stored val
with undef in instcombine, so that SimplifyCFG can optimize this code
into unreachable code.
Note: Right now, simplifyCFG hasn't been taught about optimizing
this to unreachable and adding an llvm.trap (this is already done for
the above 3 cases).
Reviewers: majnemer, hfinkel, sanjoy, davide
Reviewed by: sanjoy, davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320480
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Nemanja Ivanovic [Tue, 12 Dec 2017 12:33:09 +0000 (12:33 +0000)]
[PowerPC] Add branch flag on asm parser-only branch instructions
This flag was missing but it wasn't an issue as nothing depended on it
for these asm parser-only instructions. Now that LLDB support is slowly
landing, it is important to get this right.
Committing on behalf of Leonardo Bianconi.
Differential revision: https://reviews.llvm.org/D40846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320475
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Nemanja Ivanovic [Tue, 12 Dec 2017 12:09:34 +0000 (12:09 +0000)]
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
The last of the three patches that https://reviews.llvm.org/D40348 was
broken up into.
Canonicalize the materialization of constants so that they are more likely
to be CSE'd regardless of the bit-width of the use. If a constant can be
materialized using PPC::LI, materialize it the same way always.
For example:
li 4, -1
li 4, 255
li 4, 65535
are equivalent if the uses only use the low byte. Canonicalize it to the
first form.
Differential Revision: https://reviews.llvm.org/D40348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320473
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Simon Pilgrim [Tue, 12 Dec 2017 11:34:25 +0000 (11:34 +0000)]
Revert r320461 - causing ICE in windows buildss
[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320470
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Jonas Devlieghere [Tue, 12 Dec 2017 11:32:21 +0000 (11:32 +0000)]
[dsymutil] Accept line tables up to DWARFv5.
This patch removes the hard-coded check for DWARFv2 line tables. Now
dsymutil accepts line tables for DWARF versions 2 to 5 (inclusive).
Differential revision: https://reviews.llvm.org/D41084
rdar://
35968319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320469
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Eugene Leviant [Tue, 12 Dec 2017 10:12:46 +0000 (10:12 +0000)]
Revert r320464 as it breaks gold plugin tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320467
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Igor Laevsky [Tue, 12 Dec 2017 10:03:39 +0000 (10:03 +0000)]
Revert r320049, r320014 and r319894
They were causing failures of the piglit OpenGL tests with AMD GPUs using the
Mesa radeonsi driver.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320466
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Serguei Katkov [Tue, 12 Dec 2017 09:44:41 +0000 (09:44 +0000)]
[NFC][SafepointIRVerifier] Add alias for set of available values
Introduces usage of AvailableValueSet alias name instead of
DenseSet<const Value *> for better reading.
Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320465
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Eugene Leviant [Tue, 12 Dec 2017 09:12:32 +0000 (09:12 +0000)]
[ThinLTO] Remove unused code from thinLTOInternalizeModule
Differential revision: https://reviews.llvm.org/D40970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320464
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Dorit Nuzman [Tue, 12 Dec 2017 08:57:43 +0000 (08:57 +0000)]
[LV] Ignore the cost of values that will not appear in the vectorized loop
VecValuesToIgnore holds values that will not appear in the vectorized loop.
We should therefore ignore their cost when VF > 1.
Differential Revision: https://reviews.llvm.org/D40883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320463
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Craig Topper [Tue, 12 Dec 2017 08:17:04 +0000 (08:17 +0000)]
[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320461
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Mikael Holmen [Tue, 12 Dec 2017 07:29:57 +0000 (07:29 +0000)]
[CallSiteSplitting] Don't let debug intrinsics affect optimizations
Summary:
This solves PR35616.
We don't want the compiler to generate different code when we compile
with/without -g, so we now ignore debug intrinsics when determining if
the optimization can trigger or not.
Reviewers: junbuml
Subscribers: davide, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320460
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Craig Topper [Tue, 12 Dec 2017 07:06:35 +0000 (07:06 +0000)]
[X86] Use Ld scheduler classes for instructions with folded loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320459
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Craig Topper [Tue, 12 Dec 2017 07:06:32 +0000 (07:06 +0000)]
[X86] Correct the FMA3 regular expressions in the znver1 scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320458
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Tony Tye [Tue, 12 Dec 2017 05:47:00 +0000 (05:47 +0000)]
[AMDGPU] Rename Bonaire target to be gfx704; remove gfx800 and make Iceland and Tonga both use gfx802; update target feature handling
Correct committed version to match intended accepted review D40051 id=123417
- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.
Differential Revision: https://reviews.llvm.org/D40051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320457
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Vedant Kumar [Mon, 11 Dec 2017 23:34:50 +0000 (23:34 +0000)]
[llvm-cov] Simplify a test case. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320439
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Max Moroz [Mon, 11 Dec 2017 23:17:46 +0000 (23:17 +0000)]
[llvm-cov] Add an option for "export" command to emit only file summary data.
Summary:
That allows to get the same data as produced by "llvm-cov report",
but in JSON format, which is better for further processing by end users.
Reviewers: vsk
Reviewed By: vsk
Differential Revision: https://reviews.llvm.org/D41085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320435
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Sam Clegg [Mon, 11 Dec 2017 23:03:38 +0000 (23:03 +0000)]
Reland "[WebAssembly] Import the linear memory and function table."
Original change: https://reviews.llvm.org/D40875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320432
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Richard Trieu [Mon, 11 Dec 2017 22:25:04 +0000 (22:25 +0000)]
Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion
See bug https://bugs.llvm.org/show_bug.cgi?id=35631
r318704 is giving a fatal error on some code with unsigned to floating point
conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320429
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Matt Arsenault [Mon, 11 Dec 2017 21:38:43 +0000 (21:38 +0000)]
LSR: Check more intrinsic pointer operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320424
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Hans Wennborg [Mon, 11 Dec 2017 21:15:27 +0000 (21:15 +0000)]
Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
The tests fail (opt asserts) on Windows.
> Summary:
> If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
> &V2)))), bitcast)`, but the load is used in other instructions, it leads
> to looping in InstCombiner. Patch adds additional check that all users
> of the load instructions are stores and then replaces all uses of load
> instruction by the new one with new type.
>
> Reviewers: RKSimon, spatel, majnemer
>
> Subscribers: llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320421
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Evandro Menezes [Mon, 11 Dec 2017 21:09:27 +0000 (21:09 +0000)]
[CodeGen] Improve the consistency of instruction fusion*
When either instruction in a fused pair has no other dependency, besides on
the other instruction, make sure that other instructions do not get
scheduled between them. Additionally, avoid fusing an instruction more than
once along the same dependency chain.
Differential revision: https://reviews.llvm.org/D36704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320420
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Adrian Prantl [Mon, 11 Dec 2017 20:43:21 +0000 (20:43 +0000)]
ASAN: Provide reliable debug info for local variables at -O0.
The function stack poisioner conditionally stores local variables
either in an alloca or in malloc'ated memory, which has the
unfortunate side-effect, that the actual address of the variable is
only materialized when the variable is accessed, which means that
those variables are mostly invisible to the debugger even when
compiling without optimizations.
This patch stores the address of the local stack base into an alloca,
which can be referred to by the debug info and is available throughout
the function. This adds one extra pointer-sized alloca to each stack
frame (but mem2reg can optimize it away again when optimizations are
enabled, yielding roughly the same debug info quality as before in
optimized code).
rdar://problem/
30433661
Differential Revision: https://reviews.llvm.org/D41034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320415
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Tony Jiang [Mon, 11 Dec 2017 20:42:37 +0000 (20:42 +0000)]
[PowerPC] Partially enable the ISEL expansion pass.
The pass to expand ISEL instructions into if-then-else sequences in patch D23630
is currently disabled. This patch partially enable it by always removing the
unnecessary ISELs (all registers used by the ISELs are the same one) and folding
the ISELs which have the same input registers into unconditional copies.
Differential Revision: https://reviews.llvm.org/D40497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320414
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Justin Bogner [Mon, 11 Dec 2017 19:53:23 +0000 (19:53 +0000)]
[cmake] Pass TARGETS_TO_BUILD through to host tools build
In r319620, the host build was changed to use Native for
TARGETS_TO_BUILD because passing semicolons through add_custom_command
is surprisingly difficult. However, Native really doesn't make any
sense here, and it only works because we don't technically do any
codegen in the host tools so pretty well anything will "work".
The problem here is that passing something other than the correct
value is very fragile - as evidence note how the llvm-config in the
host tools acts differently than the target one now, and misreports
the targets to build. Similarly, if there is any logic conditional on
the targets in tablegen (now or in the future), it will do the wrong
thing.
To fix this, we need to escape the semicolons in the targets string
and pass it through to the child cmake invocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320413
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George Burgess IV [Mon, 11 Dec 2017 19:22:59 +0000 (19:22 +0000)]
Ensure moved-from container is cleared on move
In all cases except for this optimistic attempt to reuse memory, the
moved-from TinyPtrVector was left `empty()` at the end of this
assignment. Though using a container after it's been moved from can be a
bit sketchy, it's probably best to just be consistent here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320408
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Alexey Bataev [Mon, 11 Dec 2017 19:11:16 +0000 (19:11 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320407
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Krzysztof Parzyszek [Mon, 11 Dec 2017 18:57:54 +0000 (18:57 +0000)]
[Hexagon] Add support for Hexagon V65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320404
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Simon Pilgrim [Mon, 11 Dec 2017 18:39:42 +0000 (18:39 +0000)]
[X86] Add LODS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320403
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Simon Pilgrim [Mon, 11 Dec 2017 18:32:59 +0000 (18:32 +0000)]
[X86] Add CMP/TEST schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320402
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Simon Pilgrim [Mon, 11 Dec 2017 18:23:24 +0000 (18:23 +0000)]
[X86] Add AND/OR/XOR schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320400
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Jonas Devlieghere [Mon, 11 Dec 2017 18:22:47 +0000 (18:22 +0000)]
[dwarfdump] Fix off-by-one bug in accelerator table extractor.
This fixes a bug where the verifier was complaining about empty
accelerator tables. When the table is empty, its size is not a valid
offset as it points after the end of the section.
This patch also makes the extractor return llvm:Error instead of bool
for better error reporting in the verifier.
Differential revision: https://reviews.llvm.org/D41063
rdar://
35932007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320399
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Simon Pilgrim [Mon, 11 Dec 2017 18:13:40 +0000 (18:13 +0000)]
[X86] Add ADD/SUB schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320397
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Simon Pilgrim [Mon, 11 Dec 2017 17:59:05 +0000 (17:59 +0000)]
[X86] Add ADC/SBB schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320395
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Simon Pilgrim [Mon, 11 Dec 2017 17:37:08 +0000 (17:37 +0000)]
[X86] Add MOVSLQ schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320392
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Simon Pilgrim [Mon, 11 Dec 2017 17:01:21 +0000 (17:01 +0000)]
Normalize line endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320389
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Amara Emerson [Mon, 11 Dec 2017 16:58:29 +0000 (16:58 +0000)]
[GlobalISel] Disable GISel for big endian.
This is due to PR26161 needing to be resolved before we can fix
big endian bugs like PR35359. The work to split aggregates into smaller LLTs
instead of using one large scalar will take some time, so in the mean time
we'll fall back to SDAG.
Some ARM BE tests xfailed for now as a result.
Differential Revision: https://reviews.llvm.org/D40789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320388
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Simon Pilgrim [Mon, 11 Dec 2017 16:47:21 +0000 (16:47 +0000)]
[X86] Add LWP schedule tests
Tag LWP instructions as WriteSystem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320387
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Simon Pilgrim [Mon, 11 Dec 2017 16:32:58 +0000 (16:32 +0000)]
[X86] Add INT/INTO schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320386
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Simon Pilgrim [Mon, 11 Dec 2017 16:16:40 +0000 (16:16 +0000)]
[X86] Add IN/OUT schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320385
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Simon Pilgrim [Mon, 11 Dec 2017 16:08:21 +0000 (16:08 +0000)]
[X86] Add IDIV schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320384
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Simon Pilgrim [Mon, 11 Dec 2017 16:04:08 +0000 (16:04 +0000)]
[X86] Add CMPXCHG schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320383
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Simon Pilgrim [Mon, 11 Dec 2017 15:53:12 +0000 (15:53 +0000)]
[X86] Add CLZERO schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320382
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Alexander Potapenko [Mon, 11 Dec 2017 15:48:56 +0000 (15:48 +0000)]
[MSan] Hotfix compilation
For some reason the override directives got removed in r320373.
I suspect this to be an unwanted effect of clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320381
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Simon Pilgrim [Mon, 11 Dec 2017 15:41:52 +0000 (15:41 +0000)]
[X86] Add ADCX/ADOX/XADD/XLAT schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320380
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Nirav Dave [Mon, 11 Dec 2017 15:35:40 +0000 (15:35 +0000)]
[X86] Modify Nontemporal tests to avoid deadstore optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320379
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Tony Tye [Mon, 11 Dec 2017 15:35:27 +0000 (15:35 +0000)]
[AMDGPU] Rename Bonaire target to be gfx704; update target feature handling
- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.
Differential Revision: https://reviews.llvm.org/D40051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320378
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Simon Pilgrim [Mon, 11 Dec 2017 15:25:31 +0000 (15:25 +0000)]
[X86] Add SETCC/STC/STD/UD2 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320376
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Dmitry Preobrazhensky [Mon, 11 Dec 2017 15:23:20 +0000 (15:23 +0000)]
[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559
Reviewers: vpykhtin, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320375
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Sanjay Patel [Mon, 11 Dec 2017 15:19:31 +0000 (15:19 +0000)]
[DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)
At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap())
to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some
element types, but...it's difficult.
Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG
combine and preserve all of the existing behavior AFAICT otherwise.
Some tests that will probably fail if someone does try to restrict this in a more targeted way
for x86-only may be found in:
test/CodeGen/X86/combine-mul.ll
test/CodeGen/X86/vector-mul.ll
test/CodeGen/X86/widen_arith-5.ll
This should prevent the infinite looping seen with:
https://bugs.llvm.org/show_bug.cgi?id=35579
Differential Revision: https://reviews.llvm.org/D41040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320374
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Alexander Potapenko [Mon, 11 Dec 2017 15:05:22 +0000 (15:05 +0000)]
[MSan] introduce getShadowOriginPtr(). NFC.
This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair.
The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr().
The rationale for this change is to simplify KMSAN instrumentation implementation.
In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages.
Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation,
therefore it's easier to work with those pointers together.
Reviewed at https://reviews.llvm.org/D40835.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320373
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Simon Pilgrim [Mon, 11 Dec 2017 14:56:44 +0000 (14:56 +0000)]
[X86] Add SAR/SHL/SHR schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320371
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Simon Pilgrim [Mon, 11 Dec 2017 14:46:42 +0000 (14:46 +0000)]
[X86] Add RCL/RCR schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320370
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Krzysztof Parzyszek [Mon, 11 Dec 2017 14:46:06 +0000 (14:46 +0000)]
[Hexagon] Crash in instruction selection for insert_vector_elt for HVX
A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320369
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Nemanja Ivanovic [Mon, 11 Dec 2017 14:35:48 +0000 (14:35 +0000)]
[PowerPC] Sign-extend negative constant stores
Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320368
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Nemanja Ivanovic [Mon, 11 Dec 2017 14:16:02 +0000 (14:16 +0000)]
[DAGCombiner] Add combined indexed load to the work list
This commit is the first part of https://reviews.llvm.org/D40348.
In order to allow target combines to be performed on newly combined
indexed loads, add them back to the worklist. The remainder of the
above patch will be committed in subsequent revisions and will use
this. Test cases will be included with those follow-up commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320365
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Diana Picus [Mon, 11 Dec 2017 13:28:45 +0000 (13:28 +0000)]
[ARM GlobalISel] Add test for a MOVTi16 pattern. NFC
Add test for matching an OR with 0xFFFF0000 to a MOVTi16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320362
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Simon Pilgrim [Mon, 11 Dec 2017 13:25:02 +0000 (13:25 +0000)]
[X86] Add fsgsbase schedule tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320361
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Alex Bradbury [Mon, 11 Dec 2017 12:49:02 +0000 (12:49 +0000)]
[RISCV] Add custom CC_RISCV calling convention and improved call support
The TableGen-based calling convention definitions are inflexible, while
writing a function to implement the calling convention is very
straight-forward, and allows difficult cases to be handled more easily. With
this patch adds support for:
* Passing large scalars according to the RV32I calling convention
* Byval arguments
* Passing values on the stack when the argument registers are exhausted
The custom CC_RISCV calling convention is also used for returns.
This patch also documents the ABI lowering that a language frontend is
expected to perform. I would like to work to simplify these requirements over
time, but this will require further discussion within the LLVM community.
We add PendingArgFlags CCState, as a companion to PendingLocs.
The PendingLocs vector is used by a number of backends to handle arguments
that are split during legalisation. However CCValAssign doesn't keep track of
the original argument alignment. Therefore, add a PendingArgFlags vector which
can be used to keep track of the ISD::ArgFlagsTy for every value added to
PendingLocs.
Differential Revision: https://reviews.llvm.org/D39898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320359
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Alex Bradbury [Mon, 11 Dec 2017 12:38:17 +0000 (12:38 +0000)]
[RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320358
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Alex Bradbury [Mon, 11 Dec 2017 12:34:11 +0000 (12:34 +0000)]
[RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot of the
RISC-V tests.
Differential Revision: https://reviews.llvm.org/D39849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320357
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Simon Pilgrim [Mon, 11 Dec 2017 12:22:15 +0000 (12:22 +0000)]
[X86] Regenerate fsgsbase intrinsic tests. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320356
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Roger Ferrer Ibanez [Mon, 11 Dec 2017 12:13:45 +0000 (12:13 +0000)]
[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515.
This change:
- makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
- lowering is done by first converting the boolean value into the carry flag
using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
operations does the actual addition.
- for subtraction, given that ISD::SUBCARRY second result is actually a
borrow, we need to invert the value of the second operand and result before
and after using ARMISD::SUBE. We need to invert the carry result of
ARMISD::SUBE to preserve the semantics.
- given that the generic combiner may lower ISD::ADDCARRY and
ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
as well otherwise i64 operations now would require branches. This implies
updating the corresponding test for unsigned.
- add new combiner to remove the redundant conversions from/to carry flags
to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
- fixes PR34045
- fixes PR34564
- fixes PR35103
Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320355
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Alex Bradbury [Mon, 11 Dec 2017 11:53:54 +0000 (11:53 +0000)]
[RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because
it's not possible to write a pattern that directly matches a frameindex.
Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.
Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can
make use of it in the RISC-V backend.
Differential Revision: https://reviews.llvm.org/D39848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320353
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Diana Picus [Mon, 11 Dec 2017 11:44:23 +0000 (11:44 +0000)]
[ARM GlobalISel] Add tests for PKHBT and PKHTB
Test (some of) the patterns for selecting PKHBT and PKHTB. The others
are just very similar to the ones we're testing and there would be
little value in covering them as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320352
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Aleksandar Beserminji [Mon, 11 Dec 2017 11:21:40 +0000 (11:21 +0000)]
[mips] Removal of microMIPS64R6
All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.
This is LLVM part of patch.
Differential Revision: https://reviews.llvm.org/D35625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320350
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Dylan McKay [Mon, 11 Dec 2017 11:01:27 +0000 (11:01 +0000)]
[AVR] Implement some missing code paths
This has been broken since r320009.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320348
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Dylan McKay [Mon, 11 Dec 2017 11:01:19 +0000 (11:01 +0000)]
[AVR] Fix incorrectly-calculated AVRMCExpr evaluations
This has been broken since r320009.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320347
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Craig Topper [Mon, 11 Dec 2017 08:33:20 +0000 (08:33 +0000)]
[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.
We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320344
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Craig Topper [Mon, 11 Dec 2017 08:33:19 +0000 (08:33 +0000)]
[DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320343
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Craig Topper [Mon, 11 Dec 2017 06:16:26 +0000 (06:16 +0000)]
[X86] Regenerate test with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320342
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Craig Topper [Mon, 11 Dec 2017 01:48:10 +0000 (01:48 +0000)]
[X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 while other types are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320340
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Simon Pilgrim [Sun, 10 Dec 2017 22:11:56 +0000 (22:11 +0000)]
[X86] Add ROL/ROR schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320334
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Simon Pilgrim [Sun, 10 Dec 2017 21:56:24 +0000 (21:56 +0000)]
[X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320333
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Simon Pilgrim [Sun, 10 Dec 2017 21:28:00 +0000 (21:28 +0000)]
[X86] Add DEC/INC schedule tests
Include i686 (non-REX) variant tests as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320332
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Simon Pilgrim [Sun, 10 Dec 2017 21:10:28 +0000 (21:10 +0000)]
[X86] Add INS/OUTS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320331
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Simon Pilgrim [Sun, 10 Dec 2017 20:58:22 +0000 (20:58 +0000)]
[X86] Add CMPS/MOVS/SCAS/STOS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320330
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Simon Pilgrim [Sun, 10 Dec 2017 20:46:57 +0000 (20:46 +0000)]
[X86] Add CMOV schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320329
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Simon Pilgrim [Sun, 10 Dec 2017 20:22:47 +0000 (20:22 +0000)]
[X86] Add BT/BTC/BTR/BTS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320328
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Craig Topper [Sun, 10 Dec 2017 19:47:57 +0000 (19:47 +0000)]
[X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320326
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Craig Topper [Sun, 10 Dec 2017 19:47:56 +0000 (19:47 +0000)]
[X86] Rename some instructions that start with Int_ to have the _Int at the end.
This matches AVX512 version and is more consistent overall. And improves our scheduler models.
In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320325
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Simon Pilgrim [Sun, 10 Dec 2017 19:19:22 +0000 (19:19 +0000)]
[X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320322
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Simon Pilgrim [Sun, 10 Dec 2017 18:53:15 +0000 (18:53 +0000)]
[X86][X87] Add missing x87 scheduler tests
Split off some 'n' instruction versions to make it clearer when WAIT is being inserted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320321
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Craig Topper [Sun, 10 Dec 2017 17:42:44 +0000 (17:42 +0000)]
[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.
Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320320
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